ES2111465B1 - Filtro de decimacion que usa un circuito de relleno como ceros para suministrar una razon de decimacion seleccionable. - Google Patents

Filtro de decimacion que usa un circuito de relleno como ceros para suministrar una razon de decimacion seleccionable.

Info

Publication number
ES2111465B1
ES2111465B1 ES09501230A ES9501230A ES2111465B1 ES 2111465 B1 ES2111465 B1 ES 2111465B1 ES 09501230 A ES09501230 A ES 09501230A ES 9501230 A ES9501230 A ES 9501230A ES 2111465 B1 ES2111465 B1 ES 2111465B1
Authority
ES
Spain
Prior art keywords
decimation
accumulator
filling circuit
filter
reason
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
ES09501230A
Other languages
English (en)
Other versions
ES2111465A1 (es
Inventor
Daniel Arthur Staver
Donald Thomas Mcgrath
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
General Electric Co
Original Assignee
General Electric Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by General Electric Co filed Critical General Electric Co
Publication of ES2111465A1 publication Critical patent/ES2111465A1/es
Application granted granted Critical
Publication of ES2111465B1 publication Critical patent/ES2111465B1/es
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M7/00—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits
    • H03M7/30—Compression; Expansion; Suppression of unnecessary data, e.g. redundancy reduction
    • H03M7/3002—Conversion to or from differential modulation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H17/00—Networks using digital techniques
    • H03H17/02—Frequency selective networks
    • H03H17/06—Non-recursive filters
    • H03H17/0621—Non-recursive filters with input-sampling frequency and output-delivery frequency which differ, e.g. extrapolation; Anti-aliasing
    • H03H17/0635—Non-recursive filters with input-sampling frequency and output-delivery frequency which differ, e.g. extrapolation; Anti-aliasing characterized by the ratio between the input-sampling and output-delivery frequencies
    • H03H17/065—Non-recursive filters with input-sampling frequency and output-delivery frequency which differ, e.g. extrapolation; Anti-aliasing characterized by the ratio between the input-sampling and output-delivery frequencies the ratio being integer
    • H03H17/0664—Non-recursive filters with input-sampling frequency and output-delivery frequency which differ, e.g. extrapolation; Anti-aliasing characterized by the ratio between the input-sampling and output-delivery frequencies the ratio being integer where the output-delivery frequency is lower than the input sampling frequency, i.e. decimation

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Mathematical Physics (AREA)
  • Theoretical Computer Science (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)
  • Analogue/Digital Conversion (AREA)

Abstract

FILTRO DE DECIMACION QUE USA UN CIRCUITO DE RELLENO CON CEROS PARA SUMINISTRAR UNA RAZON DE DECIMACION SELECCIONABLE. UN FILTRO DE DECIMACION PARA FILTRAR UNA CORRIENTE DE SEÑALES ELECTRICAS CUANTIFICADAS DE PROCEDENCIA EXTERNA QUE COMPRENDE UN GENERADOR DE COEFICIENTES SENSIBLE A UN CONJUNTO DE SEÑALES DE SELECCION DE RAZON-DECIMACION DE PROCEDENCIA EXTERNA PARA SUMINISTRAR UNA SEÑAL DEL COEFICIENTE NORMALIZADO DISTINTA EN CADA PUERTO RESPECTIVO DE UNA PLURALIDAD DE PUERTOS DE SALIDA. EL GENERADOR DE COEFICIENTES EMPLEA UN CIRCUITO DE RELLENO CON CEROS PARA SUMINISTRAR LAS SEÑALES DE COEFICIENTES NORMALIZADOS. UN ACUMULADOR ESTA ACOPLADO AL GENERADOR DE COEFICIENTES PARA RECIBIR CADA UNA DE LAS SEÑALES DE COEFICIENTES NORMALIZADOS GENERADAS EN EL MISMO. EL ACUMULADOR RECIBE LA CORRIENTE DE SEÑALES ELECTRICAS CUANTIFICADAS PRODUCIENDO UNA PLURALIDAD DE SEÑALES DE SALIDA DEL ACUMULADOR. UN DETECTOR DE DESBORDAMIENTO DE CAPACIDAD ESTA ACOPLADO AL ACUMULADOR PARA DETECTAR Y CORREGIR CUALQUIERCONDICION DE DESBORDAMIENTO QUE SE PRODUZCA EN EL ACUMULADOR.
ES09501230A 1994-06-24 1995-06-20 Filtro de decimacion que usa un circuito de relleno como ceros para suministrar una razon de decimacion seleccionable. Expired - Fee Related ES2111465B1 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/265,343 US5463569A (en) 1994-06-24 1994-06-24 Decimation filter using a zero-fill circuit for providing a selectable decimation ratio

Publications (2)

Publication Number Publication Date
ES2111465A1 ES2111465A1 (es) 1998-03-01
ES2111465B1 true ES2111465B1 (es) 1998-10-01

Family

ID=23010046

Family Applications (1)

Application Number Title Priority Date Filing Date
ES09501230A Expired - Fee Related ES2111465B1 (es) 1994-06-24 1995-06-20 Filtro de decimacion que usa un circuito de relleno como ceros para suministrar una razon de decimacion seleccionable.

Country Status (5)

Country Link
US (1) US5463569A (es)
KR (1) KR100338971B1 (es)
DE (1) DE19521610B4 (es)
ES (1) ES2111465B1 (es)
TW (1) TW252239B (es)

Families Citing this family (13)

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Publication number Priority date Publication date Assignee Title
US5677845A (en) * 1995-06-02 1997-10-14 General Electric Company Programmable data acquisition system for collecting electrical power signals
CA2157690A1 (en) * 1995-09-07 1997-03-08 Bosco Leung Lower power passive sigma-delta converter
DE19639410A1 (de) 1996-09-25 1998-04-02 Siemens Ag Meßeinrichtung für elektrische Leistung
US5880973A (en) * 1996-11-20 1999-03-09 Graychip Inc. Signal processing system and method for enhanced cascaded integrator-comb interpolation filter stabilization
US6202198B1 (en) 1998-04-21 2001-03-13 Neoprobe Corporation Programmable integrated analog input/output circuit with distributed matching memory array
GB9813982D0 (en) * 1998-06-30 1998-08-26 Mem Limited Residual current detection device
AU6275499A (en) * 1999-09-29 2001-04-30 Ohio State University Research Foundation, The A programmable integrated analog input/output circuit with distributed matching memory array
JP2001285863A (ja) * 2000-03-30 2001-10-12 Sony Corp 画像情報変換装置及び方法
DE102007054951A1 (de) * 2007-11-17 2009-05-20 Conti Temic Microelectronic Gmbh Sigma-Delta-Wandler zur Digitalisierung eines analogen Signals
US9002917B2 (en) * 2010-07-30 2015-04-07 National Instruments Corporation Generating filter coefficients for a multi-channel notch rejection filter
JP5812774B2 (ja) * 2011-09-08 2015-11-17 ルネサスエレクトロニクス株式会社 半導体装置
KR102192991B1 (ko) * 2014-04-23 2020-12-18 삼성전자주식회사 가변적인 디지털 필터를 포함하는 아날로그-디지털 컨버터 및 이를 포함하는 이미지 센서
US9712348B1 (en) * 2016-01-15 2017-07-18 Avago Technologies General Ip (Singapore) Pte. Ltd. System, device, and method for shaping transmit noise

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4547726A (en) * 1983-08-01 1985-10-15 General Electric Company Means and method for measuring power system frequency
US4723216A (en) * 1985-08-01 1988-02-02 General Electric Company Digital frequency-locked loop for use with staggered sampling systems
US4715000A (en) * 1985-08-06 1987-12-22 General Electric Company Digital phase-locked loop and frequency measuring device
US4937577A (en) * 1986-02-14 1990-06-26 Microchip Technology Inc. Integrated analog-to-digital converter
JP2600236B2 (ja) * 1987-12-29 1997-04-16 ソニー株式会社 サンプリング周波数変換回路
US4896156A (en) * 1988-10-03 1990-01-23 General Electric Company Switched-capacitance coupling networks for differential-input amplifiers, not requiring balanced input signals
US4951052A (en) * 1989-07-10 1990-08-21 General Electric Company Correction of systematic error in an oversampled analog-to-digital converter
JPH0772864B2 (ja) * 1990-05-11 1995-08-02 パイオニア株式会社 ディジタル信号プロセッサ
EP0476215B1 (en) * 1990-09-18 1995-12-13 ALCATEL BELL Naamloze Vennootschap Multi-channel decimator
JP2591864B2 (ja) * 1991-01-30 1997-03-19 日本電気アイシーマイコンシステム株式会社 ディジタルフィルタ
US5349676A (en) * 1991-02-11 1994-09-20 General Electric Company Data acquisition systems with programmable bit-serial digital signal processors
US5157395A (en) * 1991-03-04 1992-10-20 Crystal Semiconductor Corporation Variable decimation architecture for a delta-sigma analog-to-digital converter
US5126961A (en) * 1991-03-06 1992-06-30 General Electric Company Plural-channel decimation filter, as for sigma-delta analog-to-digital converters
US5301121A (en) * 1991-07-11 1994-04-05 General Electric Company Measuring electrical parameters of power line operation, using a digital computer
JP3042125B2 (ja) * 1992-01-13 2000-05-15 日本電気株式会社 間引きフィルタ
US5181033A (en) * 1992-03-02 1993-01-19 General Electric Company Digital filter for filtering and decimating delta sigma modulator output signals

Also Published As

Publication number Publication date
DE19521610B4 (de) 2005-12-22
KR960003115A (ko) 1996-01-26
KR100338971B1 (ko) 2002-10-31
DE19521610A1 (de) 1996-01-04
ES2111465A1 (es) 1998-03-01
TW252239B (en) 1995-07-21
US5463569A (en) 1995-10-31

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