ES2101627B1 - Circuito integrado traductor para red de banda ancha. - Google Patents
Circuito integrado traductor para red de banda ancha.Info
- Publication number
- ES2101627B1 ES2101627B1 ES09400814A ES9400814A ES2101627B1 ES 2101627 B1 ES2101627 B1 ES 2101627B1 ES 09400814 A ES09400814 A ES 09400814A ES 9400814 A ES9400814 A ES 9400814A ES 2101627 B1 ES2101627 B1 ES 2101627B1
- Authority
- ES
- Spain
- Prior art keywords
- stage
- broadband network
- translator circuit
- integrated
- integrated translator
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/54—Store-and-forward switching systems
- H04L12/56—Packet switching systems
- H04L12/5601—Transfer mode dependent, e.g. ATM
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/30—Peripheral units, e.g. input or output ports
- H04L49/3081—ATM peripheral units, e.g. policing, insertion or extraction
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q11/00—Selecting arrangements for multiplex systems
- H04Q11/04—Selecting arrangements for multiplex systems for time-division multiplexing
- H04Q11/0428—Integrated services digital network, i.e. systems for transmission of different types of digitised signals, e.g. speech, data, telecentral, television signals
- H04Q11/0478—Provisions for broadband connections
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/54—Store-and-forward switching systems
- H04L12/56—Packet switching systems
- H04L12/5601—Transfer mode dependent, e.g. ATM
- H04L2012/5614—User Network Interface
- H04L2012/5616—Terminal equipment, e.g. codecs, synch.
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/54—Store-and-forward switching systems
- H04L12/56—Packet switching systems
- H04L12/5601—Transfer mode dependent, e.g. ATM
- H04L2012/5638—Services, e.g. multimedia, GOS, QOS
- H04L2012/5646—Cell characteristics, e.g. loss, delay, jitter, sequence integrity
- H04L2012/5649—Cell delay or jitter
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/54—Store-and-forward switching systems
- H04L12/56—Packet switching systems
- H04L12/5601—Transfer mode dependent, e.g. ATM
- H04L2012/5638—Services, e.g. multimedia, GOS, QOS
- H04L2012/5646—Cell characteristics, e.g. loss, delay, jitter, sequence integrity
- H04L2012/5652—Cell construction, e.g. including header, packetisation, depacketisation, assembly, reassembly
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/54—Store-and-forward switching systems
- H04L12/56—Packet switching systems
- H04L12/5601—Transfer mode dependent, e.g. ATM
- H04L2012/5672—Multiplexing, e.g. coding, scrambling
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/54—Store-and-forward switching systems
- H04L12/56—Packet switching systems
- H04L12/5601—Transfer mode dependent, e.g. ATM
- H04L2012/5678—Traffic aspects, e.g. arbitration, load balancing, smoothing, buffer management
- H04L2012/568—Load balancing, smoothing or shaping
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S370/00—Multiplex communications
- Y10S370/901—Wide area network
- Y10S370/902—Packet switching
- Y10S370/903—Osi compliant network
- Y10S370/905—Asynchronous transfer mode, ASN
Abstract
CIRCUITO INTEGRADO TRADUCTOR PARA RED DE BANDA ANCHA. EL CIRCUITO INTEGRADO TRADUCTOR PARA RED DE BANDA ANCHA, CONSISTE EN UN CIRCUITO QUE SE CONFIGURA A PARTIR DE UNA ETAPA DE ENTRADA (1), UN DETECTOR DE CELULAS VACIAS Y UN FILTRO (2), UNA ETAPA DEL CALCULO DE CONTROL (3), UN EXTRACTOR DE LA DIRECCION DE PAGINA (4), UN PROCESADOR DE CABECERA (5), UNA ETAPA DE RETARDO (13), UNA ETAPA DE SALIDA (6), UN INTERFAZ CON EL MICROPROCESADOR (7), UNA ETAPA DE INSERCION (8), UN INTERFAZ DE MEMORIAS EXTERNAS (9) Y UNA ETAPA DE EXTRACCION (10), MODIFICANDO LA ETAPA DE ENTRADA LA CABECERA DE LAS CELULAS DEL FLUJO DE DATOS (11), ADAPTANDOLAS CON OBJETO DE IMPLEMENTAR LAS FUNCIONES DE LA CAPA MTA PARA EL TRATAMIENTO DE DATOS, MIENTRAS QUE EL PROCESADOR DE CABECERA (5) EN COLABORACION CON LAS MEMORIAS EXTERNAS (13) REALIZA LA TRADUCCION DE LAS CABECERAS DE LAS CELULAS DE ACUERDO CON LA PROGRAMACION INDICADA PARA EL ELEMENTO DE RED EN QUE SE ENCUENTRA.
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
ES09400814A ES2101627B1 (es) | 1994-04-19 | 1994-04-19 | Circuito integrado traductor para red de banda ancha. |
CA002146691A CA2146691C (en) | 1994-04-19 | 1995-04-10 | Translator chip for a wideband network |
EP95500049A EP0678998A3 (en) | 1994-04-19 | 1995-04-10 | Translator chip for a wideband network |
PE1995266359A PE25896A1 (es) | 1994-04-19 | 1995-04-12 | Circuito integrado traductor para red de banda ancha |
US08/815,998 US5777995A (en) | 1994-04-19 | 1997-03-10 | Translator chip for a wideband network |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
ES09400814A ES2101627B1 (es) | 1994-04-19 | 1994-04-19 | Circuito integrado traductor para red de banda ancha. |
Publications (2)
Publication Number | Publication Date |
---|---|
ES2101627A1 ES2101627A1 (es) | 1997-07-01 |
ES2101627B1 true ES2101627B1 (es) | 1998-03-01 |
Family
ID=8285928
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
ES09400814A Expired - Fee Related ES2101627B1 (es) | 1994-04-19 | 1994-04-19 | Circuito integrado traductor para red de banda ancha. |
Country Status (5)
Country | Link |
---|---|
US (1) | US5777995A (es) |
EP (1) | EP0678998A3 (es) |
CA (1) | CA2146691C (es) |
ES (1) | ES2101627B1 (es) |
PE (1) | PE25896A1 (es) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
ES2160049A1 (es) * | 1999-04-22 | 2001-10-16 | Telefonica Sa | Conmutador de paquetes para un red con modo de transferencias asincrono. |
ES2160061A1 (es) * | 1999-07-06 | 2001-10-16 | Telefonica Sa | Procesador en modo de transferencia asincrona de entrada y salida a un conmutador. |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2884035B1 (fr) * | 2005-04-04 | 2007-06-22 | St Microelectronics Sa | Interfacage de cicrcuits dans un circuit electronique integre |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4792899A (en) * | 1987-01-02 | 1988-12-20 | Motorola, Inc. | Microprocessor support integrated circuit |
FR2659513A1 (fr) * | 1990-03-12 | 1991-09-13 | Cit Alcatel | Installation terminale d'abonne pour reseau asynchrone. |
JP2825961B2 (ja) * | 1990-10-18 | 1998-11-18 | 富士通株式会社 | Hdlc系データのatmセル処理装置 |
GB2253118B (en) * | 1991-02-20 | 1995-04-12 | Roke Manor Research | Improvements in or relating to asynchronous transfer mode switching system |
US5379297A (en) * | 1992-04-09 | 1995-01-03 | Network Equipment Technologies, Inc. | Concurrent multi-channel segmentation and reassembly processors for asynchronous transfer mode |
US5422848A (en) * | 1992-07-06 | 1995-06-06 | Motorola Inc. | ECL-to-CMOS buffer having a single-sided delay |
-
1994
- 1994-04-19 ES ES09400814A patent/ES2101627B1/es not_active Expired - Fee Related
-
1995
- 1995-04-10 CA CA002146691A patent/CA2146691C/en not_active Expired - Fee Related
- 1995-04-10 EP EP95500049A patent/EP0678998A3/en not_active Withdrawn
- 1995-04-12 PE PE1995266359A patent/PE25896A1/es not_active Application Discontinuation
-
1997
- 1997-03-10 US US08/815,998 patent/US5777995A/en not_active Expired - Fee Related
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
ES2160049A1 (es) * | 1999-04-22 | 2001-10-16 | Telefonica Sa | Conmutador de paquetes para un red con modo de transferencias asincrono. |
ES2160061A1 (es) * | 1999-07-06 | 2001-10-16 | Telefonica Sa | Procesador en modo de transferencia asincrona de entrada y salida a un conmutador. |
Also Published As
Publication number | Publication date |
---|---|
EP0678998A2 (en) | 1995-10-25 |
CA2146691A1 (en) | 1995-10-20 |
EP0678998A3 (en) | 2000-07-12 |
CA2146691C (en) | 2000-02-15 |
PE25896A1 (es) | 1996-06-25 |
ES2101627A1 (es) | 1997-07-01 |
US5777995A (en) | 1998-07-07 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
ES2283095T3 (es) | Tarjeta de memoria de interfaz doble y modulo de adaptacion para la misma. | |
ATE491307T1 (de) | Einheit und verfahren zur speicheradressenübersetzung und bildverarbeitungsvorrichtung mit einer solchen einheit | |
EP1615227A3 (en) | Multilevel semiconductor memory device | |
EP1316964A3 (en) | Non-volatile semiconductor memory device and memory system using the same | |
EP0908892A3 (en) | Semiconductor integrated circuit device | |
WO2003003197A3 (en) | System-on-a-chip controller | |
SE8203621L (sv) | Kanal-grenssnittkrets | |
EP1146432A3 (de) | Umkonfigurierungs-Verfahren für programmierbare Bausteine während der Laufzeit | |
DE20211123U1 (de) | Media-Player mit Möglichkeit zur Unterstützung verschiedener Chipkarten | |
ES2101627B1 (es) | Circuito integrado traductor para red de banda ancha. | |
EP0180428A3 (en) | Portable computer | |
GB2317475A (en) | Adjustable fifo-based memory scheme | |
IT1303281B1 (it) | Cella di memoria di tipo eeprom con soglia regolata mediante impiantoe procedimento per la sua fabbricazione. | |
HK105993A (en) | Multi-stage integrated decoder device | |
IT1120522B (it) | Perfezionamento nelle memorie di controllo per sistemi di elaborazione di dati | |
JPS5591030A (en) | Address extending system of microprocessor | |
ITMI911485A1 (it) | Circuito di precarica di bit line per la lettura di una cella di memoria eprom. | |
ES2157666T3 (es) | Circuito para la activacion de una disposicion de memoria de semiconductores no volatil. | |
DK161292C (da) | Pcm omskifterenhed | |
JPS6321940B2 (es) | ||
ATE28010T1 (de) | Zeichengenerator. | |
IT8221574A0 (it) | Dispositivo elettronico a stadio di uscita in controfase particolarmente per l'associazione a memorie di sola lettura elettricamente programmabili. | |
JPS5523555A (en) | Micro cash system having resident bit | |
JPS5495128A (en) | Memory control system | |
In | zero suppression In programming, the |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
EC2A | Search report published |
Date of ref document: 19970701 Kind code of ref document: A1 Effective date: 19970701 |
|
PC2A | Transfer of patent | ||
FD1A | Patent lapsed |
Effective date: 20040503 |