ES2053187T3 - Sistema de calculo. - Google Patents

Sistema de calculo.

Info

Publication number
ES2053187T3
ES2053187T3 ES90907008T ES90907008T ES2053187T3 ES 2053187 T3 ES2053187 T3 ES 2053187T3 ES 90907008 T ES90907008 T ES 90907008T ES 90907008 T ES90907008 T ES 90907008T ES 2053187 T3 ES2053187 T3 ES 2053187T3
Authority
ES
Spain
Prior art keywords
processor systems
coupling component
decision logic
processor
interlaced
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
ES90907008T
Other languages
English (en)
Inventor
Michael Feigenbutz
Michael Faulhaber
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Rockwell Collins Deutschland GmbH
Original Assignee
Teldix GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Teldix GmbH filed Critical Teldix GmbH
Application granted granted Critical
Publication of ES2053187T3 publication Critical patent/ES2053187T3/es
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/17—Interprocessor communication using an input/output type connection, e.g. channel, I/O port

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
  • Hardware Redundancy (AREA)
  • Advance Control (AREA)

Abstract

EL TEMA DE ESTA INVENCION ES UN SISTEMA INFORMATICO CON VARIOS SISTEMAS DE PROCESADOR QUE OPERAN INDEPENDIENTEMENTE, UNA LOGICA DE DECISION Y UN CANAL DE SISTEMA QUE ENTRELAZA LOS SISTEMAS DE PROCESADOR Y LA LOGICA DE DECISION. EN ESTE SISTEMA INFORMATICO HAY AL MENOS DOS SUBSISTEMAS DE PROCESADOR ENTRELAZADOS POR EL CANAL DE SISTEMA QUE CONSTAN AL MENOS DE DOS SISTEMAS DE PROCESADOR LOCAL QUE OPERAN INDEPENDIENTEMENTE. LOS SISTEMAS DE PROCESADOR LOCAL DE UN SUBSISTEMA DE PROCESADOR PUEDEN ENTRELAZARSE O ENLAZARSE CON EL CANAL DE SISTEMA MEDIANTE UN COMPONENTE DE ACOPLAMIENTO. UNA LOGICA DE DECISION DEL COMPONENTE DE ACOPLAMIENTO DECIDE SOBRE EL SIGUIENTE ENLACE QUE SE HA DE EFECTUAR MEDIANTE EL COMPONENTE DE ACOPLAMIENTO DEPENDIENDO DE UNA SECUENCIA PROGRAMABLE DE FORMA SELECTIVA DEL PROCESO DE PETICIONES DE COMUNICACION.
ES90907008T 1989-05-31 1990-05-11 Sistema de calculo. Expired - Lifetime ES2053187T3 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE3917715A DE3917715A1 (de) 1989-05-31 1989-05-31 Rechnersystem

Publications (1)

Publication Number Publication Date
ES2053187T3 true ES2053187T3 (es) 1994-07-16

Family

ID=6381767

Family Applications (1)

Application Number Title Priority Date Filing Date
ES90907008T Expired - Lifetime ES2053187T3 (es) 1989-05-31 1990-05-11 Sistema de calculo.

Country Status (6)

Country Link
US (1) US5423007A (es)
EP (1) EP0474656B1 (es)
JP (1) JPH04506123A (es)
DE (2) DE3917715A1 (es)
ES (1) ES2053187T3 (es)
WO (1) WO1990015387A1 (es)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3917715A1 (de) * 1989-05-31 1990-12-06 Teldix Gmbh Rechnersystem
ES2139583T3 (es) * 1992-08-19 2000-02-16 Siemens Nixdorf Inf Syst Sistema multiprocesador con memorias cache.
DE9312739U1 (de) * 1993-08-25 1993-10-07 Siemens Ag Redundantes Automatisierungssystem
US5845107A (en) * 1996-07-03 1998-12-01 Intel Corporation Signaling protocol conversion between a processor and a high-performance system bus
US6295571B1 (en) * 1999-03-19 2001-09-25 Times N Systems, Inc. Shared memory apparatus and method for multiprocessor systems

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JPS60258671A (ja) * 1984-06-05 1985-12-20 Nec Corp プロセツサ
US4750111A (en) * 1984-08-22 1988-06-07 Crosby Jr Edward D Computer system for processing analog and digital data
CA1239227A (en) * 1984-10-17 1988-07-12 Randy D. Pfeifer Method of and arrangement for ordering of multiprocessor operations in a multiprocessor system
US5067071A (en) * 1985-02-27 1991-11-19 Encore Computer Corporation Multiprocessor computer system employing a plurality of tightly coupled processors with interrupt vector bus
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JPH07104837B2 (ja) * 1987-11-25 1995-11-13 富士通株式会社 プロセッサの制御方法
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DE3786583T2 (de) * 1986-03-12 1993-12-02 Hitachi Ltd Prozessor.
US5274797A (en) * 1986-05-30 1993-12-28 Bull Hn Information Systems Inc. Multiprocessor system with centralized initialization, testing and monitoring of the system and providing centralized timing
JP2585535B2 (ja) * 1986-06-02 1997-02-26 株式会社日立製作所 複合計算機システムにおけるプロセス結合方法
US4945475A (en) * 1986-10-30 1990-07-31 Apple Computer, Inc. Hierarchical file system to provide cataloging and retrieval of data
US4831523A (en) * 1986-10-31 1989-05-16 Bull Hn Information Systems Inc. Multiple DMA controller chip sequencer
US4941089A (en) * 1986-12-12 1990-07-10 Datapoint Corporation Input/output network for computer system
US4910666A (en) * 1986-12-18 1990-03-20 Bull Hn Information Systems Inc. Apparatus for loading and verifying a control store memory of a central subsystem
US5142683A (en) * 1987-03-09 1992-08-25 Unisys Corporation Intercomputer communication control apparatus and method
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US5029074A (en) * 1987-06-29 1991-07-02 Digital Equipment Corporation Bus adapter unit for digital processing system
US5113496A (en) * 1987-08-04 1992-05-12 Mccalley Karl W Bus interconnection structure with redundancy linking plurality of groups of processors, with servers for each group mounted on chassis
EP0311705B1 (en) * 1987-10-14 1993-03-31 Bull HN Information Systems Inc. Data processing system with a fast interrupt
US5191651A (en) * 1987-11-03 1993-03-02 International Business Machines Corporation Apparatus and method for making of interconnected processors act like a single node in a multinode communication system
US5113498A (en) * 1987-11-10 1992-05-12 Echelon Corporation Input/output section for an intelligent cell which provides sensing, bidirectional communications and control
US5027271A (en) * 1987-12-21 1991-06-25 Bull Hn Information Systems Inc. Apparatus and method for alterable resource partitioning enforcement in a data processing system having central processing units using different operating systems
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US5185864A (en) * 1989-06-16 1993-02-09 International Business Machines Corporation Interrupt handling for a computing system with logical devices and interrupt reset
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US5201053A (en) * 1990-08-31 1993-04-06 International Business Machines Corporation Dynamic polling of devices for nonsynchronous channel connection

Also Published As

Publication number Publication date
EP0474656A1 (de) 1992-03-18
JPH04506123A (ja) 1992-10-22
US5423007A (en) 1995-06-06
EP0474656B1 (de) 1994-04-13
WO1990015387A1 (de) 1990-12-13
DE59005377D1 (de) 1994-05-19
DE3917715A1 (de) 1990-12-06

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