Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W20/00—Interconnections in chips, wafers or substrates
  • H10W20/01—Manufacture or treatment
  • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
  • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D1/00—Resistors, capacitors or inductors
  • H10D1/01—Manufacture or treatment
  • H10D1/041—Manufacture or treatment of capacitors having no potential barriers
  • H10D1/042—Manufacture or treatment of capacitors having no potential barriers using deposition processes to form electrode extensions
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D1/00—Resistors, capacitors or inductors
  • H10D1/60—Capacitors
  • H10D1/68—Capacitors having no potential barriers
  • H10D1/692—Electrodes
  • H10D1/711—Electrodes having non-planar surfaces, e.g. formed by texturisation
  • H10D1/716—Electrodes having non-planar surfaces, e.g. formed by texturisation having vertical extensions
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W20/00—Interconnections in chips, wafers or substrates
  • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
  • H10W20/211—Through-semiconductor vias, e.g. TSVs
  • H10W20/212—Top-view shapes or dispositions, e.g. top-view layouts of the vias

Definitions

• the present invention relates to the field of integration of microelectronic components, more particularly, for electronic products, related semiconductor products, and their manufacturing processes.
• the invention will find its application more particularly in the field of capacitive storage components, in particular integrated solid supercapacitors.
• Capacitors are important elements of integrated circuits (IC) and semiconductor devices, for example for use as information storage cells in memory devices, or energy. They are present in many electronic functions, such as analog signal processing and energy converters. Whether they are integrated on the silicon chip or externally by discrete components, they contribute significantly to the size of the system. As the capacitance density available on silicon technologies is limited to a few nF/mm2, electronic circuits often use components external to the chip to implement capacitance requirements in the chip.
• Silicon chip capacitors can have different architectures.
• MIM Metal/Insulator/Metal
• MIM capacitors widely used in integrated circuits, include two metal plates with an insulator between the plates.
• BEOL back-end-of-line
• the space for the integration of capacitors in particular is often limited and superimposed on the surface of the circuit to limit the additional footprint of these capacitors. Since the capacitance of a capacitor is linearly proportional to the surface area of the capacitor, the lack of layout space at the BEOL limits the number of conventional MIM capacitors placed there, resulting in lower power density insufficient when capacitors are used as energy storage devices.
• 3D capacitors In the search for high-performance on-chip integrated energy storage solutions, increasing the specific surface area of the capacitive structure using a three-dimensional (3D) architecture has proven to be an excellent approach that significantly increases the density of capacity while allowing reduction of chip surface area.
• the technological interest of 3D capacitors lies in the fact that the capacitors are stackable and have a surface developed in the plane (x;y) of the substrate, but also on the height/thickness z, allowing a significant saving of space and a surface developed capacity greater than a planar capacity.
• a semiconductor device comprising a substrate comprising at least one cavity, and a three-dimensional structure formed in the substrate comprising:
• a three-dimensional capacitor comprising a capacitive stack, the capacitive stack being at least partially housed in the at least one cavity of the substrate,
• the at least one cavity extends along the thickness of the substrate from the upper face of said substrate, and the three-dimensional capacitor is configured to delimit, on the upper face of the substrate, a contour of an inscribed portion , the pillar being arranged in the inscribed portion of the substrate.
• the capacitive stack comprises a first electrode layer, an intermediate layer and a second electrode layer
• the three-dimensional structure comprises a first conformal layer comprising a first part forming the first electrode layer of the capacitive stack and a second conforming part arranged in the pillar, the first part and the second part being electrically disconnected from each other.
• the intermediate layer is an ionic conductive dielectric material.
• This device makes it possible to obtain a capacitor which has a much greater power density and charge density than with an ionic non-conductive dielectric known in the state of the art.
• the advantage of the device according to the invention is to densify the capacitance value per surface unit of the useful silicon (in the horizontal plane) while benefiting from the cost reduction, because certain stages of manufacturing the three-dimensional capacitor can be shared with the fabrication of the pillar while retaining the independent functionality of the capacitor and the pillar.
• the invention makes it possible to benefit from the surfaces around the pillars which can play various roles such as electrical, thermal or mechanical and at the same time overcome the limitations of the solutions proposed in the prior art.
• the capacitor is said to be three-dimensional in that it has a three-dimensional structure making it possible to increase the developed surface area without increasing the horizontal surface area of silicon and consequently increasing the associated storage capacity.
• the invention relates to a method of manufacturing a device as described above comprising a step a) comprising the production of a three-dimensional structure comprising at least one cavity of a three-dimensional capacitor and at least one pillar in a substrate, the capacitor is configured to delimit on the upper face of the substrate a contour of an inscribed portion, the pillar (400) being arranged in the inscribed portion of the substrate, a step b) comprising the conformal deposition of a first layer on the three-dimensional structure, that is to say in the cavity and in the pillar as well as on the upper face of the substrate, so that a first part of the first layer forms a first layer of a capacitive stack of the capacitor and a second part of the first layer is formed in the pillar, a step c) of filling the pillar, a step d) of partial removal of the first layer so as to electrically disconnect the first part of the first layer and the second part of the first layer, step d) being able to be carried out before or
• Figure 1 represents a top view of a semiconductor device according to a first embodiment of the invention.
• Figure 2 represents a view along section AA of Figure 1.
• Figure 3 represents a view along section BB of Figure 2.
• Figure 4 represents a top view of a semiconductor device according to a second embodiment of the invention.
• Figure 5 represents a view according to section CC of Figure 4
• Figure 6 represents a view along section DD of Figure 4.
• Figure 7 represents a view along section EE of Figure 5.
• Figure 8 shows a sectional view of the semiconductor device in a complete stack.
• Figures 9 to 15 represent the steps of a process for manufacturing a semiconductor device according to the invention.
• the ionic conductive dielectric material has an ionic conductivity at room temperature at least equal to 1 pS.cm-1;
• the ionic conductive dielectric material has an associated activation energy less than or equal to 0.6eV;
• the pillar 400 is arranged in the center of the inscribed portion 202;
• the transverse distance 104 at the thickness 103 of the substrate 100 between the center of a cavity and the center of the pillar 400 is less than or equal to 100 pm;
• the transverse distance 104 at the thickness 103 of the substrate 100 between the center of a cavity and the center of the pillar 400 is less than or equal to 5pm;
• At least one cavity of the capacitor 300 is a trench 301;
• trench 301 is circular and arranged in the form of a circle around pillar 400;
• the capacitor 300 comprises at least two circular and concentric trenches 301;
• At least one cavity of the capacitor is a column 302;
• the capacitor 300 comprises a plurality of columns 302,
• the plurality of columns 302 is arranged in a circular manner around the pillar 400;
• the width 401 of a pillar is 20 times greater than the width 303 of a cavity of the three-dimensional capacitor 300, the widths 401,303 being taken transversely to the thickness 103 of the substrate 100;
• the three-dimensional capacitor 300 includes 2 to 20 cavities.
• the pillar 400 comprises a metallic material so as to fill the pillar 400 at the level of the upper face 101 of the substrate 100;
• the metallic material is different from the intermediate layer 502 so that the pillar 400 does not include a capacitive stack 500;
• the cavity only opens onto the upper face 101 of the substrate 100;
• the semiconductor device comprises an underlying layer and a superadjacent layer to the substrate;
• the three-dimensional structure is intended to be arranged at the end of the interconnection line (BEOL);
• the three-dimensional structure is located at the level of interconnections coupled to a processor, or at the rear of a processor,
• the invention relates to a processor comprising a semiconductor device as described above in which the three-dimensional structure is located at interconnections coupled to the processor, or at the rear of the processor.
• the removal of the first layer is carried out at the upper face 101 of the substrate 100 between the cavity and the pillar 400;
• the method comprises the conformal deposition of an intermediate layer then the conformal deposition of the second electrode layer;
• the conformal deposition of the intermediate layer is carried out only in the three-dimensional capacitor or the conformal deposition of the intermediate layer is carried out over the entire three-dimensional structure 200 then a step of removing the intermediate layer in outside the capacitor is carried out;
• the method comprises the conformal deposition of the second electrode layer 503 is carried out only in the three-dimensional capacitor 30 or else the conformal deposition of the second electrode layer 503 is carried out over the entire three-dimensional structure 200 and a step of removing the second electrode layer 503 outside the capacitor 300 is carried out forming a first part of the second layer 503 participating in the capacitive stack;
• the removal of the second electrode layer 503 is carried out by retaining it at the level of the pillar 400 forming a second part of second layer 503 on the pillar 400, the first part and the second part being electrically disconnected one from the other.
• transverse is meant a direction perpendicular to a longitudinal direction.
• the longitudinal direction is understood as the thickness of the stack or substrate.
• a cross section is a section perpendicular to the longitudinal axis.
• a cross section is a section perpendicular to the thickness of the substrate stack.
• the width of a cavity or pillar is defined as the dimension of the cavity or pillar transverse to the thickness.
• upper used in particular to qualify a face of the substrate only serves here to designate a first of the two faces of the substrate (the other being the lower face), without making any hypothesis on the relative position of the faces, in a vertical direction.
• the upper face could thus also have been called the front face, as opposed to a rear face.
• a parameter “substantially equal/greater/less than” or “of the order of” a given value we mean that this parameter is equal/greater/less than the given value, to within plus or minus 10%, or even to plus or minus 5% of this value.
• the term “over”, “overcomes”, “covers”, “above” or “underlying” or “underneath” or their equivalents do not necessarily mean “ in touch with ".
• the deposition of a first layer on a second layer does not necessarily mean that the two layers are directly in contact with each other, but it means that the first layer at least partially covers the second layer either in being directly in contact with it, or being separated from it by at least one other layer or at least one other element.
• a substrate By a substrate, a film, a layer, a chip or a protuberance “based” on a material A, we mean a substrate, a film, a layer, a chip or a protuberance comprising this material A and possibly others materials, for example doping elements.
• coating corresponds to a layer which is formed, in particular by modification of the underlying layer or by a deposit on this underlying layer.
• dielectric corresponds to a material whose electrical conductivity is low enough in the given application to serve as an insulator.
• Coupled we mean that two or more elements are in direct physical or electrical contact.
• the invention relates to a semiconductor device comprising a three-dimensional structure 200 formed in a substrate 100.
• the basic capacitance structures are essentially stacks of layers in one direction, the thickness 103 of the substrate. In this sense, their form is monotonous in this direction.
• the 3D shape here means a geometry more complex than a stack of layers in a single direction; these may be shapes defined by one or more cavities or trenches in which layers are present with a stack that extends in several directions, depending on the surface of the cavity or trench that is covered.
• the 3D structures also cover structures with several functionally connected cavities or trenches, typically to form parts of the same capacitor 300.
• the semiconductor device comprises a substrate 100.
• the three-dimensional structure 200 can be implemented or produced in a substrate 100, such as a semiconductor substrate.
• the semiconductor substrate 100 may be a crystalline substrate formed using bulk silicon or a silicon-on-insulator substructure.
• the semiconductor substrate 100 may be formed using alternative materials, which may or may not be combined with silicon, which include, but are not limited to, germanium, antimonide d indium, lead telluride, indium arsenide, indium phosphide, gallium arsenide, indium gallium arsenide, gallium antimonide, or other combinations of materials group III-V or group IV.
• any material that may serve as a foundation upon which a semiconductor device may be constructed falls within the spirit and scope of the present disclosure.
• the three-dimensional structure 200 is formed in the substrate 100 more particularly in a part of the substrate. It is defined for the remainder of the description that the substrate comprises an upper face 101 opposite a lower face 102.
• the three-dimensional structure 200 comprises at least one pillar 400.
• the three-dimensional structure comprises a pillar 400, but may comprise several pillars 400.
• the pillar 400 extends along the thickness 103 of the substrate 100.
• the pillar 400 opens out at the level of the upper face 101 of the substrate 100.
• the pillar 400 may or may not open out at the level of the lower face 102 of the substrate 100.
• the pillar 400 is a vertical structure which can have different functions, whether electrical, thermal or packaging.
• the pillar 400 may be an interconnection, a via or through via (TSV for "Through Silicon Via", that is to say via through silicon; we can also encounter vias through glass called “TGV”), a vertical heat dissipation structure, a vertical encapsulation structure.
• TSV via or through via
• FIG. 8 An example of implementation is illustrated in Figure 8 where we find a three-dimensional assembly 600 comprising two electronic chips, for example two processors 610, and a passive interposer 620 which allows their interconnection, and their connection to another level at through 630 copper pillars, thus achieving a level of signal redistribution.
• the three-dimensional structure 200 according to the invention is arranged at the level of the passive interposer 620.
• the pillar 400 having a depth 402 extending along the thickness 103 of the substrate 100 and a width 401 extending transversely to the thickness 103 of the substrate 100.
• the width 401 of the pillar 400 is greater than or equal to 2pm.
• the pillar 400 has side walls 403 having a vertical main component.
• the side walls 403 of the pillar 400 are vertical, that is to say extending along the thickness 103 of the substrate 100.
• the pillar 400 has a cross section at the thickness of the substrate of circular shape.
• Other shapes of pillar 400 can be considered such as for example polygonal, parallelepiped, oval.
• the pillar 400 opens onto the upper face 101 of the substrate 100 and may or may not open onto the lower face 102 of the substrate 100. According to the embodiments illustrated in the figures, the pillars 400 do not open onto the lower face 102 of the substrate 100. Subsequent stages of manufacturing the semiconductor device may however include the addition of an underlying layer on the lower face 102 of the substrate 100 implying that the pillar 400 opens onto the lower face 102 of the substrate 100.
• the semiconductor device according to the invention comprises a three-dimensional structure 200.
• the three-dimensional structure 200 is formed in a part of the substrate 100 and comprises a three-dimensional capacitor 300.
• the three-dimensional capacitor 300 comprises a capacitive stack 500 at least partially housed in a cavity formed in the substrate 100.
• the three-dimensional capacitor 300 thus has a three-dimensional structuring making it possible to increase the developed surface area and the associated storage capacity.
• the substrate 100 comprises at least one cavity.
• the substrate 100 more specifically the three-dimensional structure 200, can comprise up to 20 cavities, more specifically 2 to 10 cavities.
• the cavities comprise the same capacitive stack 500 so as to optimize the capacity of the condenser 300.
• the following description is made with reference to a cavity, but applies to all cavities when the three-dimensional structure 200 includes more than one cavity.
• the cavity extends along the thickness 103 of the substrate 100 from the upper face 101 of said substrate 100. The cavity thus penetrates into the substrate 100.
• the cavity and the pillar 400 extend in the same parallel main direction at the thickness 103 of the substrate 100.
• the cavity opens into the upper face 101 of the substrate 100 and advantageously does not open into the lower face 102 of the substrate 100 so as to allow the arrangement of the capacitive stack 500 on the largest possible substrate surface.
• the three-dimensional capacitor 300 can simply be called capacitor 300.
• the capacitor 300 is configured to delimit on the upper face 101 of the substrate 100, a contour 201 of an inscribed portion 202.
• the contour 201 may have various shapes such as, for example, circular, ovoid, parallelepiped, polygonal.
• the inscribed portion 202 comprises at least one pillar 400.
• the pillar 400 is arranged in the inscribed portion 202 defined by the capacitor 300.
• the pillar 400 is arranged in the center of the inscribed portion 202. More specifically, the center of the pillar 400 corresponds to the center of the inscribed portion 202.
• the three-dimensional structure 200 comprises a first conformal layer comprising a first part forming the first electrode layer 501 of the capacitive stack 500 and a second part 404 arranged in the pillar 400 more specifically covering the side walls 403 of the pillar 400.
• the first electrode layer 501 and the second part 404 are advantageously identical, in particular since they are preferably formed at the same time by a single deposition of a first layer.
• the first part forming the first electrode layer 501 and the second part 404 arranged in the pillar 400 are electrically disconnected from each other.
• the electrical disconnection of the first part forming the first electrode layer 501 and the second part 404 arranged in the pillar 400 is advantageously done by partial removal 504 of the first layer, in particular on the upper face 101 of the substrate 100.
• the arrangement of the three-dimensional capacitor 300 in a three-dimensional structure 200 comprising a pillar 400 saves space by using a part of substrate 100 conventionally used while allowing a pooling of the steps in particular the deposition of the first layer without implying a functional link between the capacitor 300 and the pillar 400.
• the width 401 of the pillar 400 is at least 20 times greater than the width 303 of a cavity, preferably 50 times greater than the width 303 of a cavity.
• the cavity of the capacitor 300 is a trench 301.
• trench 301 is meant a cavity in the substrate 100 having a length of dimension greater than its width 303.
• the length being understood as the direction transverse to the thickness and width.
• the ratio between the length and the width is greater than or equal to 2, preferably greater than or equal to 20.
• the trench 301 has a depth, that is to say a dimension extending along a direction parallel to the thickness 103 of the order of 20 pm.
• the trench 301 is straight or curved.
• the rectilinear trench 301 can be a straight line extending in a single direction or extending in several directions and thus forming a broken line.
• the trench 301 curves perhaps a continuous curve in a single direction or extending in several directions and thus forming a curved line.
• the 300 may include a trench 301 defining by itself the contour 201 of the inscribed portion 202.
• the trench 301 is thus closed on itself, the ends of the trench 302 meet.
• the inscribed portion 202 may be of variable and arbitrary shape.
• the trench 301 is for example circular or even polygonal or parallelepiped.
• the pillar 400 is at the center of the inscribed portion 202 and the trench 301 forms the contour 200 of the inscribed portion 202.
• the capacitor 300 may comprise several cavities and in particular several trenches 301. According to the preferred possibility, the capacitor 300 comprises several trenches 301 closed on itself and concentric. Preferably, the trenches
• the trenches 301 are circular as illustrated in Figures 1 and 3.
• the trenches 301 advantageously comprise the same capacitive stack 500 so as to increase the surface area of the capacitor 300.
• the cavity of the capacitor 300 is a column 302.
• column is meant a cavity in the substrate 100 having a length of dimension substantially equivalent to its width.
• the ratio between length and width is of the order of 1.
• the length and width are 10pm and the depth is of the order of 20pm.
• Each column 302 has a cross section with circular, ovoid, parallelepiped, polygonal thickness. All columns 302 may or may not have the same cross-section shape.
• the capacitor 300 comprises at least three columns 302.
• the columns 302 are thus advantageously arranged so as to define a contour 201 of an inscribed portion 202.
• the contour 201 of the inscribed portion 202 is formalized by all of the lines 203 connecting successive columns 302 to each other.
• the contour 201 is formed by all the lines 203 connecting the columns 302 closest to the pillar 400.
• the columns 302 are advantageously arranged around the pillar 400 so as to form an advantageously circular contour 201 as illustrated in Figure 4.
• the transverse distance 104 at the thickness 103 separating the center of the pillar 400 from the center of a cavity is less than or equal to 100 pm.
• the transverse distance 104 at the thickness 103 separating the center of the pillar 400 from the center of a cavity is greater than or equal to 5 pm.
• the condenser 300 comprises at least one trench 301 and at least one column 302.
• the capacitor 300 comprises a capacitive stack 500 comprising a first electrode layer 501 advantageously formed at least by the first part of a first layer 501, an intermediate layer 502 and a second electrode layer 503.
• the first electrode layer 501 covers the side walls of at least one cavity, preferably of all the cavities of the three-dimensional structure 200 and of the upper face 101 of the substrate 100 exposed between the cavities.
• the first electrode layer 501 is chosen from materials TiN, TaN, W, Ni, Pt, Ru.
• the intermediate layer 502 is a dielectric ionic material and covers the first electrode layer 501.
• the intermediate layer 502 may be an electrolyte in the solid state.
• the dielectric is an ionic conductor.
• the ionic conductor has high ionic conductivity at room temperature (preferably between 20°C and 25°C, preferably at 25°C), at least 1 pS.cm-1, and advantageously which also has a low associated activation energy, generally less than 0.6eV.
• the intermediate layer 502 may include AI2O3, HfO2, ZrO2, TiO2, Nb2O5, Ta2O5, SrTiOx, BaTiOx, Ga2O3, Y2O3, rare earth oxide, solid state electrolyte, glass electrolyte, ceramic electrolyte, LiPON , an ionic antiperovskite, LiSCIO, a doped Li(3-2x)DxCIO where D is a divalent cationic dopant, hafnium silicate, zirconium silicate, hafnium dioxide, hafnium zirconate, zirconium, aluminum oxide, titanium oxide, silicon nitride, carbon-doped silicon nitride, silicon carbide and hafnium silicate nitride, a high k dielectric material, or an alloy thereof.
• the intermediate layer 502 of ionic dielectric material makes it possible to obtain a capacitor which has a much greater power density and a charge density than with an ionic non-conductive dielectric known in the state of the art.
• the second electrode layer 503 covers the intermediate layer 502.
• the second electrode layer 503 is TiN, TaN, W, Ni, Pt, Ru.
• the first electrode layer 501, the second electrode layer 503, and the second part 404 may comprise W, Mo, Ti, Ta, Al, TaN, TiN, TiC, WN, MoN, MoC, Co, Ni, Cu , Ru, Pd, Pt, Ir, IrOx, graphene, MnO2, Li, RuOx, ITO, SrRuOx, a metal oxide, graphitic carbon, an alkali metal, a low work function metal, a transition metal oxide , a Co oxide, LiCoO2, NaCoO2, a transition metal dichalcogenide, a spinel oxide, LiMn2O4, LiNiMnO4, a conductive polymer or a conductive metal.
• the first electrode layer 501 projects at its ends onto the upper face 101 relative to the intermediate layer 502 and the second electrode layer 503 so as to allow the connection of the first electrode layer 501 and the second electrode layer 503 separately.
• one or the other or both of the first electrode layer 501 and the second electrode layer 503 is an ion intercalation electrode.
• the semiconductor device comprises a micro-battery.
• the pillar 400 comprises the second part 404 of the first conformal layer covering the side walls 403.
• the pillar 400 comprises a metallic material 405 filling the entire remaining volume and ensuring leveling with the upper face 101 of the substrate 100.
• the presence of the second part 404 of the first conformal layer in the pillar 400 may be of interest as interdiffusion barrier between the substrate 100 and the metallic material 405, or also a diffusion barrier of ions from the metallic material 405 towards the substrate 100.
• the second part 404 of the first conformal layer acts as a barrier to diffusion between substrate 100 and the metallic material 405, or also to an additional chemical barrier to improve the encapsulation of the components.
• the metallic material 405 is different from the intermediate layer 502 of the capacitive stack.
• the metallic material 405 is different from the first electrode layer 501 and preferably from the second electrode layer 503.
• the metallic material 405 is chosen depending on the objective of the pillar 400 being preferentially different from electronic conduction and being for example heat dissipation, encapsulation, packaging etc...
• the pillar 400 does not include a capacitive stack 500.
• the pillar 400 comprises a part of the second electrode layer 503.
• a part of the second electrode layer 503 is arranged on the metallic material 405 so as to at least partially cover the metallic material 405.
• This part of the second electrode layer 503 makes it possible to facilitate/optimize the electrical, thermal or mechanical contact between the metallic material 405 and the following levels.
• this part of the second electrode layer 503 is identical to the second electrode layer 503 described above with reference to the capacitive stack.
• the capacitor 300 has a three-dimensional shape which extends to the upper face 101 of the substrate by delimiting for this upper face 101 two surface parts: a part interior to the capacitor 300 which is the one inscribed, and a exterior part.
• the shape of the capacitor 300 provides it with an interior edge (this is the case for a circular trench 301), or a border of placement of the cavities (this is the case if the capacitor 300 is formed with several cavities, for example of column type 302 which surrounds an interior part according to a profile, regular or not, delimiting this surface). By joining the edges of these cavities spaced around the inscribed surface, we reveal the shape of this border.
• the cavities are then like posts delimiting a surface of the ground, barriers joining the posts revealing the shape of this surface which is the inscribed surface.
• the contour of this surface, formed by the capacitor can therefore be continuous (as in the case of a trench with a closed contour, for example circular) or discrete as in the case of via-shaped cavities.
• the semiconductor device according to the invention is produced on the rear face of CMOS technology.
• the semiconductor device comprises an underlying layer such as for example a substrate comprising a transistor and/or an underlying layer.
• the semiconductor device is produced at the end of the interconnection line also called Back End of Line (BEOL).
• BEOL Back End of Line
• the invention relates to a method of manufacturing a semiconductor device as described above.
• the different stages of the process are illustrated in Figures 9 to 15.
• the method of manufacturing a semiconductor device comprising the following steps of:
• the process comprises the following steps of:
• the manufacturing process begins as illustrated in Figure 9 with the presence of substrate 100.
• the manufacturing process advantageously comprises a step a) comprising the production of at least one cavity and at least one pillar 400 in a substrate 100.
• This first production step is carried out by a plasma type etching step, more commonly called deep ion reactive etching or DRIE and known by professional.
• a plasma type etching step more commonly called deep ion reactive etching or DRIE and known by professional.
• the arrangement of the at least one cavity and of the pillar 400 is defined so that the cavity defines a contour of an inscribed portion with the pillar arranged in the inscribed portion.
• the semiconductor device obtained at the end of step a) is illustrated in Figure 10.
• the method comprises a step b) comprising the conformal deposition of a first layer on the three-dimensional structure 200, that is to say in the cavity and in the pillar as well as on the upper face 101 of the substrate 100.
• the conformal deposition is carried out by conventional methods known to those skilled in the art such as: chemical vapor deposition (CVD), or atomic deposition (ALD).
• CVD chemical vapor deposition
• ALD atomic deposition
• the process then comprises a step c) of filling the pillar 400.
• the filling is carried out by conventional methods known to those skilled in the art such as: electrochemical deposition or electroless deposition.
• the semiconductor device obtained at the end of step c) is illustrated in Figure 12.
• the method comprises a step d) of advantageously partial removal 504 of the first layer so as to electrically disconnect a first part of the first layer 501 and a second part 404 of the first layer.
• the removal of the first layer is carried out at the upper face 101 of the substrate 100, preferably between the cavity and the pillar 400.
• the removal is carried out by conventional methods known to those skilled in the art such as: chemical etching or plasma engraving, both coupled with photolithography for the definition of patterns.
• the semiconductor device obtained at the end of step d) is illustrated in Figure 13.
• This step d) can be carried out before or after step c).
• the method then comprises the successive steps to carry out the rest of the capacitive stack 500.
• the method comprises the conformal deposition of the intermediate layer 502 then the conformal deposition of the second electrode layer 503.
• the production of the stack capacitive 500 is produced by conventional methods known to those skilled in the art such as: atomic deposition or ALD.
• the conformal deposition of the intermediate layer 502 is carried out only as illustrated in Figure 14 or the conformal deposition of the intermediate layer 502 is carried out on the entire three-dimensional structure 200 and the method comprises a step of removing the intermediate layer 502 outside the capacitor 300.
• the conformal deposition of the second electrode layer 503 is carried out only as illustrated in Figure 15 or else the conformal deposition of the second electrode layer 503 is carried out on the entire three-dimensional structure 200 and the method comprises a step of removing the second electrode layer 503 outside the capacitor 300 and advantageously from the pillar 400 forming a first part of second layer 503 participating in the capacitive stack and a second part of second layer 503 on the pillar 400.
• the first part and the second part are electrically disconnected from each other.
• the invention is not limited to the embodiments previously described and extends to all the embodiments covered by the invention.

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• 2022
  • 2022-12-12 FR FR2213149A patent/FR3143198A1/fr active Pending
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