Classifications

• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
  • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
  • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
  • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
  • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
  • H05B45/00—Circuit arrangements for operating light-emitting diodes [LED]
  • H05B45/30—Driver circuits
  • H05B45/32—Pulse-control circuits
  • H05B45/325—Pulse-width modulation [PWM]
• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G2230/00—Details of flat display driving waveforms
• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G2310/00—Command of the display device
  • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
  • G09G2310/0264—Details of driving circuits
  • G09G2310/027—Details of drivers for data electrodes, the drivers handling digital grey scale data, e.g. use of D/A converters
• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G2310/00—Command of the display device
  • G09G2310/06—Details of flat display driving waveforms
  • G09G2310/065—Waveforms comprising zero voltage phase or pause
• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G2310/00—Command of the display device
  • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
  • G09G2330/02—Details of power systems and of start or stop of display operation
  • G09G2330/021—Power management, e.g. power saving
• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
  • G09G2330/02—Details of power systems and of start or stop of display operation
  • G09G2330/028—Generation of voltages supplied to electrode drivers in a matrix display other than LCD

Definitions

• This application relates to a display screen whose display pixels include light-emitting diodes.
• a pixel of an image corresponds to the unitary element of the image displayed by a display screen.
• the display screen generally comprises for the display of each pixel of the image at least three components, also called display sub-pixels, which each emit light radiation substantially in a single color (for example, red, green and blue).
• the superposition of the radiation emitted by these three display sub-pixels provides the observer with the colored sensation corresponding to the pixel of the displayed image.
• the display pixel of the display screen is the set formed by the three display sub-pixels used for the display of a pixel of an image.
• Each display sub-pixel can comprise a light source, in particular a light-emitting diode.
• the display pixels can be distributed in a matrix fashion, each display pixel being located at the intersection of a row (or row) and a column of the matrix. In general, each row of display pixels is selected in succession, and the display pixels of the selected row are programmed to display the desired image pixels.
• the size of the light-emitting diode circuit is generally smaller than the size of the pixel of the image thanks to the high intrinsic luminosity of the diodes electroluminescent.
• One of the solutions used is therefore to deposit these unit light-emitting diodes on a support (also called a slab) containing the control electronics.
• Another solution consists in using display pixels comprising light-emitting diodes and a control circuit for the light-emitting diodes.
• Document WO 2018/185433 describes an example of a smart pixel.
• a smart pixel For a smart pixel, it is generally the number of conductive pads of the smart pixel, used for the electrical connection of the smart pixel to the support, which imposes the dimensions of the smart pixel, in particular because of the minimum size of these pads. and the minimum space to be provided between these pads. To limit the number of conductive pads, it is known to provide a single supply voltage to the display pixels, and each display pixel internally generates one or more reduced supply voltages, in particular for the biasing of components of the electronics of ordered.
• the static consumption of a display pixel corresponds to the electric power consumed by the display pixel when the latter does not emit light. It can be composed of component leakage currents or currents necessary for the internal operation of the display pixel control circuit. In the context of smart pixels, a significant part of the static consumption comes from the generation of internal supply voltages of the smart pixel.
• the trend is to increase the number of display pixels of the display screen.
• the static consumption of the display pixels can then become a critical factor. Indeed, for a so-called 4K display screen having a resolution of 2160 by 3840 display pixels, the static consumption of the display screen can be greater than 150 W.
• An object of an embodiment is to provide a light-emitting diode display screen that overcomes any or part of the disadvantages of existing light-emitting diode display screens.
• Another object of an embodiment is that the display pixels have dimensions of less than 200 mpi, which limits the number of interconnections between the display pixel and the display pixel support.
• One embodiment provides a display pixel for a display screen, comprising at least one light-emitting diode, a pilot circuit for the light-emitting diode and first, second, third and fourth electrically conductive pads, the circuit driver being at least partly powered by a first power supply voltage received between the first and second electrically conductive pads, the light-emitting diode being powered by a first binary signal received between the third and second electrically conductive pads, the first binary signal alternating between a second supply voltage, strictly higher than the first supply voltage, and a third voltage, strictly lower than the first supply voltage, the control circuit being configured to determine a digital signal from the values of a second binary signal on the fourth electrically conductive pad received during each of first pulses of the first binary signal at the third voltage and for driving the light emitting diode from the digital signal.
• the driver circuit is configured to control the light-emitting diode by pulse-width modulation from the digital signal
• the display pixel comprises only the first, second, third and fourth electrically conductive pads.
• the driver circuit is configured to turn on or off the light-emitting diode at the rate of second pulses of the first binary signal at the third voltage.
• the driver circuit is configured to determine a clock signal and a third binary signal from the second binary signal.
• control circuit comprises a circuit for storing binary data determined during each first pulse from the third binary signal.
• the second binary signal is intended to comprise a mixture of third pulses having the same duration and fourth pulses having the same duration greater than the duration of each third pulse, the driver circuit being configured to supplying the clock signal at the same rate as the third and fourth pulses and the third binary signal equal to a first state or to a second state according to the succession of the third and fourth pulses.
• One embodiment also provides a display screen comprising a matrix of display pixels as defined previously, the display screen further comprising supply circuits, for each display pixel, of the first supply voltage between the first and second electrically conductive pads, the first binary signal between the third and second electrically conductive pads, and the second binary signal on the fourth electrically conductive pad.
• the supply circuits are configured to maintain the first electrically conductive pad at a first potential substantially constant, the second electrically conductive pad at a second substantially constant potential, and the third electrically conductive pad at a third potential which alternates between first and second values, either the first value is strictly greater than the first potential and the second value is equal to the second potential, or the first value is equal to the first potential and the second value is strictly less than the second potential.
• the supply circuits are configured to supply the third voltage equal to the zero voltage.
• the supply circuits are configured to supply the second binary signal alternating between two potentials, the difference in absolute value between the two potentials being strictly lower than the second supply voltage.
• the supply circuits are configured to supply the first binary signal comprising, for the display of an image, the first pulse at the third voltage of a first duration and a succession of second pulses , each second pulse having a second duration less than the first duration.
• the durations between two pairs of successive second pulses increase or decrease.
• Figure 1 shows, partially and schematically, a known example of a display screen
• Figure 2 is a very schematic sectional view of a known example of a display pixel
• Figure 3 is a bottom view of the display pixel of Figure 2;
• FIG. 4 represents a known example of block diagram of the display pixel of FIG. 2;
• FIG. 5 represents known examples of timing diagrams of signals from the display pixel of FIG.
• Figure 6 shows, partially and schematically, an embodiment according to the invention of a display screen
• FIG. 7 represents a block diagram of an embodiment according to the invention of a display pixel of the display screen of FIG. 6;
• FIG. 8 represents timing diagrams of signals from the display pixel of FIG. 7;
• FIG. 9 represents a block diagram of another embodiment according to the invention of a display pixel of the display screen of FIG. 6;
• FIG. 10 represents timing diagrams of signals from the display pixel of FIG. 9.
• a “binary signal” is a signal which alternates between a first constant state, for example a low state, denoted “0”, and a second constant state, for example a high state, denoted “1”.
• the high and low states of different binary signals of the same electronic circuit can be different. In practice, binary signals may correspond to voltages or currents which may not be perfectly constant in the high or low state.
• the term “power terminals” of an insulated-gate field-effect transistor, or MOS transistor refers to the source and the drain of the MOS transistor.
• the expressions “about”, “approximately”, “substantially”, and “of the order of” mean to within 10%, preferably within 5%.
• the expression “substantially constant” means which varies by less than 10% over time with respect to a reference value.
• FIG. 1 shows, partially and schematically, a known example of a display screen 10.
• the display screen 10 comprises display pixels 12j_, j for example arranged in M rows and in N columns, M being an integer varying from 1 to 8000 and N being an integer varying from 1 to 16000, i being an integer varying from 1 to M and j being an integer varying from 1 to N. example, in FIG. 1, M and N are equal to 6.
• Each display pixel 12j_, j is connected to a source of a low reference potential Gnd, for example ground, via an electrode 14i and to a source of a high reference potential Vcc via an electrode 16 j .
• the electrodes 14i are shown aligned along the rows in FIG.
• the display screen supply voltage corresponds to the voltage between the high reference potential Vcc and the low reference potential Gnd.
• the supply voltage depends in particular on the arrangement of the light-emitting diodes and on the technology according to which the light-emitting diodes are manufactured. By way of example, the supply voltage may be of the order of 4 V to 5 V.
• the display screen 10 comprises a selection circuit 22 connected to the row electrodes 18i and adapted to supply a selection and timing signal Comi on each row electrode 18j_.
• the display screen 10 comprises a data supply circuit 24 connected to the column electrodes 20 j and adapted to supply a data signal Data j on each column electrode 20 j .
• the selection circuit 22 and the control circuit 24 are controlled by a circuit 26, comprising for example a microprocessor.
• FIG. 2 is a very schematic sectional view of a known example of the display pixel 12j_, j and Figure 3 is a bottom view of the display pixel 12j_, j .
• Each display pixel 12j_, j comprises a control circuit 30 covered with a display circuit 32.
• the display circuit 32 comprises at least one light-emitting diode LED, preferably at least three light-emitting diodes LED.
• the display pixel comprises a lower face 34 and an upper face 35 opposite the lower face 34, the faces 34 and 35 being preferably planar and parallel.
• the control circuit 30 further comprises conductive pads 36, not shown in FIG. 2, on the lower face 34.
• the control circuit 30 may correspond to an integrated circuit comprising electronic components, in particular field-effect transistors with insulated gate, also called MOS transistors, or thin film transistors, also called TFT transistors (English acronym for Thin-Film Transistor).
• the display circuit 32 comprises only the light-emitting diodes LEDs, and the conductive elements of these light-emitting diodes LEDs, and the control circuit 30 comprises all of the electronic components necessary for controlling the light-emitting diodes LEDs of the display circuit. 32.
• the display circuit 32 can also comprise other electronic components in addition to the light-emitting diodes LEDs.
• the light-emitting diodes LED can be 2D light-emitting diodes, also called planar light-emitting diodes, comprising a stack of plane layers, or 3D light-emitting diodes each comprising a three-dimensional semiconductor element covered with an active zone.
• the light-emitting diodes are shown connected to a common anode. It may however be desirable to arrange the light-emitting diodes LED according to another configuration.
• the light-emitting diodes can be connected in common cathode, or be connected independently of each other.
• the display pixel 12j_ ,j comprises three display sub-pixels emitting light at first, second and third wavelengths.
• the first wavelength corresponds to blue light and is in the range of 430 nm to 490 nm.
• the second wavelength corresponds to green light and is in the range of 510 nm to 570 nm.
• the third wavelength corresponds to red light and is in the range of 600 nm to 720 nm.
• Each conductive pad 36 is intended to be connected to one of the electrodes 14 ⁇ , 16 j , 18 ⁇ , 20 j shown schematically in Figure 2.
• a first conductive pad 36 is connected to the source of the low reference potential gnd.
• a second conductive pad is connected to the source of the high reference potential Vcc.
• a third conductive pad 36 is connected to the row electrode 18i and receives the selection and timing signal Comi.
• a fourth conductive pad 36 is connected to the column electrode 20 j and receives the data signal Data j .
• the dimensions of the conductive pads 36 and the arrangement of the conductive pads 36 on the face 34 are in particular imposed by the design rules of the display pixel 12j_ ,j and by the method of assembling the display pixels 12j_ ,j in the display screen 10.
• FIG. 4 represents a known example of a block diagram of a display pixel 12j_ ,j of the display screen 10. In FIG. 4, it has been indicated, above each block, the voltage power supply used to power the electronic components of the block.
• the display pixel 12j_, j comprises at least three light-emitting diodes, a single light-emitting diode LED being represented in FIG. 4.
• Each light-emitting diode LED is connected in series to a controllable current source CS, comprising for example an MOS transistor.
• the anode of the light-emitting diode LED is for example connected to the conductive pad 36 receiving the high reference potential Vcc and the cathode of the light-emitting diode LED is for example connected to a terminal of the controllable current source CS, the other terminal of the controllable current source CS being connected to the conductive pad 36 receiving the low reference potential Gnd.
• the display pixel 12 i; j further comprises a circuit 40 for controlling the controllable current source CS.
• the driver circuit 40 may in particular comprise electronic components such as MOS transistors. It may be desirable to use a reduced supply voltage, less than 4 V, for example of the order of 1 V or 1.8 V, to supply the electronic components of the driver circuit 40, this voltage of reduced feeding corresponding, for example, to the voltage likely to be applied between the power terminals of the MOS transistors.
• the display pixel 12 ij comprises a circuit 42 (Vdd Generation) for supplying, from the supply voltage Vcc, a reduced supply voltage Vdd used in particular for supplying the circuit of control 40.
• Circuit 42 comprises for example a voltage divider.
• the selection and timing signal Comi received at one of the conductive pads 36 of each display pixel 12j_, j , is a binary signal alternating between a low state "0" and a high state “1", the low state corresponding to the low reference potential Gnd and the high state “1" corresponding to a low voltage, for example approximately 1 V, strictly lower than the reduced supply voltage Vdd.
• the data signal Data j is a binary signal alternating between a low state "0" and a high state "1", the low state corresponding to the low reference potential Gnd and the high state "1" corresponding to a low voltage , for example approximately 1 V, strictly lower than the reduced supply voltage Vdd.
• the driver circuit 40 comprises a circuit 44 (Clk & data separation) connected to the conductive pad 36 receiving the data signal Data j and supplying, from the data signal Data j , a clock signal Clk and data Data.
• the driver circuit 40 comprises a circuit 46 (Mode selection) receiving the signals Clk and Data, connected to the conductive pad 36 receiving the selection and timing signal Comi, and configured to supply the signals Clk and Data to a circuit 48 (Color Data registers) for storage or to supply a PWM signal to a circuit 50 (LED driver) for controlling the controllable current source CS associated with each light-emitting diode LED.
• the memory circuit 48 is configured to store signals from color R, G, B representative of the image pixel to be displayed.
• Circuit 50 is suitable for controlling the controllable current sources CS connected to the light-emitting diodes LED with signals I_red, I_green, and I_blue, obtained from the color signals R, G, B, and from the PWM signal.
• the data signals Data j allow both the determination, by each display pixel 12i, j , a clock signal and color signals R, G, B representative of the desired light intensities for the radiation at the first, second and third wavelengths.
• FIG. 5 represents a timing diagram of signals received by the display pixels 12i ,j having the structure represented in FIG. 4 during the display of an image on the display screen 10.
• the potentials Vcc and Gnd are substantially constant.
• the image pixels of a new image to be displayed are displayed successively from the row of rank 1 to the row of rank M.
• the duration of frame T is called the duration separating two successive selections of the same row of the screen of display 10.
• Timing diagrams of the Comi and Datai signals will be detailed for the row of rank 1, knowing that the timing diagrams of the Comi signals are similar to the timing diagram of the Comi signal although shifted in time.
• the display of a new image pixel by a display pixel 12i j , j varying from 1 to N, of the row of rank 1 comprises a first phase PI followed by a second phase P2.
• phase PI data signals Data j are transmitted to each display pixel 12i ,j of the row of rank 1, only the signal Datai being represented in FIG. 5.
• the light-emitting diodes of each display pixel 12i j are controlled from the color signals R, G, B, determined from the data signals Data j .
• the selection and timing signal Comi is set to state "1".
• the setting to state "1" of the signal Comi for a long period is detected by the circuit 46 of each display pixel 12i , j of the row of rank 1 and thus allows the selection of the display pixels 12i , j of this row, the display pixels of the other rows not being selected.
• the data signals Data j are transmitted to the column electrodes 20 j .
• circuit 44 determines clock signal Clk and data Data from the pulses of data signal Data j .
• each pulse of the data signal Data j can have a first duration or a second duration, strictly greater than the first duration.
• the signal Clk can correspond to a series of pulses of the same durations, the rising edges of which coincide, to within a possible constant offset, with the rising edges of the pulses of the data signal Data j .
• the data Data may correspond to a binary signal in state "0" when the pulse of signal Data j has the first duration, and in state "1" when the pulse of signal Data j has the second duration.
• Circuit 46 selected by signal Comi at state "1" supplies, at the rate of clock signal Clk, the data Data which is stored in circuit 50 in the form of digital signals R, G,
• the end of the first PI period for a row corresponds to the start of the first PI period for the following row.
• the light-emitting diodes of the display pixel 12i ,j are controlled by pulse width modulation or control PWM (English acronym for Pulse Width Modulation).
• PWM Pulse Width Modulation
• the selection and timing signal Comi presents the repetition of a succession of pulses at state "1" which are transmitted by the circuit 46 of each display pixel 12i, j from the row of rank 1 to the circuit 50 (PWM signal) to clock the operation of the circuit 50 for controlling the light-emitting diodes LED by pulse-width modulation.
• the number of pulses of the succession corresponds to the number of bits of each digital signal R, G, and B.
• the current source CS corresponds to an MOS transistor
• this transistor is turned on or is blocked , at the rate of the PWM pulses, according to the "0" or "1" value of each bit of the color signal R, G, or B starting with the most significant bit, the transistor being kept on or off until 'at the next pulse of the Comi signal.
• the duration between two successive pulses of the signal Comi is divided each time by two, so that the total duration during which the light-emitting diode is lit depends on the value of the color signal R, G, or B.
• the succession of pulses of the signal Comi is repeated until the next first phase PI of the row of rank 1, a single repetition being illustrated by way of example in figure 5.
• the static consumption of the display pixel 12 ij is largely due to electronic components other than the MOS transistors of the driver circuit 40, in particular the circuit 42 for supplying the reduced supply voltage Vdd.
• the current trend is to increase the number of display pixels 12i, j of the display screen 10.
• the static consumption of the display pixels can then become a critical factor. Indeed, for a so-called 4K display screen 10, having a resolution of 2160 by 3840 display pixels, the static consumption of the display screen 10 can be greater than 150 W.
• one of the conductive pads 36 is used to receive the high supply voltage Vcc and another conductive pad 36 is used to receive the reduced supply voltage Vdd without modifying the total number of conductive pads 36.
• the generation of the reduced supply voltage is no longer carried out within each display pixel 12j_, j and the static consumption of the display screen is reduced .
• the side dimensions of the display pixels 12j_, j may not be changed.
• the structure of the driver circuit 40 of the display pixel 12j_, j is modified and some of the signals supplied to the display pixel 12 i;j are modified.
• FIG. 6 shows, partially and schematically, an embodiment of a display screen 60.
• the display screen 60 comprises all the elements of the display screen 10 of the figure 1, with the difference that the electrodes 16 j , j varying from 1 to N, supply the reduced supply voltage Vdd and that the row electrodes 18i, i varying from 1 to M, supply the high supply voltage Vcci which contains part of the timing signal.
• Column electrodes 20 j supply the signals of data Data j and the electrodes 14 ⁇ provide the low reference potential as for the display screen 10.
• FIG. 7 represents an example block diagram of a display pixel 12 ⁇ rj of the display screen 60.
• the display pixel 12 ⁇ rj of the display screen 60 has the same structure as the display pixel 12i, j of the display screen 10 represented in FIG. 4, with the difference that it does not include the circuit 42 for supplying the reduced supply voltage Vdd and that it further comprises a circuit 62 (Vcc pulses detection) for detecting pulses of the signal Vcci which supplies the selection and timing signal Comi to the selection circuit 46.
• the reduced supply voltage Vdd is directly supplied by one of the conductive pads 36.
• FIG. 8 represents a timing diagram of signals received by the display pixels 12i, j having the structure represented in FIG. 7 during the display of an image on the display screen 60.
• Each signal Vcci i varying from 1 to M, is a binary signal which varies between a state "1" in which the signal Vcci is equal to the high supply voltage Vcc described previously, for example of the order of 4 V at 5 V, and a "0" state, in which the signal Vcci is substantially equal to the low reference potential GND.
• Each signal Vcci has a first phase Pi followed by a second phase P2.
• phase P1 data signals Data j are transmitted to each display pixel 12 ij of the row of rank i, only the signal Datai being represented in FIG. 8.
• each pixel display 12i, j are controlled from the color signals R, G, B, determined from the data signals Data j .
• the signal Coitii supplied by the circuit 62 of each display pixel 12 ij , therefore varies between states "0" and "1" in a complementary manner to the signal Vcci, the state "0" corresponding for example to the low reference potential GND and state "1" corresponding to a low voltage, for example about 1 V, equal for example to the reduced supply voltage Vdd.
• the operation of the rest of the pilot circuit 40 is therefore identical to what was previously described in relation to FIG. In particular, during the first phase PI, the signal Vcci is set to state “0”.
• the setting to state "0" of the signal Vcci for a long period is detected by the circuits 62 and 46 of each display pixel 12_, j of the row of rank i and thus allows the selection of the display pixels 12j_ ,j of this row, the display pixels of the other rows not being selected.
• the data signals Data j are transmitted to the column electrodes 20 j .
• circuit 44 determines clock signal Clk and data Data from the pulses of data signal Data j , for example as described previously.
• Circuit 46 selected by signal Comi in state "1" supplies, at the rate of clock signal Clk, the data Data which is stored in circuit 50 in the form of digital signals R, G, B whose bits are given by the successive values of the Data signal.
• the signal Vcci presents the repetition of a succession of pulses in the "0" state which are converted by the circuit 62 of each display pixel 12i , j of the rank row i in pulses at state "1" of signal Comi.
• These pulses are transmitted by the circuit 46 of each display pixel 12j_ ,j of the row of rank i to the circuit 50 (PWM signal) to clock the operation of the circuit 50 for controlling the light-emitting diodes LEDs by pulse width modulation, for example as previously described.
• the durations of the pulses in state "0" of each signal Vcci during the phases P1 and P2 are less than at least 75% of the duration of the frame T, preferably at least 80%, more preferably at least 85% of the duration of the frame T.
• the signal Vcci is therefore most of the time equal to the high supply voltage Vcc, and the supply of the light-emitting diodes LED is not substantially disturbed by the pulses of the Vcci signal. This would not have been the case if the high supply voltage had been transported by the data signals Data j which themselves vary substantially continuously between the high and low states.
• the light emitting diodes LED are in a common anode configuration. It may however be desirable to arrange the LEDs in a common cathode configuration.
• FIG. 9 represents an exemplary block diagram of a display pixel 12j_, j of the display screen 60 in which the light-emitting diodes LED of the display pixel 12 i;j are in a configuration with common cathode
• the display pixel 12 i;j represented in FIG. 9 has the same structure as the display pixel 12 i;j represented in FIG.
• FIG. 10 represents a timing diagram of signals received by the display pixels 12j_, j having the structure represented in FIG. 9 during the display of an image on the display screen 60.
• Each signal Vee ⁇ i varying from 1 to M, is a binary signal which varies between a "1" state in which the signal Vee ⁇ is equal to the reduced supply voltage Vdd described above, for example of the order of 1 V or 1.8 V, and a "0" state, in which the signal Vee ⁇ is at a reference potential strictly lower than the reference potential GND, for example at a negative potential, in particular of the order of -2.2 V or -3 V, so that the difference between the potentials Vdd and Vee is equal to the high supply voltage Vcc described above.
• the signal Vee ⁇ evolves like the signal Comi described previously.
• the circuit 62 is not present insofar as, as the signal Vee ⁇ evolves like the signal Comi, it can be used directly by the circuit 46. However, as the dynamics of the signal Vee ⁇ is different from that of the signal Comi, it may be desirable to provide that the circuit 62 is adapted to supply the signal Comi from the signal Veei.
• the PWM modulation could be generated internally in the control circuit 30 of the display pixel 12j_, j in order to avoid the use of the Comi signal to generate it.
• Other embodiments could also not use PWM modulation but linear diode driving LED light emitting.
• Other embodiments could also use other electro-optical components such as organic light-emitting diodes.

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• Engineering & Computer Science (AREA)
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• Computer Hardware Design (AREA)
• General Physics & Mathematics (AREA)
• Theoretical Computer Science (AREA)
• Control Of Indicators Other Than Cathode Ray Tubes (AREA)
• Control Of El Displays (AREA)
• Led Device Packages (AREA)
• Led Devices (AREA)
• Devices For Indicating Variable Information By Combining Individual Elements (AREA)

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• 2021
  • 2021-03-31 FR FR2103309A patent/FR3121569B1/fr active Active
• 2022
  • 2022-03-30 JP JP2023560744A patent/JP2024513859A/ja active Pending
  • 2022-03-30 EP EP22719573.2A patent/EP4315308A1/de active Pending
  • 2022-03-30 WO PCT/EP2022/058460 patent/WO2022207730A1/fr active Application Filing
  • 2022-03-30 CN CN202280025625.6A patent/CN117136400A/zh active Pending
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