EP4243061A1 - Mos-transistor auf soi-struktur - Google Patents

Mos-transistor auf soi-struktur Download PDF

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Publication number
EP4243061A1
EP4243061A1 EP23160299.6A EP23160299A EP4243061A1 EP 4243061 A1 EP4243061 A1 EP 4243061A1 EP 23160299 A EP23160299 A EP 23160299A EP 4243061 A1 EP4243061 A1 EP 4243061A1
Authority
EP
European Patent Office
Prior art keywords
transistor
conductive via
region
contact
body region
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
EP23160299.6A
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English (en)
French (fr)
Inventor
Sebastien Cremer
Frederic Monsieur
Alain Fleury
Sebastien Haendler
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics Crolles 2 SAS
STMicroelectronics France SAS
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STMicroelectronics SA
STMicroelectronics Crolles 2 SAS
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Filing date
Publication date
Application filed by STMicroelectronics SA, STMicroelectronics Crolles 2 SAS filed Critical STMicroelectronics SA
Publication of EP4243061A1 publication Critical patent/EP4243061A1/de
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/535—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including internal interconnections, e.g. cross-under constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53257—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being a refractory metal
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78639—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with a drain or source connected to a bulk conducting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/78654—Monocrystalline silicon transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365

Definitions

  • MOS Metal Oxide Semiconductor
  • MOS transistors integrated in and on an SOI structure have already been proposed.
  • MOS transistors on SOI structure have many advantages including high integration density and high electrical performance.
  • one embodiment provides a device comprising an active semiconductor layer on and in contact with an insulating layer, the device comprising at least one transistor comprising a source region, a drain region and a body region arranged in the layer. active, the body region being connected to a conductive via passing through the insulating layer.
  • the insulating layer is arranged on and in contact with a semiconductor substrate, the conductive via being adapted to electrically connect the body region to the semiconductor substrate.
  • the device comprises a body contact pad, connected to the body region, the contact pad being connected to the conductive via by a metal track of an interconnection network of the device.
  • said metal track is entirely arranged in the lowest level of metal tracks of the interconnection network.
  • the conductive via is isolated laterally from the active layer.
  • the conductive via is made of a metallic material, for example tungsten.
  • the transistor comprises a stack of a gate insulator and a conductive gate surmounting the body region between the source and drain regions.
  • the transistor is a PDSOI transistor.
  • the device comprises a plurality of transistors arranged in and on the active layer, the device comprising, for each transistor, a specific conductive via per transistor, connected to the body region of the transistor and passing through the insulating layer.
  • the device includes a plurality of transistors formed in and on the active layer, the conductive via being connected to body regions of several transistors of the device.
  • Another embodiment provides a method of manufacturing a device comprising an active semiconductor layer on and in contact with an insulating layer, the device comprising a transistor including a source region, a drain region and a body region formed in the active layer, the method comprising formation of a conductive via connected to the body region and passing through the insulating layer.
  • the body contact pad and the conductive via are formed simultaneously during the same metal deposition step.
  • the transistor is surrounded by an insulating trench, the conductive via being formed in the insulating trench.
  • the expressions “approximately”, “approximately”, “substantially”, and “of the order of” mean to the nearest 10%, preferably to the nearest 5%.
  • FIG. 1A represents, in a partial and schematic top view, an example of device 1 comprising a MOS transistor 11.
  • FIG. 1B represents a first sectional view of the device 1 of the Figure 1A , there Figure 1B being a view according to the section plane BB of the Figure 1A .
  • FIG. 1C represents a second sectional view of the device 1 of the Figure 1A , there Figure 1C being a view according to the cutting plane CC of the Figure 1A .
  • FIG. 1D represents a third sectional view of the device 1 of the Figure 1A , there Figure 1D being a view according to the cutting plane DD of the Figure 1A .
  • the transistor 11 is formed in and on an SOI structure comprising a support substrate 13 made of a semiconductor material, for example silicon, surmounted by a buried insulating layer 15, for example silicon dioxide (SiO 2 ), itself surmounted by an active semiconductor layer 17, for example made of silicon, for example made of monocrystalline silicon.
  • a support substrate 13 made of a semiconductor material, for example silicon, surmounted by a buried insulating layer 15, for example silicon dioxide (SiO 2 ), itself surmounted by an active semiconductor layer 17, for example made of silicon, for example made of monocrystalline silicon.
  • the substrate 13 has a thickness of between 200 ⁇ m and 800 ⁇ m, for example between 500 ⁇ m and 800 ⁇ m, for example of the order of 775 ⁇ m.
  • substrate 13 is a highly resistive substrate, for example with a resistivity of between 1 k ⁇ .cm and 10 k ⁇ .cm, for example, between 2 k ⁇ .cm and 8 k ⁇ .cm.
  • Substrate 13 is for example doped with P type.
  • substrate 13 is doped with boron atoms.
  • the doping level of substrate 13 is between 10 12 at/cm 3 and 10 13 at/cm 3 .
  • the buried insulating layer 15 has for example a thickness of between 100 nm and 400 nm, for example between 100 nm and 250 nm, for example of the order of 200 nm.
  • the active semiconductor layer 17 has for example a thickness of between 30 nm and 500 nm, for example between 50 nm and 200 nm, for example of the order of 75 nm.
  • the buried insulating layer 15 is formed on and in contact with the semiconductor substrate 13 so that the lower face of the buried insulating layer 15 is in contact with the upper face of the semiconductor substrate 13.
  • the active semiconductor layer 17 is for example formed on and in contact with the buried insulating layer 15 so that the lower face of the active semiconductor layer 17 is in contact with the upper face of the buried insulating layer 15.
  • the device 1 may comprise a plurality of transistors 11, for example identical or similar, integrated in and on the SOI structure.
  • the transistor 11 comprises a source region 19 and a drain region 21 formed in the active semiconductor layer 17.
  • the source 19 and drain 21 regions are laterally separated from each other by a body region 23 (body ).
  • An upper part 23a of the body region 23 constitutes the channel forming region of the transistor 11.
  • the source 19, drain 21 and body 23 regions are flush with the upper face of the active semiconductor layer 17. .
  • the transistor 11 is, for example, a P-channel MOS transistor (PMOS), that is to say a transistor whose source 19 and drain 21 regions are P-type doped, for example doped with boron atoms. , while the body region 23 is doped with type N, for example doped with arsenic or phosphorus atoms.
  • PMOS P-channel MOS transistor
  • NMOS N-channel MOS
  • transistor 11 is a PDSOI transistor (from the English “Partially Depleted Semiconductor On Insulator”), that is to say a transistor in which, in the absence of polarization, the body area is partially depleted (in contrast with FDSOI transistors - from the English “Fully Depleted Semiconductor On Insulator” - semiconductor on insulator totally depleted, in which, in the absence of polarization, the body area is fully depleted).
  • PDSOI transistor from the English “Partially Depleted Semiconductor On Insulator”
  • FDSOI transistors - from the English “Fully Depleted Semiconductor On Insulator” - semiconductor on insulator totally depleted, in which, in the absence of polarization, the body area is fully depleted
  • the transistor 11 comprises one or more contact pads 27 surmounting the source region 19 and electrically connected to the source region 19, and one or more contact pads 29 surmounting the drain region 21 and electrically connected to the drain region 21
  • the source contact pads 27 are in contact, via their lower faces, with the upper face of the source region 19
  • the drain contact pads 29 are in contact, via their lower faces, with the upper face of the drain region 21.
  • the contact pads 27, 29 allow electrical contact between the source 19 and drain 21 regions of the transistor 11 and other components via a network of interconnection not shown in figures 1A, 1B , 1C and 1D .
  • Figure 1A three contact pads 27 and three contact pads 29 have been shown, in practice, the number of contact pads of each type may be different from three.
  • the contact pads 27, 29 are, for example, made of a metallic material, for example tungsten.
  • the source region 19 and the drain region 21 are more heavily doped locally in contact with the pads 27 and 29 in order to optimize the electrical contact between the regions 19, 21 and, respectively, the contact pads. 27 and 29.
  • the source 19 and drain 21 regions extend, for example, orthogonal to the cutting plane of the Figure 1B , along the cutting plane DD of the Figure 1A on a first width L1.
  • the transistor 11 further comprises a conductive gate 31 located above the channel forming region 23a, facing the channel forming region 23a.
  • the gate 31 is separated from the channel forming region 23a by an insulating layer 33 called gate insulator.
  • the gate insulator is made of silicon dioxide (SiO 2 ) and has, for example, a thickness of between 1 nm and 10 nm, for example, of the order of 5 nm.
  • the gate insulator 33 is for example in contact, via its lower face, with the upper face of the channel forming region 23a, and, via its upper face, with the lower face of the conductive grid 31.
  • the grid 31 is, for example, covered, on the side of its upper face, by an insulating passivation layer 35, for example made of silicon dioxide. Insulating spacers can also cover the sides of the gate 31 and the sides of the gate insulator 33.
  • the insulating spacers are, for example, made of silicon nitride (Si 3 N 4 ) and/or silicon dioxide ( SiO 2 ).
  • Gate 31 is, for example, made of doped polycrystalline silicon.
  • the gate 31, the gate insulator 33 and the passivation layer 35 extend laterally beyond the channel forming region 23a.
  • the gate 31 is connected to one or more components via contact pads 37 also called gate contacts, and an interconnection network not shown.
  • the gate contacts 37 are offset outside of the channel forming region 23a.
  • four gate contacts 37 have been shown.
  • the number of contacts of grid 37 can be different from four.
  • the gate contacts 37 are metallic, for example the same material as the source 27 and drain 29 contact pads, for example tungsten.
  • the grid contact pads 37 are in contact, via their lower faces, with the upper face of the grid 31.
  • the body region 23 extends laterally, beyond the source 19 and drain 21 regions, by a body contact recovery region 23b flush with the upper face of the active layer 17.
  • body contact recovery region 23b is not covered by gate 31.
  • Transistor 11 of the figures 1A, 1B , 1C and 1D comprises, in contact with the body contact recovery region 23b, one or more contact pads 39 called body contact pads.
  • the transistor 11 comprises a single body contact pad 39.
  • the body contact pad 39 is, for example, on and in contact, mechanically and electrically, with the body contact recovery region 23b.
  • the body contact recovery region 23b is more heavily doped locally in the vicinity of the contact pad 39 in order to optimize the electrical contact between the region 23 and the contact pad 39.
  • the contact pad 39 allows electrical contact between the body region 23 of the transistor 11 and other components via an interconnection network not shown in figures 1A, 1B , 1C and 1D .
  • the contact pad 39 is preferably made of a metallic material, for example identical to the material of the contact pads 27, 29.
  • the contact pad 39 is, for example made of tungsten.
  • the transistor 11 is surrounded laterally by an insulating trench 25, for example of type STI (from the English "Shallow Trench Isolation" - shallow insulation trench).
  • the insulating trench 25 thus forms a ring around the transistor 11.
  • the insulating trench 25 extends, for example, vertically, from the upper face of the active semiconductor layer 17, through the entire thickness of the active semiconductor layer 17 so as to reach the buried insulating layer 15.
  • the insulating trench 25 opens into the buried insulating layer 15.
  • the insulating trench 25 can pass entirely through the buried insulating layer 15. and all or part of the thickness of the substrate 13.
  • the source 19 and drain 21 regions are in contact, laterally, with a side of the trench 25.
  • the insulating trench 25 makes it possible to electrically isolate the transistor 11 other components (not visible in the figure) of the device.
  • the transistor 11 is, for example, covered by an interconnection network not shown in figures 1A, 1B , 1C and 1D , making it possible to connect the transistor 11, via its contact pads 27, 29, 37 and 39, to other components.
  • the interconnection network comprises, for example, several stacked metallization levels, separated two by two by insulating levels which are themselves crossed by metal vias.
  • the production of the interconnection network may include plasma etching and mechanical-chemical planarization steps capable of generating parasitic electrical charges which are likely to be trapped at the interfaces between the body region 23 and the insulating layers 15 and 25. More particularly, the plasmas used to carry out the engravings are generated from high electrical voltages. The etching process is thus carried out under conditions of significant electric fields which is likely to cause the introduction of charges parasites in body region 23. In addition, mechano-chemical planarization processes can generate parasitic charges by electro-friction type mechanisms. The accumulation of these parasitic charges undesirably modifies the electrical properties of the transistor 11. This problem of injecting parasitic charges at the interfaces with the layers 15 and/or 25 arises particularly when producing the metallization level(s).
  • upper parts of the interconnection network generally relatively thick, for example with a thickness of between 1 ⁇ m and 10 ⁇ m, for example of the order of 3 ⁇ m to 6 ⁇ m.
  • it is planned to form, before the production of higher metallization levels of the interconnection network of the device, a conduction path between the body region 23 of the transistor 11 and the semiconductor substrate 13 of the SOI structure, so as to create an evacuation path for parasitic charges and avoid their trapping at the interfaces with the layers 15 and 25 delimiting the body region 23.
  • FIG. 2A represents, in a partial and schematic top view, an example of device 2 comprising a MOS transistor 111 according to one embodiment.
  • FIG. 2B represents a sectional view of the device 2 of the Figure 2A , there Figure 2B being a sectional view according to the sectional plane BB of the Figure 2A .
  • Device 2 of Figures 2A and 2B includes elements in common with device 1 of the figures 1A, 1B , 1C and 1D .
  • transistor 111 is similar to transistor 11 illustrated in figures 1A, 1B , 1C and 1D .
  • these elements will not be detailed again below.
  • Device 2 of Figures 2A and 2B differs from device 1 of figures 1A, 1B , 1C and 1D essentially in that, in the mode of realization of the Figures 2A and 2B , the device 2 comprises a conductive via 41 or VTB (from the English "Via Through Box") extending vertically through the active layer 17 (more particularly, in the example shown, through an insulating region 25 crossing the active layer 17) and the buried insulating layer 15 and opening into or on and in contact with the upper face of the semiconductor substrate 13.
  • VTB from the English "Via Through Box”
  • the body region 23 of the transistor 11 is connected, preferably connected, to the semiconductor substrate 13 by the conductive via 41. More particularly, in this example, the body region 23 and the semiconductor substrate 13 are connected, preferably connected, electrically, via the contact pad 39 and the conductive via 41.
  • the contact pad 39 and the conductive via 41 are connected, preferably connected, to each other, for example directly, by a metal track 43, for example in copper.
  • the metal track 43 is in contact, mechanically and electrically, via its lower face, with the upper face of the body contact pad 39 and with the upper face of the conductive via 41.
  • the metal track 43 is for example example a track of the first metallization level M1 (corresponding to the lowest level) of the interconnection network formed on the side of the upper face of the device.
  • the conductive via 41 is for example isolated laterally from the active layer 17.
  • the conductive via 41 is formed facing a part of the SOI structure in which the active layer 17 has previously been removed and replaced by a material dielectric, for example silicon dioxide (for example at the same time as the insulating trenches 25 are formed).
  • the conductive via 41 has a width greater than the width of the contact pad 39.
  • the conductive via 41 has, for example, a width of between 10 nm and 300 nm, for example between 50 nm and 200 nm, for example of the order of 150 nm.
  • the conductive via 41 is, for example, made of a metallic material, for example identical to the material of the contact pads 27, 29, 37 and/or 39, for example made of tungsten.
  • the conductive via 41 is, for example, located in the vicinity of the body contact pad 39.
  • the conductive via 41 is formed in the insulation region 25 (as illustrated in Figures 2A and 2B ) laterally delimiting transistor 111.
  • the conductive vias 41 can be shared. That is to say that a via conductor 41 can be common to several transistors 111, for example, neighboring ones. In other words, the same conductor via 41 can allow the evacuation of charges accumulated in and around several transistors 111, for example neighboring ones.
  • the body contact pads 39 of said transistors are electrically connected together, for example by metal tracks of the lower level(s) of the interconnection network.
  • the device may include a specific via conductor 41 per transistor.
  • the conductive via 41 is, for example, formed between a step of forming a pre-metallic dielectric (not detailed in the figures) on the upper face of the active layer 17 and of the gate 31 and steps of forming the levels metallization of the interconnection network of the device.
  • the formation of the conductive via 41 comprises a step of forming an opening through the insulating trench 25.
  • the formation of the conductive via 41 comprises a step of forming an opening through the dielectric pre-metallic, the active layer 17 and possibly the buried insulating layer 15.
  • the step of forming the opening is followed by a step of filling the opening with the material of the conductive via 41.
  • the formation of the body contact pad 39 comprises for example a step of forming an opening through the pre-metallic dielectric, followed by a step of filling the opening with the material of the pad 39.
  • the opening of the body contact pad 39 and the opening of the conductive via 41 are for example carried out successively during distinct photolithography steps.
  • the opening of the conductive via 41 is, for example, carried out before the opening of the contact pad 39.
  • the filling of the conductive via 41 and the filling of the contact pad 39, with a conductive material are for example carried out simultaneously after the steps formation of the openings, in a single metal deposition step followed, for example, by a mechanical-chemical planarization step.
  • the conductive track 43 can then be formed on and in contact with the upper face of the via 41 and the contact pad 39.
  • the body region 23 of the transistor 111 is electrically connected to the semiconductor substrate 13 via via 41.
  • the upper metallization levels of the interconnection stack can then be formed.
  • the conductive via 41 allows the evacuation of parasitic charges generated, in the body region 23 of the transistor, during the manufacturing steps of the upper metallization levels of the interconnection network of the device.
  • the conductive via 41 also allows the evacuation of charges created during other stages of the manufacturing process such as stages of sawing, grinding, etc. This makes it possible to very significantly limit the trapping of parasitic charges at the interfaces between the body region 23 of the transistor 111 and the insulating layers 15 and/or 25.
  • the substrate 13 can be electrically connected to a reference potential, for example ground, or in contact with a conductive metal support forming a ground plane.
  • the via conductor 41 can be made outside the active part of the transistor, the size of a transistor is therefore not increased.
  • the manufacturing of the conductive via 41 is compatible with the usual manufacturing processes for transistors.

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EP23160299.6A 2022-03-11 2023-03-06 Mos-transistor auf soi-struktur Pending EP4243061A1 (de)

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FR2202143 2022-03-11

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20160336990A1 (en) * 2015-05-15 2016-11-17 Skyworks Solutions, Inc. Radio frequency isolation cavity formation using sacrificial material
US20180061766A1 (en) * 2016-08-26 2018-03-01 Qualcomm Incorporated Semiconductor devices on two sides of an isolation layer
US20180174948A1 (en) * 2016-12-21 2018-06-21 Globalfoundries Inc. Integrated circuit chip with molding compound handler substrate and method

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20160336990A1 (en) * 2015-05-15 2016-11-17 Skyworks Solutions, Inc. Radio frequency isolation cavity formation using sacrificial material
US20180061766A1 (en) * 2016-08-26 2018-03-01 Qualcomm Incorporated Semiconductor devices on two sides of an isolation layer
US20180174948A1 (en) * 2016-12-21 2018-06-21 Globalfoundries Inc. Integrated circuit chip with molding compound handler substrate and method

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