EP4177952B1 - Image sensor - Google Patents

Image sensor Download PDF

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Publication number
EP4177952B1
EP4177952B1 EP22205247.4A EP22205247A EP4177952B1 EP 4177952 B1 EP4177952 B1 EP 4177952B1 EP 22205247 A EP22205247 A EP 22205247A EP 4177952 B1 EP4177952 B1 EP 4177952B1
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EP
European Patent Office
Prior art keywords
trench
electrode
capacitor
image sensor
substrate
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EP22205247.4A
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German (de)
English (en)
French (fr)
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EP4177952A1 (en
Inventor
Hyuk Soon Choi
Sang-Su Park
Hee Sung Shim
Dae Kwn AHN
Min-Jun Choi
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14609—Pixel-elements with integrated switching, control, storage or amplification elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/1463—Pixel isolation structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14603—Special geometry or disposition of pixel-elements, address-lines or gate-electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/1462—Coatings
    • H01L27/14621—Colour filter arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14625—Optical elements or arrangements associated with the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14625—Optical elements or arrangements associated with the device
    • H01L27/14627—Microlenses
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14636—Interconnect structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14641—Electronic components shared by two or more pixel-elements, e.g. one amplifier shared by two pixel elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14643—Photodiode arrays; MOS imagers

Definitions

  • the present disclosure relates to image sensors.
  • An image sensor is one of semiconductor elements that convert optical information into an electrical signal.
  • the image sensor may include a charge coupled device (CCD) image sensor and a complementary metal-oxide semiconductor (CMOS) image sensor.
  • CCD charge coupled device
  • CMOS complementary metal-oxide semiconductor
  • the image sensor may be configured in the form of a package.
  • the package may be configured in a structure that protects the image sensor and at the same time allows light to enter a photo receiving surface or a sensing region of the image sensor.
  • US 2020/0021754 A1 proposes an image sensor comprises a backside-illuminated hybrid bonded stacked chip image senor having a pixel circuit array.
  • a capacitor is formed on each pixel circuit along two adjacent sidewalls of an epitaxial substrate layer facing a deep trench isolation region. The capacitor may also extend along an upper surface of the epitaxial substrate layer.
  • US 2019/0131349 A1 discusses an image sensor including a color filter on a substrate, first and second organic photodiodes on the color filter, and first and second capacitors connected to the first and second organic photodiodes, respectively.
  • An object of the present disclosure is to provide image sensors that have improved reliability in a product.
  • an image sensor is provided in accordance with claim 1. Preferred embodiments are set out in claim 2 et seq.
  • FIG. 1 is a block view illustrating an image sensing device according to some example embodiments of the present disclosure.
  • an image sensing device 1 may include an image sensor 10 and an image signal processor 20.
  • the image sensor 10 may generate an image signal IS by sensing an image of a sensing target using light.
  • the generated image signal IS may be, for example, a digital signal, but the example embodiments of the present disclosure are not limited thereto.
  • the image signal IS may be provided to the image signal processor 20 and then processed by the image signal processor 20.
  • the image signal processor 20 may receive the image signal IS output from a buffer 17 of the image sensor 10 and process the received image signal IS to be easily displayed.
  • the image signal processor 20 may perform digital binning for the image signal IS output from the image sensor 10.
  • the image signal IS output from the image sensor 10 may be a raw image signal from an active pixel sensor array 15 (APS array) without analog binning, or may be the image signal IS for which analog binning has been already performed.
  • the image sensor 10 and the image signal processor 20 may be disposed to be detached from each other as shown.
  • the image sensor 10 may be embedded in a first chip
  • the image signal processor 20 may be embedded in a second chip, whereby the image sensor 10 and the image signal processor 20 may perform communication with each other through a predetermined (or, desired) interface.
  • the example embodiments are not limited to this, and the image sensor 10 and the image signal processor 20 may be implemented by one package, for example, a multi-chip package (MCP).
  • MCP multi-chip package
  • the image sensor 10 may include an active pixel sensor array 15, a control register block 11, a timing generator 12, a row driver 14, a readout circuit 16, a ramp signal generator 13, and a buffer 17.
  • the control register block 11 may control overall operations of the image sensor 10. Particularly, the control register block 11 may directly transmit an operation signal to the timing generator 12, the ramp signal generator 13 and the buffer 17.
  • the timing generator 12 may generate a reference signal that becomes a reference of an operation timing of various elements of the image sensor 10.
  • the operation timing reference signal generated by the timing generator 12 may be transferred to the ramp signal generator 13, the row driver 14, the readout circuit 16, etc.
  • the ramp signal generator 13 may generate and transmit a ramp signal used in the readout circuit 16.
  • readout circuit 16 may include a correlation double sampler (CDS), a comparator, etc.
  • the ramp signal generator 13 may generate and transmit a ramp signal used in the correlation double sampler (CDS), the comparator, etc.
  • the row driver 14 may selectively enable rows of the active pixel sensor array 15.
  • the active pixel sensor array 15 may sense an external image.
  • the active pixel sensor array 15 may include a plurality of pixels.
  • the readout circuit 16 may sample a pixel signal provided from the active pixel sensor array 15, compare the sampled pixel signal with the ramp signal and then convert an analog image signal (data) into a data image signal (data) based on the compared result.
  • the buffer 17 may include, for example, a latch.
  • the buffer 17 may temporarily store the image signal IS that will be provided to the outside, and may transmit the image signal IS to an external memory or an external device.
  • FIG. 2 is a block view illustrating an image sensor according to some example embodiments of the present disclosure.
  • the image sensor 10 of the present embodiment may include a first chip 30 and a second chip 40, which are stacked.
  • the second chip 40 may be stacked on the first chip 30 in a third direction DR3.
  • the first chip 30 may include a sensor array region SAR, a connection region CR, and a pad region PR.
  • the sensor array region SAR may include a region corresponding to the active pixel sensor array 15 of FIG. 1 .
  • a plurality of pixels arranged in two dimensions may be disposed in the sensor array region SAR.
  • the sensor array region SAR may include a light receiving region APS and a light blocking region OB.
  • Active pixels may be arranged in the light receiving region APS to generate an active signal by receiving light.
  • Optical black pixels may be arranged in the light blocking region OB to generate an optical black signal by shielding light.
  • the light blocking region OB may be formed along the periphery of the light receiving region APS, the invention is not limited thereto.
  • a photoelectric conversion element may not be formed inside a portion of the light blocking region OB. Also, in some example embodiments, dummy pixels may be formed in the light receiving region APS adjacent to the light blocking region OB.
  • connection region CR may be formed near the sensor array region SAR. Although the connection region CR may be formed on one side of the sensor array region SAR, the invention is not limited thereto. Wirings may be formed in the connection region CR and configured to transmit and receive electrical signals of the sensor array region SAR.
  • the pad region PR may be formed near the sensor array region SAR.
  • the pad region PR may be formed to be adjacent to the edge of the image sensor according to some example embodiments, but the invention is not limited thereto.
  • the pad region PR may be connected to an external device, and may be configured to transmit and receive an electrical signal between the image sensor and the external device according to some example embodiments.
  • connection region CR is shown as being interposed between the sensor array region SAR and the pad region PR, the invention is not limited thereto.
  • the arrangement of the sensor array region SAR, the connection region CR and the pad region PR may vary as necessary.
  • the second chip 40 may be disposed below the first chip 30 in the third direction DR3, and may include a logic circuit region LC.
  • the second chip 40 may be electrically connected to the first chip 30.
  • the logic circuit region LC of the second chip 40 may be electrically connected to the sensor array region SAR through the pad region PR of the first chip 30, for example.
  • the logic circuit region LC may include a plurality of elements for driving the sensor array region SAR.
  • the logic circuit region LC may include, for example, the control register block 11, the timing generator 12, the ramp signal generator 13, the row driver 14, and the read out circuit 16 of FIG. 1 .
  • FIG. 3 is a circuit view illustrating a unit pixel of an image sensor according to some example embodiments of the present disclosure.
  • each unit pixel of the image sensor may include a photoelectric conversion element PD, a transfer transistor TX, a reset transistor RX, a first source follower transistor SF1, a pre-charge transistor PC, a first sampling transistor SMP1, a second sampling transistor SMP2, a second source follower transistor SF2, a selection transistor SEL, a first capacitor C1, and a second capacitor C2.
  • the photoelectric conversion element PD may generate and accumulate charges (photo charges) in proportion to the amount of light incident from the outside (e.g. from outside the image sensor).
  • the photoelectric conversion element PD may include, but is not limited to, at least one of, for example, a photo diode, a photo transistor, a photo gate, a pinned photodiode (PPD), or their combination.
  • the transfer transistor TX may be connected between the photoelectric conversion element PD and a floating diffusion region FD.
  • the transfer transistor TX may be controlled by a transmission signal input to a gate electrode (transfer gate electrode). When the transfer transistor TX is turned on, charges accumulated in the photoelectric conversion element PD may be transmitted to the floating diffusion region FD.
  • the floating diffusion region FD may receive the charges generated by the photoelectric conversion element PD and accumulatively store the charges.
  • a potential of a gate electrode of the first source follower transistor SF1 may vary depending on the amount of the charges accumulated in the floating diffusion region FD.
  • the reset transistor RX may periodically reset the charges accumulated in the floating diffusion region FD.
  • the reset transistor RX may be controlled by a reset signal input to a gate electrode (reset gate electrode).
  • a source of the reset transistor RX may be connected to the floating diffusion region FD.
  • a predetermined (or desired) electrical potential e.g., second power voltage Vpix2
  • Vpix2 second power voltage
  • a gate electrode (first source/follower gate electrode) of the first source follower transistor SF1 may be connected to the floating diffusion region FD.
  • the first source follower transistor SF1 may be a source follower buffer amplifier for amplifying a potential change of the floating diffusion region FD to generate a source/drain current.
  • a drain of the first source follower transistor SF1 may be connected to a power voltage (e.g., first power voltage Vpix1), and a source of the first source follower transistor SF1 may be connected to a node nd.
  • the first sampling transistor SMP1 may be connected between the source (or node nd) of the first source follower transistor SF1 and the first capacitor C1.
  • the first capacitor C1 may be connected to the first sampling transistor SMP1.
  • a first electrode of the first capacitor C1 may be connected to the first sampling transistor SMP1, and a predetermined (or desired) electrical potential (e.g., second power voltage Vpix2) may be applied to a second electrode of the first capacitor C1.
  • the first sampling transistor SMP1 may be controlled by a first sampling signal input to the gate electrode (first sampling gate electrode). When the first sampling transistor SMP1 is turned on, the first capacitor C1 may sample an electrical signal of the node nd.
  • the second sampling transistor SMP2 may be connected between the source (or node nd) of the first source follower transistor SF1 and the second capacitor C2.
  • the second capacitor C2 may be connected to the second sampling transistor SMP2.
  • a first electrode of the second capacitor C2 may be connected to the second sampling transistor SMP2, and a predetermined (or desired) electrical potential (e.g., second power voltage Vpix2) may be applied to a second electrode of the second capacitor C2.
  • the second sampling transistor SMP2 may be controlled by a second sampling signal input to the gate electrode (second sampling gate electrode). When the second sampling transistor SMP2 is turned on, the second capacitor C2 may sample the electrical signal of the node nd.
  • a gate electrode (second source/follower gate electrode) of the second source follower transistor SF2 may be connected to the node nd.
  • the second source follower transistor SF2 may be a source follower buffer amplifier for amplifying a potential change of the node nd to generate a source/drain current.
  • a drain of the second source follower transistor SF2 may be connected to the power voltage (e.g., second power voltage Vpix2), and a source of the second source follower transistor SF2 may be connected to a drain of the selection transistor SEL.
  • the selection transistor SEL may select a unit pixel to be read in a row unit.
  • the selection transistor SEL may be controlled by a selection signal input to a gate electrode (selection gate). When the selection transistor SEL is turned on, the pixel signal may be output to an output line V OUT .
  • the operation of the unit pixel of the image sensor may include a reset step of resetting the photoelectric conversion element PD and the floating diffusion region FD, an optical accumulation step of accumulating photoelectric charges in the photoelectric conversion element PD, and a sampling step of outputting the accumulated photo charges as a pixel signal.
  • the sampling step may include a noise signal sampling step and an image signal sampling step.
  • the reset transistor RX and the transfer transistor TX may be turned on. Therefore, a power voltage (e.g., second power voltage Vpix2) may be provided to the floating diffusion region FD, and the charges of the photoelectric conversion element PD and the floating diffusion region FD may be discharged and reset.
  • a power voltage e.g., second power voltage Vpix2
  • the transfer transistor TX may be turned off.
  • the photo charges may be generated and accumulated in the photoelectric conversion element PD until the turned-off transfer transistor TX is turned on again (e.g., during the photoelectric conversion time).
  • the floating diffusion region FD may be reset to the power voltage (e.g., second power voltage Vpix2) to provide a noise signal.
  • the noise signal may include a noise component.
  • the noise signal, which includes the noise component, may be amplified by the first source follower transistor SF1.
  • the first sampling transistor SMP1 may be turned on, and the first capacitor C1 may sample the first sampling signal that includes the noise component.
  • the first capacitor C1 may be precharged to remove the previously sampled voltage, so that the first source follower transistor SF1 may sample a new voltage. This precharging operation may be performed by a precharge transistor PC.
  • the second sampling transistor SMP2 may be turned off.
  • the transfer transistor TX may be turned on again.
  • the image signal may be amplified by the first source follower transistor SF1.
  • the second sampling transistor SMP2 may be turned on, and the second capacitor C2 may sample the image signal.
  • the second capacitor C2 may be precharged by removing the previously sampled voltage, so that the first source follower transistor SF1 may sample a new voltage. This precharging operation may be performed by a precharge transistor PC. In the image signal sampling step, the first sampling transistor SMP1 may be turned off.
  • Each unit pixel of the image sensor may perform a correlated double sampling (CDS) operation.
  • CDS correlated double sampling
  • each of the unit pixels may doubly sample the noise signal and the image signal to output a difference level corresponding to a difference between the noise signal and the image signal to the output line V OUT . Therefore, the pixel signal from which the noise component is removed may be output to the output line V OUT .
  • FIG. 4 is a layout view illustrating an image sensor according to some example embodiments of the present disclosure.
  • FIG. 5 is a cross-sectional view taken along line A-A of FIG. 4 .
  • FIG. 6 is a cross-sectional view taken along line B-B of FIG. 4 .
  • the image sensor may include a substrate 110, a photoelectric conversion element 120, a wiring structure IS1, a first planarization layer 140, a grid pattern 150, a first passivation layer 155, a second planarization layer 160, a color filter 170, a micro lens 180, a second passivation layer 185, a capacitor structure 200, and a first capacitor isolation pattern 230.
  • the substrate 110 may be a semiconductor substrate.
  • the substrate 110 may be bulk silicon or silicon-on-insulator (SOI).
  • SOI silicon-on-insulator
  • the substrate 110 may be a silicon substrate, or may include other materials such as silicon germanium, indium antimonide, lead telluride compound, indium arsenide, indium phosphide, gallium arsenide and/or gallium antimonide.
  • the substrate 110 may be formed of an epitaxial layer on the base substrate.
  • the substrate 110 may include a first surface 110a and a second surface 110b, which are opposite to each other.
  • the first surface 110a may be referred to as a back side of the substrate 110
  • the second surface 110b may be referred to as a front side of the substrate 110.
  • the first surface 110a of the substrate 110 may be a photo receiving surface upon which light is incident. That is, the image sensor according to some example embodiments may be a back side illuminated (BSI) image sensor.
  • BSI back side illuminated
  • a wiring 133 may be electrically connected to the unit pixels PX1 to PX4.
  • the wiring 133 may be connected to a transistor Tr.
  • the plurality of unit pixels PX1 to PX4 may be formed in the substrate 110.
  • Each of the unit pixels PX1 to PX4 may have a polygonal shape on a plane.
  • the plurality of unit pixels PX1 to PX4 may be arranged in two dimensions (e.g., in a matrix form) on a plane that includes a first direction DR1 and a second direction DR2, as shown in FIG. 4 , and may have a rectangular shape.
  • Each of the unit pixels PX1 to PX4 may include a photoelectric conversion element 120.
  • the photoelectric conversion element 120 may be formed in the substrate 110.
  • the photoelectric conversion element 120 may generate charges in proportion to the amount of light incident from the outside.
  • the photoelectric conversion element 120 may be formed by doping impurities in the substrate 110.
  • the photoelectric conversion element 120 may be formed by ion-implantation of n-type impurities into the p-type substrate 110.
  • the photoelectric conversion element 120 may have a potential slope in a vertical direction (e.g., direction crossing the first surface 110a and the second surface 110b of the substrate 110) perpendicular to an upper surface of the substrate 110.
  • the photoelectric conversion element 120 may be a stacked form of a plurality of impurity regions.
  • the photoelectric conversion element 120 may be the photoelectric conversion element PD of FIG. 3 .
  • Each of the unit pixels PX1 to PX4 may include a transistor Tr.
  • the transistor Tr may be formed on the second surface 110b of the substrate 110.
  • the transistor Tr may be connected to the photoelectric conversion element 120 to constitute various transistors for processing an electrical signal.
  • the transistor Tr may constitute transistors such as the transfer transistor TX, the reset transistor RX, the source follower transistors SF1 and SF2 or the selection transistor SEL of FIG. 3 .
  • the transistor Tr may include a vertical transfer transistor.
  • a portion of the transistor Tr constituting the transfer transistor TX may be extended into the substrate 110.
  • the transfer transistor TX may reduce an area of the unit pixel, thereby enabling high integration of the image sensor.
  • a first trench 210t may be formed in the substrate 110.
  • the first trench 210t may be extended in the first direction DR1 and the second direction DR2 in the substrate 110.
  • the first trench 210t may be formed to surround each of the unit pixels PX1 to PX4 in plan view. In plan view, the first trench 210t may be formed in a lattice shape in the substrate 110 to separate the plurality of unit pixels PX1 to PX4.
  • the first trench 210t may be extended from the second surface 110b to the first surface 110a of the substrate 110.
  • the first trench 210t may be, for example, a deep trench formed by patterning the substrate 110.
  • the first trench 210t may include a first sidewall 210S1 and a second sidewall 210S2, which are opposite to each other in the substrate 110.
  • the first sidewall 210S1 and the second sidewall 210S2 may be opposite to each other in a direction in which the first trench 210t is extended.
  • a first insulating layer 201 may be extended along the first sidewall 210S1 of the first trench 210t.
  • a second insulating layer 202 may be extended along the second sidewall 210S2 of the first trench 210t.
  • the first insulating layer 201 and the second insulating layer 202 may include, but are not limited to, at least one of, for example, silicon nitride, silicon oxynitride, or silicon oxide.
  • the capacitor structure 200 may be formed in the first trench 210t.
  • the capacitor structure 200 may fill the first trench 210t between the first insulating layer 201 and the second insulating layer 202.
  • the capacitor structure 200 may be extended along the extended direction of the first trench 210t.
  • the capacitor structure 200 may include a first electrode 211 formed on the first sidewall 210S1 of the first trench 210t, a second electrode 212 formed on the second sidewall 210S2 of the first trench 210t, and a first dielectric layer 221 between the first electrode 211 and the second electrode 212.
  • the first electrode 211 may be extended along the first sidewall 210S1, and the second electrode 212 may be extended along the second sidewall 210S2.
  • the first electrode 211 may be disposed between the first insulating layer 201 and the first dielectric layer 221, and the second electrode 212 may be disposed between the first dielectric layer 221 and the second insulating layer 202.
  • Each of the first electrode 211 and the second electrode 212 may include, but is not limited to, at least one of a high melting point metal layer such as cobalt, titanium, nickel, tungsten and molybdenum, and/or a metal nitride layer such as a titanium nitride layer (TiN), a titanium silicon nitride layer (TiSiN), a titanium aluminum nitride layer (TiAlN), a tantalum nitride layer (TaN), a tantalum silicon nitride layer (TaSiN), a tantalum aluminum nitride layer (TaAlN) and a tungsten nitride layer (WN), or their combination.
  • a high melting point metal layer such as cobalt, titanium, nickel, tungsten and molybdenum
  • a metal nitride layer such as a titanium nitride layer (TiN), a titanium silicon nitride layer (
  • the first dielectric layer 221 may include, but is not limited to, at least one of a metal oxide such as HfO 2 , ZrO 2 , Al 2 O 3 , La 2 O 3 , Ta 2 O 3 and TiO 2 , a dielectric material having a perovskite structure such as SrTiO 3 (STO), (Ba,Sr)TiO 3 (BST), BaTiO 3 , PZT and PLZT, or their combination.
  • the first dielectric layer 221 may be a single layer or a multi-layer.
  • the first capacitor isolation pattern 230 may be formed in the substrate 110.
  • the first capacitor isolation pattern 230 may be disposed at an intersection point of the first trench 210t in view of a plane.
  • the first capacitor isolation pattern 230 may be disposed to correspond to a lattice point of the first trench 210t. Therefore, the capacitor structure 200 may be disposed on a side of each of the unit pixels PX1 to PX4.
  • the capacitor structure 200 may be divided into a first capacitor structure 311 and a second capacitor structure 321 by the first capacitor isolation pattern 230.
  • Each of the unit pixels PX1 to PX4 may include a first capacitor structure 311 and a second capacitor structure 321.
  • the first capacitor structure 311 may be disposed on a right side of each of the unit pixels PX1 to PX4 in the first direction DR1, and the second capacitor structure 321 may be disposed on a lower surface of each of the unit pixels PX1 to PX4 in the second direction DR2.
  • the first capacitor structure 311 may extend in the second direction D2, and the second capacitor structure 312 may extend in the first direction D1.
  • the first capacitor isolation pattern 230 may isolate the first capacitor structure 311 of the first unit pixel PX1 from the first capacitor structure 311 of the third unit pixel PX3, and may isolate the second capacitor structure 321 of the first unit pixel PX1 from the second capacitor structure 321 of the second unit pixel PX2.
  • the first capacitor isolation pattern 230 may fill spaces among the first capacitor structure 311 of the first unit pixel PX1, the first capacitor structure 311 of the third unit pixel PX3, the second capacitor structure 321 of the first unit pixel PX1, and the second capacitor structure 321 of the second unit pixel PX2 in the first trench 210t.
  • the first capacitor structure 311 may correspond to the first capacitor C1 of FIG. 3
  • the second capacitor structure 321 may correspond to the second capacitor C2 of FIG. 3
  • the first capacitor structure 311 may correspond to the second capacitor C2 of FIG. 3
  • the second capacitor structure 321 may correspond to the first capacitor C1 of FIG. 3 .
  • the first capacitor isolation pattern 230 may fill the first trench 210t between the first capacitor structure 311 and the second capacitor structure 321. That is, the first capacitor isolation pattern 230 may be formed by filling the lattice point of the first trench 210t.
  • the first capacitor isolation pattern 230 may include, for example, a material different from that of the substrate 110.
  • the first capacitor isolation pattern 230 may include an insulating material.
  • the wiring structure IS1 may be formed on the substrate 110. In some example embodiments, the wiring structure IS1 may be formed on the second surface 110b of the substrate 110.
  • the wiring structure IS1 may be comprised of one or a plurality of wirings.
  • the wiring structure IS1 may include an interconnection insulating layer 130, a first pad 131_1, a second pad 131_2, a first contact 132_1, a second contact 132_2, a third contact 132_3, and a wiring 133 in the interconnection insulating layer 130.
  • the number of wiring layers constituting the wiring structure IS1 and the arrangement thereof is not particularly limited, and a connection via electrically connecting the wiring layers is formed between the wiring layers.
  • the first pad 131_1 and the second pad 131_2 may be formed on the second surface 110b of the substrate 110.
  • the first pad 131_1 and the second pad 131_2 may be electrically connected to the capacitor structure 200.
  • the first contact 132_1 may be electrically connected to the first pad 131_1.
  • the second contact 132_2 may be electrically connected to the second pad 131_2.
  • the first electrode 211 may receive a voltage through the first contact 132_1 and the first pad 131_1, and the second electrode 212 may receive a voltage through the second contact 132_2 and the second pad 131_2.
  • the first electrode 211 and the second electrode 212 may be provided with a negative voltage during an effective integration time that accumulates photo charges in the photoelectric conversion element PD. Therefore, the first electrode 211 and the second electrode 212 may reduce a dark current during the effective accumulation time. In addition, the first electrode 211 and the second electrode 212 may allow light incident upon a unit pixel to totally reflect light incident upon another adjacent unit pixel, whereby crosstalk may be deteriorated.
  • any one of the first electrode 211 and the second electrode 212 may be provided with a second power voltage (Vpix2 of FIG. 2 ).
  • a voltage applied to the first electrode 211 and the second electrode 212 may be selectively provided, and therefore, the capacitor structure 200 may serve as a capacitor, and may also serve as a total reflection plate for preventing or reducing crosstalk.
  • the wiring 133 may be electrically connected to the transistor Tr through the third contact 132_3.
  • the third contact 132_3 may connect the wiring 133 with a gate electrode or a source/drain region of the transistor Tr by passing through the interconnection insulating layer 130.
  • the first planarization layer 140 may be formed on the first surface 110a of the substrate 110.
  • the first planarization layer 140 may cover the first surface 110a of the substrate 110.
  • the first planarization layer 140 may include an insulating material.
  • the first planarization layer 140 may include at least one of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, hafnium oxide, or their combination.
  • the first planarization layer 140 may be formed of a multi-layer.
  • the first planarization layer 140 may include, but is not limited to, an aluminum oxide layer, a hafnium oxide layer, a silicon oxide layer, a silicon nitride layer, and a hafnium oxide layer, which are sequentially stacked on the first surface 110a of the substrate 110.
  • the first planarization layer 140 serves as an anti-reflective layer to prevent or reduce reflection of light incident upon the substrate 110, thereby improving a light receiving rate of the photoelectric conversion element 120.
  • the first planarization layer 140 may serve as a planarization layer to form the color filter 170 and the micro lens 180, which will be described later, at a uniform height.
  • the color filter 170 may be formed on the first planarization layer 140.
  • the color filter 170 may be arranged to correspond to the respective unit pixels PX1 to PX4.
  • the plurality of color filters 170 may be arranged in two dimensions (e.g., in a matrix form) on a plane that includes a first direction X and a second direction Y.
  • the color filter 170 may have various color filters depending on the unit pixels PX1 to PX4.
  • the color filter 170 may be arranged in a bayer pattern that includes a red color filter, a green color filter, and a blue color filter, but the invention is not limited thereto.
  • the color filter 170 may include a yellow filter, a magenta filter, and a cyan filter, and may further include a white filter.
  • a first color filter, corresponding to a first pixel unit on the substrate, and a second color filter, corresponding to a second pixel unit on the substrate and isolated from the first color filter may be configured to sense the same color.
  • the color filter 170 and the micro lens 180 may be sequentially stacked on the first surface of the substrate 110.
  • a grid pattern 150 may be formed between the color filters 170.
  • the grid pattern 150 may be formed on the first planarization layer 140.
  • the grid pattern 150 may be formed in a lattice shape in view of a plane, and may be interposed between the color filters 170.
  • the grid pattern 150 may be disposed to overlap the capacitor structure 200 in a vertical direction perpendicular to the upper surface of the substrate 110.
  • the grid pattern 150 may include a conductive pattern 151 and a low refractive index pattern 153.
  • the conductive pattern 151 and the low refractive index pattern 153 may be sequentially stacked on the first planarization layer 140.
  • the conductive pattern 151 may include a conductive material.
  • the conductive pattern 151 may include at least one of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), aluminum (Al), copper (Cu), or their combination, but is not limited thereto.
  • the conductive pattern 151 may prevent or reduce charges generated by ESD, etc. from being accumulated on the surface (e.g., first surface 110a) of the substrate 110, thereby effectively avoiding an ESD bruise defect.
  • the low refractive index pattern 153 may include a low refractive index material having a refractive index lower than that of silicon (Si).
  • the low refractive index pattern 153 may include at least one of silicon oxide, aluminum oxide, tantalum oxide, or their combination, but is not limited thereto.
  • the low refractive index pattern 153 may improve condensing efficiency by refracting or reflecting light that is obliquely incident, thereby improving quality of the image sensor.
  • the first passivation layer 155 may be formed on the first planarization layer 140 and the grid pattern 150.
  • the first passivation layer 155 may be extended to be conformal along an upper surface of the first planarization layer 140, and a profile of a side and an upper surface of the grid pattern 150.
  • the first passivation layer 155 may include, for example, aluminum oxide, but is not limited thereto.
  • the first passivation layer 155 may prevent or reduce the first planarization layer 140 and the grid pattern 150 from being damaged.
  • the second planarization layer 160 may be formed on the color filter 170.
  • the second planarization layer 160 may cover the color filter 170.
  • the second planarization layer 160 may include an insulating material.
  • the second planarization layer 160 may include silicon oxide, but is not limited thereto.
  • the micro lens 180 may be formed on the second planarization layer 160.
  • the micro lens 180 may be arranged to correspond to the respective unit pixels PX1 to PX4.
  • the plurality of micro lenses 180 may be arranged in two dimensions (e.g., in a matrix form) on a plane that includes a first direction DR1 and a second direction DR2.
  • the micro lens 180 may have a convex shape, and may have a predetermined (or desired) radius of curvature. Therefore, the micro lens 180 may condense the light incident upon the photoelectric conversion element 120.
  • the micro lens 180 may include, but is not limited to, a light-transmissive resin.
  • the second passivation layer 185 may be formed on the micro lens 180.
  • the second passivation layer 185 may be extended along a surface of the micro lens 180.
  • the second passivation layer 185 may include an inorganic oxide layer.
  • the second passivation layer 185 may include at least one of silicon oxide, titanium oxide, zirconium oxide, hafnium oxide, or their combination.
  • the second passivation layer 185 may include a low temperature oxide (LTO).
  • LTO low temperature oxide
  • the second passivation layer 185 may protect the micro lens 180 from the outside.
  • the second passivation layer 185 may include an inorganic oxide layer to protect the micro lens 180 that includes an organic material.
  • the second passivation layer 185 may improve quality of the image sensor by improving condensing efficiency of the micro lens 180.
  • the second passivation layer 185 may fill a space between the micro lenses 180, thereby reducing reflection, refraction, and scattering of incident light that reaches the space between the micro lenses 180.
  • the capacitor structure 200 may be disposed in the first trench 210t that is a deep trench in the substrate 110. Therefore, an area of the capacitor structure 200 may be more increased than the case that the capacitor is formed on the second surface 110b of the first substrate 100, whereby capacitance of the capacitor structure 200 may be increased.
  • FIG. 7 is a layout view of an image sensor according to some example embodiments of the present disclosure.
  • FIG. 8 is a cross-sectional view taken along line B-B of FIG. 7 .
  • FIG. 5 For convenience of description, portions duplicated with those described with reference to FIGS. 1 to 6 will be described briefly or omitted.
  • a cross-sectional view taken along line A-A of FIG. 7 may correspond to FIG. 5 .
  • the first pixel isolation pattern 210 may include the same material as that of the substrate 110.
  • the first trench 210t may be formed between the first capacitor isolation patterns 210. Sides of the first capacitor isolation pattern 210 may be exposed by the first trench 210t. That is, the first trench 210t may be formed by etching the substrate 110 in a lattice shape in plan view except for the first capacitor isolation pattern 210.
  • a first capacitor structure 311 and the second capacitor structure 321 are provided.
  • FIGS. 9 and 10 are layout views illustrating an image sensor according to some example embodiments of the present disclosure. For convenience of description, portions duplicated with those described with reference to FIGS. 1 to 6 will be described briefly or omitted.
  • the capacitor structure 200 may include three or more electrodes. Therefore, capacitance of the capacitor structure 200 may be increased.
  • the capacitor structure 200 may include three electrodes 211, 212 and 213.
  • the capacitor structure 200 may include a first electrode 211, a first dielectric layer 221, a second electrode 212, a second dielectric layer 222, and a third electrode 213.
  • the first electrode 211, the first dielectric layer 221, the second electrode 212, the second dielectric layer 222, and the third electrode 213 may be extended along the extended direction of the first trench 210t.
  • the first electrode 211 may be disposed between the first insulating layer 201 and the first dielectric layer 221, the second electrode 212 may be disposed between the first dielectric layer 221 and the second dielectric layer 222, and the third electrode 213 may be disposed between the second dielectric layer 222 and the second insulating layer 202.
  • a first capacitor structure 311 and a second capacitor structure 321 are provided.
  • the capacitor structure 200 may include four electrodes 211, 212, 213 and 214.
  • the capacitor structure 200 may include a first electrode 211, a first dielectric layer 221, a second electrode 212, a second dielectric layer 222, a third electrode 213, a third dielectric layer 223, and a fourth electrode 214.
  • the first electrode 211 may be disposed between the first insulating layer 201 and the first dielectric layer 221
  • the second electrode 212 may be disposed between the first dielectric layer 221 and the second dielectric layer 222
  • the third electrode 213 may be disposed between the second dielectric layer 222 and the third dielectric layer 223
  • the fourth electrode 214 may be disposed between the third dielectric layer 223 and the second insulating layer 202.
  • a first capacitor structure 311 and a second capacitor structure 321 are provided.
  • FIG. 11 is a layout view illustrating an image sensor according to some example embodiments of the present disclosure. For convenience of description, portions duplicated with those described with reference to FIGS. 1 to 6 will be described briefly or omitted.
  • the image sensor may further include a second capacitor isolation pattern 240.
  • the second capacitor isolation pattern 240 may be formed in the first substrate.
  • the second capacitor isolation pattern 240 may be disposed between first capacitor isolation patterns 230 adjacent to each other.
  • the second capacitor isolation pattern 240 may be disposed between the first capacitor isolation patterns 230 adjacent to each other in the first direction DR1 and between the first capacitor isolation patterns 230 adjacent to each other in the second direction DR2. Therefore, the capacitor structure 200 may include a first capacitor structure 311, a second capacitor structure 321, a third capacitor structure 312, and a fourth capacitor structure 322. The first capacitor structure 311 and the third capacitor structure 312 and the second capacitor structure 321 and the fourth capacitor structure 322 may be isolated by the second capacitor isolation pattern 240.
  • Each of the unit pixels PX1 to PX4 may include more capacitor structures than those described in FIG. 4 .
  • Each of the unit pixels PX1 to PX4 may include a first capacitor structure 311, a second capacitor structure 321, a third capacitor structure 312, and a fourth capacitor structure 322.
  • the first capacitor structure 311 and the third capacitor structure 312 may be disposed on the right side of each of the unit pixels PX1 to PX4 in the first direction DR1, and the second capacitor structure 321 and the fourth capacitor structure 322 may be disposed on a lower surface of each of the unit pixels PX1 to PX4 in the second direction DR2.
  • a distance W11 between the second capacitor isolation pattern 240, which isolates the first capacitor structure 311 from the third capacitor structure 312, and the first capacitor isolation pattern 230 adjacent to one side of the second capacitor isolation pattern 240 may be substantially the same as a distance W12 between the second capacitor isolation pattern 240 and the first capacitor isolation patterns 230 adjacent to the other side of the second capacitor isolation pattern 240. Therefore, capacitance of the first capacitor structure 311 may be substantially the same as that of the third capacitor structure 312.
  • a distance W21 between the second capacitor isolation pattern 240, which isolates the second capacitor structure 321 from the fourth capacitor structure 322, and the first capacitor isolation pattern 230 adjacent to one side of the second capacitor isolation pattern 240 may be substantially the same as a distance W22 between the second capacitor isolation pattern 240 and the first capacitor isolation pattern 230 adjacent to the other side of the second capacitor isolation pattern 240. Therefore, capacitance of the second capacitor structure 321 may be substantially the same as that of the fourth capacitor structure 322.
  • FIG. 12 is a layout view illustrating an image sensor according to some example embodiments of the present disclosure. For convenience of description, portions duplicated with those described with reference to FIG. 11 will be described briefly or omitted.
  • a distance W11 between the second capacitor isolation pattern 240, which isolates the first capacitor structure 311 from the third capacitor structure 312, and the first capacitor isolation pattern 230 adjacent to one side of the second capacitor isolation pattern 240 may be different from a distance W12 between the second capacitor isolation pattern 240 and the first capacitor isolation pattern 230 adjacent to the other side of the second capacitor isolation pattern 240.
  • the distance W11 is larger than the distance W12. Therefore, capacitance of the first capacitor structure 311 may be larger than that of the third capacitor structure 312.
  • a distance W21 between the second capacitor isolation pattern 240, which isolates the second capacitor structure 321 from the fourth capacitor structure 322, and the first capacitor isolation pattern 230 adjacent to one side of the second capacitor isolation pattern 240 may be different from a distance W22 between the second capacitor isolation pattern 240 and the first capacitor isolation pattern 230 adjacent to the other side of the second capacitor isolation pattern 240.
  • the distance W21 is smaller than the distance W22. Therefore, capacitance of the second capacitor structure 321 may be smaller than that of the fourth capacitor structure 322.
  • FIGS. 13 and 14 are layout views illustrating an image sensor according to some example embodiments of the present disclosure. For convenience of description, portions duplicated with those described with reference to FIGS. 1 to 6 will be described briefly or omitted.
  • a unit pixel PX may have a hexagonal shape on a plane.
  • the first trench 210t may be formed to surround the periphery of the unit pixel PX in plan view.
  • First to third capacitor structures 310, 320 and 330 may be formed in the first trench 210t.
  • the first to third capacitor structures 310, 320 and 330 may be isolated from one another by the first capacitor isolation pattern 230.
  • Each of the unit pixels PX1 to PX4 may include the first to third capacitor structures 310, 320 and 330.
  • the unit pixel PX may have an octagonal shape on a plane.
  • the first trench 210t may be formed to surround the periphery of the unit pixel PX in plan view.
  • First to sixth capacitor structures 310, 320, 330, 340, 350 and 360 may be formed in the first trench 210t.
  • the first to sixth capacitor structures 310, 320, 330, 340, 350 and 360 may be isolated from one another by the first capacitor isolation pattern 230.
  • Each of the unit pixels PX1 to PX4 may include the first to sixth capacitor structures 310, 320, 330, 340, 350 and 360.
  • FIGS. 13 and 14 illustrate hexagonal and octagonal shapes of unit pixel PX, however the disclosure is not limited thereto, and other shapes may be used, and in some example embodiments, a combination of different shapes may be used (such as a grid of triangles and rectangles).
  • FIG. 15 is a circuit view illustrating a unit pixel of an image sensor according to some example embodiments of the present disclosure. For convenience of description, portions duplicated with those described with reference to FIG. 3 will be described briefly or omitted.
  • the image sensor may include first and second photoelectric conversion elements PD1 and PD2, and first and second transfer transistors TX1 and TX2.
  • the first transfer transistor TX1 may be connected between the first photoelectric conversion element PD1 and the floating diffusion region FD.
  • the second transfer transistor TX2 may be connected between the second photoelectric conversion element PD2 and the floating diffusion region FD.
  • the first and second transfer transistors TX1 and TX2 may be independently controlled by the transmission signals.
  • the first and second transfer transistors TX1 and TX2 may share the floating diffusion region FD.
  • the first and second photoelectric conversion elements PD1 and PD2 may be disposed in their respective unit pixels UP different from each other, or may be disposed in one unit pixel UP.
  • the first and second transfer transistors TX1 and TX2 may be disposed in their respective unit pixels UP different from each other, or may be disposed in one unit pixel UP.
  • FIG. 16 is a layout view illustrating an image sensor according to some example embodiments of the present disclosure.
  • FIG. 17 is a cross-sectional view taken along line A-A of FIG. 16 .
  • portions duplicated with those described with reference to FIGS. 1 to 6 will be described briefly or omitted.
  • each unit pixel of the image sensor may include two subpixels.
  • the first unit pixel may include first subpixels PX1L and PX1R
  • the second unit pixel may include second subpixels PX2L and PX2R
  • the third unit pixel may include third subpixels PX3L and PX3R
  • the fourth unit pixel may include fourth subpixels PX4L and PX4R.
  • Each of the subpixels PX1L, PX1R, PX2L, PX2R, PX3L, PX3R, PX4L and PX4R may include a photoelectric conversion element 120.
  • a second trench 220t may be formed in the substrate 110.
  • the second trench 220t may be extended in the second direction DR2 in the substrate 110.
  • the second trench 220t may isolate the respective subpixels PX1L, PX1R, PX2L, PX2R, PX3L, PX3R, PX4L and PX4R in view of a plane.
  • the second trench 220t may be extended from the second surface 110b to the first surface 110a of the substrate 110.
  • the second trench 220t may include a third sidewall 220S3 and a fourth sidewall 220S4, which are opposite to each other in the substrate 110.
  • the first sidewall 220S3 and the second sidewall 220S4 may be opposite to each other in a direction in which the second trench 220t is extended.
  • the first insulating layer 201 may be extended along the third sidewall 220S3 of the second trench 220t.
  • the second insulating layer 202 may be extended along the fourth sidewall 220S4 of the second trench 220t.
  • the capacitor structure 200 may be formed in the second trench 220t.
  • the capacitor structure 200 may fill the second trench 220t between the first insulating layer 201 and the second insulating layer 202.
  • the capacitor structure 200 may be extended along the extended direction of the second trench 220t.
  • the capacitor structure 200 may include a first electrode 211 formed on the third sidewall 220S3 of the second trench 220t, a second electrode 212 formed on the fourth sidewall 220S4 of the second trench 220t, and a first dielectric layer 221 between the first electrode 211 and the second electrode 212.
  • the first electrode 211 may be extended along the third sidewall 220S3, and the second electrode 212 may be extended along the fourth sidewall 220S4.
  • the first electrode 211 may be disposed between the first insulating layer 201 and the first dielectric layer 221, and the second electrode 212 may be disposed between the first dielectric layer 221 and the second insulating layer 202.
  • the third capacitor isolation pattern 250 may be formed in the substrate 110.
  • the third capacitor isolation pattern 250 may be disposed at a point where the first trench 210t and the second trench 220t cross each other.
  • each pixel may include a first capacitor structure 313 disposed on a right side of each of the subpixels PX1L, PX2L, PX3L and PX4L in the first direction DR1, a second capacitor structure 323 disposed on a lower surface of each of the subpixels PX1R, PX2R, PX3R and PX4R in the second direction DR2, a third capacitor structure 314 disposed on the right side of each of the subpixels PX1R, PX2R, PX3R and PX4R in the first direction DR1, and a fourth capacitor structure 324 disposed on the lower surface of each of the subpixels PX1R, PX2R, PX3R and PX4R in the second direction DR2.
  • the first electrode 211 and the second electrode 212 of each of the first to fourth capacitor structures 313, 314, 323 and 324 may be provided with a voltage through each of the first contact 132_1
  • FIG. 18 is a circuit view illustrating a unit pixel of an image sensor according to some example embodiments of the present disclosure. For convenience of description, portions duplicated with those described with reference to FIG. 3 will be described briefly or omitted.
  • the image sensor may include first to fourth photoelectric conversion elements PD1 to PD4 and first to fourth transfer transistors TX1 to TX4.
  • the third transfer transistor TX3 may be connected between the third photoelectric conversion element PD3 and the floating diffusion region FD.
  • the fourth transfer transistor TX4 may be connected between the fourth photoelectric conversion element PD4 and the floating diffusion region FD.
  • the first to fourth transfer transistors TX1 to TX4 may be independently controlled by the transmission signals. In some example embodiments, the first to fourth transfer transistors TX1 to TX4 may share the floating diffusion region FD.
  • the first to fourth photoelectric conversion elements PD1 to PD4 may be disposed in their respective unit pixels UP different from one another, or may be disposed in one unit pixel UP.
  • the first to fourth transfer transistors TX1 to TX4 may be disposed in their respective unit pixels XP different from one another, or may be disposed in one unit pixel XP.
  • FIGS. 19 and 20 are layout views of an image sensor according to some example embodiments of the present disclosure. For convenience of description, portions duplicated with those described with reference to FIGS. 1 to 6 will be described briefly or omitted.
  • the first unit pixel PX1 and the second unit pixel PX2 sense light (e.g., light of different wavelength bands) of different colors (170 of FIG. 5 ).
  • the first to fourth unit pixels PX1 to PX4, which are adjacent to one another, may be arranged in the form of a bayer pattern.
  • the first unit pixel PX1 may sense light R of a red wavelength band
  • the second and third unit pixels PX2 and PX3 may sense light G of a green wavelength band
  • the fourth unit pixel PX4 may sense light B of a blue wavelength band.
  • the image sensor may include a plurality of pixel groups PG1 to PG4.
  • the respective pixel groups PG1 to PG4 may include a plurality of unit pixels PX adjacent to one another.
  • the pixel groups PG1 to PG4 may be arranged in two dimensions (e.g., in a matrix form) on a plane that includes a first direction DR1 and a second direction DR2.
  • the pixel groups PG1 to PG4 may include first to fourth pixel groups PG1 to PG4 adjacent to one another.
  • the first pixel group PG1 and the second pixel group PG2 may be arranged along the first direction DR1.
  • the first pixel group PG1 and the third pixel group PG3 may be arranged along the second direction DR2.
  • the fourth pixel group PG4 may be arranged along the second direction DR2 together with the second pixel group PG2, and may be arranged along the first direction DR1 together with the third pixel group PG3. That is, the first pixel group PG1 and the fourth pixel group PG4 may be arranged along a diagonal direction.
  • the first to fourth pixel groups PG1 to PG4 adjacent to one another may be arranged in the form of a bayer pattern.
  • the first pixel group PG1 may sense light R of a red wavelength band
  • the second and third pixel groups PG2 and PG3 may sense light G of a green wavelength band
  • the fourth pixel group PG4 may sense light B of a blue wavelength band.
  • FIG. 21 is a block view illustrating an image sensor according to some example embodiments of the present disclosure. For convenience of description, the following description will be based on a difference from the description made with reference to FIG. 2 .
  • an image sensor 10' may further include a third chip 50.
  • the third chip 50 may be disposed between the first chip 30 and the second chip 40 in the third direction DR3.
  • the third chip 50 may include a memory device.
  • the third chip 50 may include a volatile memory device such as a DRAM, an SRAM, or the like.
  • the third chip 50 may receive signals from the first chip 30 and the second chip 40 to process the signals through the memory device.
  • the image sensor 10 may include hardware including logic circuits; a hardware/software combination such as a processor executing software; or a combination thereof.
  • the processing circuitry more specifically may include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a System-on-Chip (SoC), a programmable logic unit, a microprocessor, application-specific integrated circuit (ASIC), etc.
  • CPU central processing unit
  • ALU arithmetic logic unit
  • FPGA field programmable gate array
  • SoC System-on-Chip
  • ASIC application-specific integrated circuit

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EP22205247.4A 2021-11-05 2022-11-03 Image sensor Active EP4177952B1 (en)

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