EP4099330A4 - Procédé de test de puce de mémoire, dispositif informatique et support - Google Patents

Procédé de test de puce de mémoire, dispositif informatique et support Download PDF

Info

Publication number
EP4099330A4
EP4099330A4 EP21876735.8A EP21876735A EP4099330A4 EP 4099330 A4 EP4099330 A4 EP 4099330A4 EP 21876735 A EP21876735 A EP 21876735A EP 4099330 A4 EP4099330 A4 EP 4099330A4
Authority
EP
European Patent Office
Prior art keywords
medium
computer device
memory chip
testing method
chip testing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
EP21876735.8A
Other languages
German (de)
English (en)
Other versions
EP4099330A1 (fr
Inventor
Jinghong Xu
Yuan-Chieh Lee
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Changxin Memory Technologies Inc
Original Assignee
Changxin Memory Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from CN202110441989.XA external-priority patent/CN115240748A/zh
Application filed by Changxin Memory Technologies Inc filed Critical Changxin Memory Technologies Inc
Publication of EP4099330A1 publication Critical patent/EP4099330A1/fr
Publication of EP4099330A4 publication Critical patent/EP4099330A4/fr
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
    • G11C29/56012—Timing aspects, clock generation, synchronisation
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/022—Detection or location of defective auxiliary circuits, e.g. defective refresh counters in I/O circuitry
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/1201—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details comprising I/O circuitry
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G11C29/50008—Marginal testing, e.g. race, voltage or current testing of impedance
EP21876735.8A 2021-04-23 2021-08-17 Procédé de test de puce de mémoire, dispositif informatique et support Pending EP4099330A4 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202110441989.XA CN115240748A (zh) 2021-04-23 2021-04-23 存储芯片测试方法、计算机设备及介质
PCT/CN2021/112894 WO2022222327A1 (fr) 2021-04-23 2021-08-17 Procédé de test de puce de mémoire, dispositif informatique et support

Publications (2)

Publication Number Publication Date
EP4099330A1 EP4099330A1 (fr) 2022-12-07
EP4099330A4 true EP4099330A4 (fr) 2023-06-07

Family

ID=83693389

Family Applications (1)

Application Number Title Priority Date Filing Date
EP21876735.8A Pending EP4099330A4 (fr) 2021-04-23 2021-08-17 Procédé de test de puce de mémoire, dispositif informatique et support

Country Status (2)

Country Link
US (1) US11721411B2 (fr)
EP (1) EP4099330A4 (fr)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050248375A1 (en) * 2004-05-10 2005-11-10 Hynix Semiconductor Inc. Semiconductor memory device with ability to adjust impedance of data output driver
US20070063731A1 (en) * 2005-07-26 2007-03-22 Nec Electronics Corporation Impedance adjusting circuit and impedance adjusting method
US20070070717A1 (en) * 2005-09-27 2007-03-29 Hynix Semiconductor Inc. Semiconductor memory device for adjusting impedance of data output driver

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4075140B2 (ja) 1998-06-25 2008-04-16 富士通株式会社 電子装置及び半導体記憶装置
JP2000074986A (ja) * 1998-08-31 2000-03-14 Ando Electric Co Ltd デバイス試験装置
KR100557636B1 (ko) 2003-12-23 2006-03-10 주식회사 하이닉스반도체 클럭신호를 이용한 데이터 스트로브 회로
KR100733430B1 (ko) 2005-09-29 2007-06-29 주식회사 하이닉스반도체 반도체 메모리 장치
CN106875966B (zh) 2017-01-09 2020-02-07 上海兆芯集成电路有限公司 数据选通信号处理系统以及处理方法
US10803914B1 (en) 2019-08-27 2020-10-13 Micron Technology, Inc. Selectively squelching differential strobe input signal in memory-device testing system

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050248375A1 (en) * 2004-05-10 2005-11-10 Hynix Semiconductor Inc. Semiconductor memory device with ability to adjust impedance of data output driver
US20070063731A1 (en) * 2005-07-26 2007-03-22 Nec Electronics Corporation Impedance adjusting circuit and impedance adjusting method
US20070070717A1 (en) * 2005-09-27 2007-03-29 Hynix Semiconductor Inc. Semiconductor memory device for adjusting impedance of data output driver

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of WO2022222327A1 *

Also Published As

Publication number Publication date
US11721411B2 (en) 2023-08-08
EP4099330A1 (fr) 2022-12-07
US20220343997A1 (en) 2022-10-27

Similar Documents

Publication Publication Date Title
EP4074247A4 (fr) Procédé et dispositif de test d'état de santé et support de stockage informatique
EP3792916A4 (fr) Procédé de traitement de données basé sur une interprétation simultanée, dispositif informatique et support de stockage
EP4120114A4 (fr) Procédé et appareil de traitement de données, dispositif intelligent, et support d'enregistrement
EP4020328A4 (fr) Procédé et appareil de traitement de données, dispositif informatique et support de stockage
EP3989099A4 (fr) Procédé et appareil de conception de puces, dispositif informatique et support de stockage
EP3992800A4 (fr) Procédé et appareil de test de programme, dispositif informatique et support de stockage
WO2017189579A3 (fr) Mise en mémoire cache de données
EP3936996A4 (fr) Procédé de lecture-écriture et dispositif de mémoire
EP3917115A4 (fr) Procédé et appareil de traitement de données, dispositif informatique et support de mémoire
EP4024809A4 (fr) Procédé et appareil d'accès à une application, ainsi que dispositif électronique et support de stockage
EP4042422A4 (fr) Circuit amplificateur de détection, dispositif de mémoire, et son procédé de fonctionnement
EP3964941A4 (fr) Procédé de lecture-écriture et dispositif de mémoire
EP4207629A4 (fr) Procédé et dispositif de transmission de données d'éphémérides, support de stockage, puce et système
CA3143846A1 (en) Communicating method and device, computer equipment and storage medium
EP3885907A4 (fr) Procédé et appareil de traitement de demandes de lecture/écriture, dispositif électronique, et support de stockage
EP4109861A4 (fr) Procédé de traitement de données, appareil, dispositif informatique, et support de stockage
EP4109803A4 (fr) Procédé et dispositif de transmission de données, système de puce, support de stockage lisible par ordinateur
EP3993433A4 (fr) Procédé et dispositif d'incorporation d'informations, appareil et support d'informations informatique
EP4152146A4 (fr) Procédé et dispositif de traitement de données, et support de stockage
EP3951612A4 (fr) Procédé d'enregistrement de données distribuées, dispositif et support d'enregistrement
EP4142347A4 (fr) Procédé et dispositif de configuration de mesure, et support de stockage
EP3926628A4 (fr) Amplificateur de détection, mémoire, et procédé de lecture de données
EP4084552A4 (fr) Procédé de transmission de données, dispositif et puce, et support d'enregistrement lisible
EP3958149A4 (fr) Procédé et dispositif de traitement de données, support de stockage, et dispositif électronique
EP3905251A4 (fr) Circuit d'opération d'écriture, dispositif de mémoire à semi-conducteurs, et procédé d'opération d'écriture

Legal Events

Date Code Title Description
STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: UNKNOWN

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE INTERNATIONAL PUBLICATION HAS BEEN MADE

PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: REQUEST FOR EXAMINATION WAS MADE

17P Request for examination filed

Effective date: 20220422

AK Designated contracting states

Kind code of ref document: A1

Designated state(s): AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR

A4 Supplementary search report drawn up and despatched

Effective date: 20230509

RIC1 Information provided on ipc code assigned before grant

Ipc: G11C 29/02 20060101ALI20230502BHEP

Ipc: G11C 29/50 20060101ALI20230502BHEP

Ipc: G11C 29/12 20060101AFI20230502BHEP