Classifications

• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K1/00—Printed circuits
  • H05K1/02—Details
  • H05K1/0201—Thermal arrangements, e.g. for cooling, heating or preventing overheating
  • H05K1/0203—Cooling of mounted components
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
  • H01L21/4814—Conductive parts
  • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
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  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
  • H01L21/4814—Conductive parts
  • H01L21/4871—Bases, plates or heatsinks
  • H01L21/4882—Assembly of heatsink parts
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  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L23/00—Details of semiconductor or other solid state devices
  • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
  • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
  • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
  • H01L23/3735—Laminates or multilayers, e.g. direct bond copper ceramic substrates
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  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L23/00—Details of semiconductor or other solid state devices
  • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
  • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
  • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
  • H01L23/3736—Metallic materials
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  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L23/00—Details of semiconductor or other solid state devices
  • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
  • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
  • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
  • H01L23/49833—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the chip support structure consisting of a plurality of insulating substrates
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L23/00—Details of semiconductor or other solid state devices
  • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
  • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
  • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
  • H01L23/49838—Geometry or layout
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  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L23/00—Details of semiconductor or other solid state devices
  • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
  • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
  • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
  • H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
  • H01L23/49894—Materials of the insulating layers or coatings
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  • H01L23/00—Details of semiconductor or other solid state devices
  • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
  • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
  • H01L23/5385—Assembly of a plurality of insulating substrates
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
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  • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
  • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
  • H01L24/42—Wire connectors; Manufacturing methods related thereto
  • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
  • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
  • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
  • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
  • H01L25/072—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next to each other
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
  • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K1/00—Printed circuits
  • H05K1/02—Details
  • H05K1/0201—Thermal arrangements, e.g. for cooling, heating or preventing overheating
  • H05K1/0203—Cooling of mounted components
  • H05K1/0209—External configuration of printed circuit board adapted for heat dissipation, e.g. lay-out of conductors, coatings
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K1/00—Printed circuits
  • H05K1/02—Details
  • H05K1/03—Use of materials for the substrate
  • H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K1/00—Printed circuits
  • H05K1/02—Details
  • H05K1/03—Use of materials for the substrate
  • H05K1/05—Insulated conductive substrates, e.g. insulated metal substrate
  • H05K1/053—Insulated conductive substrates, e.g. insulated metal substrate the metal substrate being covered by an inorganic insulating layer
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K1/00—Printed circuits
  • H05K1/02—Details
  • H05K1/11—Printed elements for providing electric connections to or between printed circuits
  • H05K1/111—Pads for surface mounting, e.g. lay-out
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K1/00—Printed circuits
  • H05K1/18—Printed circuits structurally associated with non-printed electric components
  • H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K1/00—Printed circuits
  • H05K1/18—Printed circuits structurally associated with non-printed electric components
  • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
  • H05K1/183—Components mounted in and supported by recessed areas of the printed circuit board
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K3/00—Apparatus or processes for manufacturing printed circuits
  • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
  • H05K3/42—Plated through-holes or plated via connections
  • H05K3/429—Plated through-holes specially for multilayer circuits, e.g. having connections to inner circuit layers
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
  • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
  • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
  • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
  • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
  • H01L2224/321—Disposition
  • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
  • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
  • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
  • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
  • H01L2224/732—Location after the connecting process
  • H01L2224/73251—Location after the connecting process on different surfaces
  • H01L2224/73265—Layer and wire connectors
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
  • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
  • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
  • H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
  • H01L2224/83101—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus as prepeg comprising a layer connector, e.g. provided in an insulating plate member
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
  • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K1/00—Printed circuits
  • H05K1/02—Details
  • H05K1/11—Printed elements for providing electric connections to or between printed circuits
  • H05K1/115—Via connections; Lands around holes or via connections
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
  • H05K2201/06—Thermal details
  • H05K2201/066—Heatsink mounted on the surface of the PCB
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
  • H05K2201/09—Shape and layout
  • H05K2201/09009—Substrate related
  • H05K2201/09036—Recesses or grooves in insulating substrate
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  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
  • H05K2201/09—Shape and layout
  • H05K2201/09209—Shape and layout details of conductors
  • H05K2201/095—Conductive through-holes or vias
  • H05K2201/09545—Plated through-holes or blind vias without lands
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  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
  • H05K2201/09—Shape and layout
  • H05K2201/09209—Shape and layout details of conductors
  • H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
  • H05K2201/09745—Recess in conductor, e.g. in pad or in metallic substrate
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  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
  • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
  • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
  • H05K2201/10621—Components characterised by their electrical contacts
  • H05K2201/10666—Plated through-hole for surface mounting on PCB
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  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
  • H05K2203/04—Soldering or other types of metallurgic bonding
  • H05K2203/049—Wire bonding
• • H—ELECTRICITY
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  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K3/00—Apparatus or processes for manufacturing printed circuits
  • H05K3/0011—Working of insulating substrates or insulating layers
  • H05K3/0017—Etching of the substrate by chemical or physical means
  • H05K3/0026—Etching of the substrate by chemical or physical means by laser ablation
  • H05K3/0029—Etching of the substrate by chemical or physical means by laser ablation of inorganic insulating material
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  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K3/00—Apparatus or processes for manufacturing printed circuits
  • H05K3/0058—Laminating printed circuit boards onto other substrates, e.g. metallic substrates
  • H05K3/0061—Laminating printed circuit boards onto other substrates, e.g. metallic substrates onto a metallic substrate, e.g. a heat sink
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  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K3/00—Apparatus or processes for manufacturing printed circuits
  • H05K3/22—Secondary treatment of printed circuits
  • H05K3/24—Reinforcing the conductive pattern
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  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K3/00—Apparatus or processes for manufacturing printed circuits
  • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
  • H05K3/403—Edge contacts; Windows or holes in the substrate having plural connections on the walls thereof
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  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K3/00—Apparatus or processes for manufacturing printed circuits
  • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
  • H05K3/42—Plated through-holes or plated via connections
  • H05K3/421—Blind plated via connections
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  • H05K3/00—Apparatus or processes for manufacturing printed circuits
  • H05K3/46—Manufacturing multilayer circuits
  • H05K3/4685—Manufacturing of cross-over conductors

Definitions

• the present invention relates to an electronic module and a method for producing an electronic module.
• Metal-ceramic substrates are sufficiently known from the prior art, for example as printed circuit boards or circuit boards, for example from DE 10 2013 104 739 A1, DE 19 927 046 B4 and DE 10 2009 033 029 A1.
• connection surfaces for electrical components and conductor tracks are arranged on one component side of the metal-ceramic substrate, the electrical components and the conductor tracks being able to be interconnected to form electrical circuits.
• Essential components of the metal-ceramic substrates are an insulation layer, which is preferably made from a ceramic, and at least one metal layer attached to the insulation layer. Because of their comparatively high insulation strengths, insulation layers made of ceramic have proven to be particularly advantageous in power electronics. By structuring the metal layer, conductor tracks and / or connection surfaces can then be implemented for the electrical components.
• the object is achieved by an electronic module according to claim 1 and by a method according to claim 7. Further advantages and properties emerge from the subclaims and the description and the accompanying figures.
• an electronics module in particular a power electronics module, is provided, comprising
• a secondary component metallization which is attached to the side of the insulation layer facing away from the metal-ceramic substrate and is in particular insulated from the primary component metallization by the insulation layer, the ceramic element having a first size and the insulation layer having a second size and in order to form a island-like insulation layer on the primary component metallization, a ratio of the second size to the first size assumes a value which is smaller than 0.8, preferably smaller than 0.6 and particularly preferably smaller than 0.4.
• an island-like insulation layer is provided with which, in particular, electrical insulation between the primary component metallization and the secondary component metallization is realized.
• the insulation layer is preferably connected directly to the primary component metalization.
• the insulation layer is part of a further, in particular smaller, metal-ceramic substrate, which in turn is placed on the larger metal-ceramic substrate serving as a carrier and in the context of a DCB or active soldering process or by means of an adhesive is connected to the metal-ceramic substrate.
• the insulation layer is a comparatively thin insulation layer made of ceramic that contributes to the electrical insulation of the secondary component metallization from the primary component metallization. It is particularly provided that the electronics module or the arrangement of the primary component metallization and the secondary component metallization is not completely embedded in an encapsulation or a housing.
• the person skilled in the art understands the first size to mean a first thickness and / or a first length or width or area of the ceramic element and the second size to mean a second thickness and / or second length or width or area of the insulation layer.
• the insulation layer can be strip-shaped, or have an elliptical, circular, diamond-shaped and / or square cross-section.
• the insulation layer is preferably surrounded on all sides by the primary component metallization in a plane running parallel to the main extension plane.
• the insulation layer is arranged at the edge of the primary component metallization so that the insulation layer is at most on three or two sides of the primary component metallization in a plane running parallel to the main extension plane.
• the insulation layer in particular circumferentially, protrudes from the outermost edge of the secondary component metallization, in particular for the purpose of avoiding an electrical flashover between the secondary component metallization and the primary component metallization. It is preferably provided that the insulation layer, in particular circumferentially along an outermost edge of the insulation layer or the secondary component metallization, protrudes in a direction running parallel to the main extension plane of the metal-ceramic substrate opposite an outermost edge of the secondary component metallization, preferably by 10 pm to 500 pm, preferably by 50 pm to 250 pm and particularly preferably by 100 to 150 pm.
• the insulation layer is designed in such a way that its outermost edge protrudes from the secondary component metallization in such a way that it forms a “pullback” that prevents electrical overheating and causes complete electrical insulation of the secondary component metallization from the primary component metallization.
• a ratio of the second thickness to the first thickness assumes a value between 0.03 and 0.8, preferably 0.03 and 0.5 and particularly preferably between 0.03 and 0.3.
• the second thickness has a value between 500 ⁇ m and 1 mm, preferably between 200 ⁇ m and 500 ⁇ m and particularly preferably between 10 ⁇ m and 200 ⁇ m. It has been found that a sufficient insulation strength can be produced with comparatively thin insulation layers.
• the insulation layer advantageously uses the primary component metallization as mechanical stabilization. Due to the comparatively thin second thicknesses, it is advantageously simplified to realize fine structuring or separating sections between electrical components or insulation layers.
• the primary or secondary component metallization and / or the cooling part metallization is connected directly and directly to the insulation layer, for example connected by means of a DCB method, an AMB method or by means of a thin-film technology.
• the metal-ceramic substrate or the further metal-ceramic substrate comprises at least one metal layer, for example as part of the cooling part metallization or the primary or secondary component metallization, which is firmly bonded to an outside of the ceramic element or the insulation layer wherein the metal layer and the ceramic element extend along a main extension plane and are arranged one above the other along a stacking direction running perpendicular to the main extension plane.
• the materials for the metallization or the metal section ie for the primary component metallization, the secondary component metallization, the cooling part metallization and / or a backside metallization are copper, aluminum, molybdenum and / or their alloys, as well as laminates such as CuW, CuMo, CuAI , AlCu and / or CuCu conceivable, in particular a special copper sandwich structure with a first copper layer and a second copper layer, with a grain size in the first copper layer differing from a second copper layer. Furthermore, it is preferably provided that the at least one metallization, ie the primary component metallization or secondary component metallization, is surface-modified.
• SiC SiC
• BeO MgO
• MgO high-density MgO (> 90% of the theoretical density)
• TSZ tetragonally stabilized zircon
• the insulation layer or the ceramic element as Composite or hybrid ceramic is formed in which several ceramic layers, each of which differ in terms of their material composition, are arranged one above the other and are joined together to form an insulation layer to combine various desired properties.
• a ceramic that is as thermally conductive as possible is used for the lowest possible heat resistance.
• a metallic intermediate layer is arranged in the ceramic element or in the insulation layer between two ceramic layers.
• the primary component metallization and / or the cooling part metallization is preferably bonded to the insulating layer by means of an AMB method and / or a DCB method.
• a “DCB process” (direct copper bond technology) or a “DAB process” (direct aluminum bond technology) is understood by those skilled in the art to be such a process which is used, for example, for joining metal layers or sheets (e.g. B. copper sheets or foils or aluminum sheets or foils) is used with one another and / or with ceramic or ceramic layers, using metal or copper sheets or metal or copper foils that have a layer or a coating ( Melting layer) have.
• this layer or this coating (on melting layer) forms a eutectic with a melting temperature below the melting temperature of the metal (e.g. copper), so that through Laying the film on the ceramic and by heating all layers these can be connected to one another, namely by melting the metal or copper essentially only in the area of the melting layer or oxide layer.
• the DCB method then z. B. on the following process steps: • Oxidizing a copper foil in such a way that a uniform copper oxide layer results;
• an active soldering process e.g. B. for connecting metal layers or metal foils, in particular copper layers or copper foils with Kera mikmaterial is a method to understand, which is specifically used for the manufacture of metal-ceramic substrates, is at a temperature between tween about 600-1000 ° C a connection between a metal foil, e.g. copper foil, and a ceramic substrate, for example aluminum nitride ceramic, made using a hard solder which, in addition to a main component such as copper, silver and / or gold, also contains an active metal.
• This active metal which is for example at least one element from the group Hf, Ti, Zr, Nb, Ce, creates a connection between the solder and the ceramic by chemical reaction, while the connection between the solder and the metal is a metallic brazed connection .
• a thick-film process is also conceivable for the connection.
• At least one first electrical component is connected to the primary component metallization and at least one second electrical component is connected to the secondary component metallization, in particular in each case directly adjacent.
• the at least one first electrical component and the at least one second electrical component are thus electrically isolated from one another via the insulation layer.
• the at least one first electrical component and / or the at least one second electrical component is preferably a switchable component or an active or passive component.
• This is preferably a WBG semiconductor (wide bandgap semiconductors), such as.
• B. a semiconductor made of silicon carbide, gallium nitride and / or indium gallium nitride.
• Examples of electronic components are MOSFETs (“metal-oxide-semiconductor field-effect transistors”) or IGBTs (“insulated-gate bipolar transistors”).
• the at least one first electrical component and the at least one second electrical component are connected to one another via a wire bond.
• the connection via the wire bond replaces another conductor path created by structuring the primary component metallization, if necessary.
• the primary component metallization is electrically conductively connected to the secondary component metallization via a through-hole contact or a side contact.
• a recess is integrated into the insulation layer, which is filled with an electrically conductive medium, in particular the metal of the secondary component metallization, during the formation of the secondary component metallization.
• the secondary component metallization protrudes or protrudes at least in sections from the outermost edge of the insulation layer.
• the secondary component metallization runs around the insulation layer and thus forms a side contact from, which overlaps or bypasses the insulation layer at the outermost edge and establishes a connection to the primary component metallization.
• the primary component metallization of the metal-ceramic substrate is unstructured and / or free from structuring that extends up to a ceramic element. This advantageously makes it possible to dispense with an otherwise expensive etching process, in particular an etching process in which the boundary layer between the ceramic element and the primary component metallization has to be etched away as part of a “second etching”.
• the primary component metallization is structured. “Structured” is to be understood in particular to mean that the primary component metallization extends to the ceramic element.
• this free area ie an isolation trench formed by the structuring, can be filled at least partially, preferably completely or in layers, with the isolation layer and / or with a further isolation layer and / or a filling compound, in particular an electrically insulating filling compound.
• the filler compound it is provided in particular that the insulation layer bridges the insulation trench formed and the filler compound supports or supports the insulation layer.
• the filling compound is a plastic or a hard resin.
• the structuring allows a further separation of metal sections, in particular in a plane parallel to the main extension plane, in addition to the separation by the insulation layer in a direction perpendicular to the main extension plane. It is preferably provided that at least one recess is let into the primary component metallization, in which the island-like insulation layer and / or the secondary component metallization is arranged and / or a first electrical component and / or a second electrical component is.
• the secondary component metallization can advantageously be arranged in such a way that it is flush with the primary component metallization, as a result of which the connections to the primary component metallization and the secondary component metallization lie on one level, in particular a plane running parallel to the main extension plane.
• vibration damping elements such as. B. a snubber, which comprises a resistor and a capacitor, to reduce electrical oscillations in the electrical module.
• a vibration damping element also has an advantageous effect on the inductance of the electronics module.
• the recess is dimensioned such that in the assembled state the at least one first electrical component and / or the at least one second electrical component is arranged below an upper side of the primary component metallization or in the assembled state is arranged such that the upper side the primary component metallization is flush with an upper side of the at least one first electrical component and / or of the at least one second electrical component.
• the electronics module comprises an encapsulation in which the metal-ceramic substrate with the insulation layer and the second component metallization is embedded.
• the recess can form a form fit with the encapsulation in this case.
• vias are integrated into the encapsulation in order to be able to control, for example, the first electrical component, the second electrical component and / or the third electrical component via an external metallization on the encapsulation.
• the recess has a depth measured in the stacking direction that assumes a value between 50 pm and 800 pm, preferably between 70 pm and 600 pm and particularly preferably between 100 pm and 400 pm. such as B. chips, integrate in the recess or sink in this. It is also conceivable that the depth assumes a value which is less than 150 ⁇ m, preferably less than 100 ⁇ m and particularly preferably less than 70 ⁇ m.
• the secondary component metallization is structured to form a metal section and at least one further metal section isolated from the metal section. It is preferably provided that the secondary component metallization is thinner than the primary component metallization, since the primary component metallization can mainly be used to dissipate the heat, while the secondary component metallization is preferably intended to isolate metal sections from one another.
• the primary component metallization is preferably more than 5 times, preferably more than 10 times and particularly preferably more than 20 times as thick as the secondary component metallization. In this way, for example, several second electrical components and / or at least one third electrical component can be connected to the insulation layer or to the secondary component metallization.
• Another object of the present invention is a method for the manufacture of an electronic module, in particular an electronic module according to the invention, comprising:
• the ceramic element having a first size and the insulation layer having a second size
• the island-like insulation layer formed on the primary component metallization being dimensioned such that a ratio of second size assumes a value for the first size which is smaller than 0.8, preferably smaller than 0.6 and particularly preferably smaller than 0.5 and
• a layer in particular a continuous flat layer made of an insulation material, is connected to the primary component metallization and the connected layer is structured from the insulation material and / or
• the primary component metallization is applied to the primary component metallization using a mask.
• a mask It is preferably a ceramic-containing insulation material.
• the structuring is carried out by means of a laser or as part of an etching process or a milling process.
• the insulation material is applied to the primary component metallization by means of a deposition process, in particular by means of sputtering or a gas phase deposition process.
• comparatively thin insulation layers can be implemented that have an insulating effect and, in particular, can be applied in a material-saving manner.
• a layer of a metal material is attached to a pre-composite comprising the metal-ceramic substrate and the island-like insulation layer, the layer of the metal material attached to the pre-composite being structured to form the secondary component metallization .
• a secondary initial component metallization is produced which is only a few micrometers, in particular up to 30 ⁇ m, thick. It is through a subsequent enlargement of this secondary initial component metallization possible to realize a secondary pre-component metallization that has a thickness that is greater than the secondary initial component metallization. For example, the thickness of the metallization is increased as part of a galvanic or electrochemical process.
• At least one first electrical component is connected to the primary component metallization and at least one second electrical component is connected to the secondary component metallization, preferably
• the at least one electrical second component and / or the secondary construction part metallization are connected to one another in an electrically conductive manner via a wire bond.
• This makes it possible in an advantageous manner to replace the usually provided conductor track for connecting the at least one electrical component to the at least one second electrical component by the connection via wire bonds.
• This could prove to be advantageous in particular in the context of the manufacture and manufacture and in the context of equipping the electronic modules. Further advantages and features emerge from the following description of preferred embodiments of the subject matter according to the invention with reference to the attached figures. Individual features of the individual embodiment can be combined with one another within the scope of the invention.
• Fig. 1 schematically, an electronic module according to a first exemplary embodiment of the present invention in an exploded view, each equipped and once unequipped and in a composite view
• Fig. 2 schematically an electronic module according to a second exemplary embodiment of the present invention
• Fig. 3 schematically an electronic module according to a third exemplary embodiment of the present invention
• Fig. 4 schematically an electronic module according to a fourth exemplary embodiment of the present invention
• Fig. 5 schematically an electronic module according to a fifth exemplary embodiment of the present invention
• 11a-11f schematically a method for producing an electronic module according to a sixth exemplary embodiment of the present invention.
• an electronic module 100 according to a first exemplary embodiment of the present invention is shown schematically in an exploded view, each unequipped (top) and equipped (center), and shown in a composite view (bottom).
• Such electronic modules 100 include a metal-ceramic substrate 1 as a carrier for at least one first electrical component 51.
• the metal-ceramic substrate 1 serving as a carrier includes a ceramic element 10 on which a primary component metallization 21 on opposite sides and a cooling part metallization 20 are connected.
• the primary component metallization 21 and the cooling part metallization 20 are preferably connected to the ceramic element 10 as part of a DAB or DCB method, ie a direct connection method, or as part of an active soldering method.
• the at least one electrical component 51 can be connected to the metal-ceramic substrate 1 via a first soldering material 31, for example. It can be, for example, at least a first electrical component 51 can be a chip or a microprocessor.
• the prior art typically provides for the primary component metallization 21 to be structured in order to arrange the at least one electrical component 51 on the metal-ceramic substrate 1 in an electrically insulated manner from at least one second electronic component 52.
• an insulation layer 40 is provided for electrical insulation of the at least one first electrical component 51 from the at least one second electrical component 52.
• the insulation layer 40 is part of a further metal-ceramic substrate 2 which is smaller in comparison to the metal-ceramic substrate 1 serving as a carrier.
• the further metal-ceramic substrate 2 is smaller than the metal-ceramic substrate 1 by a factor of 2, preferably by a factor of 4 and particularly preferably by a factor of 7.5, compared to the metal-ceramic substrate 1 serving as a carrier
• the further metal-ceramic substrate 2 comprises a rear-side metallization 23 and a secondary component metallization 22 opposite the rear-side metallization 23.
• the further metal-ceramic substrate 2 is connected to the primary component metallization 21 via a bonding layer 15 tied up.
• the rear-side metallization 23 of the further metal-ceramic substrate 2 is connected to the primary component metallization 21 via the binding layer 15, the binding layer 15 being able to take place in the context of a DCB or DAB direct connection method and / or via an adhesive and / or via a Active solder material.
• the at least one second electrical component 52 is connected to at least one section of the secondary component metallization 22 via a second solder material 32.
• the second solder material 32 can correspond to the first solder material 31 or differ from the first solder material 31.
• the embodiment of FIG. 1 is characterized in that the ceramic element 10 of the metal-ceramic substrate 1 has a first size L1, D1 and the insulation layer 40 has a second size L2, D2 primary component metallization 21, a ratio of the second size L2, D2 to the first size L1, D1 assumes a value that is less than 0.8, preferably less than 0.6 and particularly preferably less than 0.4.
• the insulation layer 40 prevents the at least one first electrical component 51 from being connected in an electrically conductive manner to the at least one second electrical component 52 via the primary component metallization 21.
• a first size L1, D2 to be a first length L1 measured along a main extension plane FISE of the metal-ceramic substrate 1 and / or a first thickness D1 of the ceramic element 10 measured perpendicular to the main extension plane HSE and a second size L2, D2 a second length L2 measured parallel to the main extension plane HSE and / or a second thickness D2 measured perpendicular to the main extension plane HSE.
• the second thickness D2 of the insulation layer 40 is smaller than the first thickness D1 of the ceramic element 10.
• the second thickness D2 is less than 0.8 times the first thickness D1, preferably less than 0.5 times the first thickness D1 and particularly preferably less than 0.3 times the first thickness D1.
• FIG. 2 shows an electronics module 100 according to a second exemplary embodiment of the present invention.
• the embodiment in FIG. 2 essentially supplements that in FIG. 1 in that the at least one first electrical component 51 is connected in an electrically conductive manner to the secondary component metallization 22 via a wire bond 8.
• a wire bond 8 establishes the connection between the at least one first electrical component 51 and the at least one second electrical component 52 realized, the second electrical component 52 being electrically isolated from the primary component metallization 21 via the insulation layer 40.
• the secondary component metallization 22 is structured, in particular in such a way that separate and in particular electrically isolated metal sections are attached to the secondary Form component metallization 22. Furthermore, it is particularly preferably provided that the electronics module 100 has terminal lugs 16 and / or electrical contact means with which an electrical contact to the primary component metallization 21 and / or secondary component metallization 22 can be established. For example, in the exemplary embodiment shown in FIG another connection with a connection lug 16 at which an output signal can be tapped. Furthermore, it is conceivable that different Metallab sections of the secondary component metallization 22 are also connected to one another via a wire bond 8 or a further wire bond 8.
• FIG. 3 A third exemplary embodiment of the present invention is shown in FIG.
• the embodiment of FIG. 3 differs from that of FIGS. 1 and 2 in that the insulation layer 40 is connected directly or directly to the primary component metallization 21 instead of indirectly via the rear-side metallization 23 of the further metal-ceramic substrate 2.
• the insulation layer 40 has a second thickness D2 and the ceramic element 10 has a first thickness D1, the ratio of the second thickness D2 to the first thickness D1 being between 0.03 and 0.8, preferably 0.03 and 0.5 and particularly preferably between 0.03 and 0.3.
• the second thickness D2 has a value of 500 ⁇ m to 1 mm, preferably between 200 ⁇ m and 500 ⁇ m and particularly preferably between 10 ⁇ m and 200 ⁇ m.
• the insulation layer 40 has a second length L2 measured along the main plane of extension HSE of the metal-ceramic substrate 1 and the secondary component metallization 22 has a third length L3 measured along the main plane of extension HSE, the second length L2 being smaller than the third length is L3.
• a ratio of the second length L2 to the third length L3 assumes a value between 0.7 and 0.9, preferably between 0.75 and 0.85 and particularly preferably between 0.78 and 0.82.
• the secondary component metallization 22 is set back in relation to an outermost edge of the insulation layer 40 in the direction of the main extension plane HSE, in particular circumferentially for the entire island-like insulation layer 40 22, which in particular prevents an electrical flashover from occurring between the secondary component metallization 22 and the primary component metallization 21, in particular in the case of comparatively thin layers or layer thicknesses of the insulation layer 40, ie compared to comparatively thin second thicknesses D2.
• the primary component metallization 21 is free of structuring that extend as far as the ceramic element 10.
• the metal-ceramic substrate 1 has a first length L1 measured parallel to the main extension plane HSE, a ratio of the second length L2 to the first length L1 assuming a value that is less than 0.8, preferably less than 0.6 and particularly preferably less than 0.4.
• FIG. 4 an electronics module 100 according to a fourth preferred embodiment of the present invention is shown.
• the exemplary embodiment in FIG. 4 is distinguished from the previous ones in that the primary component metallization 21 has a recessed profile, ie forms at least one recess 45 into which the insulation layer 40 is embedded or within which the insulation layer 40 is arranged or is formed.
• the insulation layer 40 in particular with the secondary component metallization 22 in the recess 45, it is in front partially possible to realize a flush termination along a stacking direction S running perpendicular to the main extension plane HSE between the primary component metallization 21 and the secondary component metallization 22, so that a flat surface of the primary component metallization 21 and the secondary component metallization 22, in particular of each of the ceramic element 10 facing away sides, is provided.
• this is a Snubber47.
• the type of snubber 47 is intended to provide electrical vibration damping between the primary component metallization 21 and the secondary component metallization 22. In such a case, it is advantageously possible, for example, to place the snubber 47 on the jointly provided connection level of the primary component metallization 21 and the secondary component metallization 22 to be arranged.
• FIG. 5 shows an electronics module 100 according to a fifth exemplary embodiment of the present invention.
• the insulation layer 40 carries at least one third electrical component 53 in addition to the at least one second electrical component 52.
• This can be a passive or active SMD component, for example.
• the area below the electrical component 53 is provided for heat dissipation from other components, ie for the first electrical component 51 and second electrical component 52, for example.
• the insulation layer 40 it is possible to equip this Be rich with the third electrical component 53, in particular when a comparatively small amount of heat emanates from the third electrical component 53.
• the top side of the metal-ceramic substrate 1 serving as a carrier is used as comprehensively and as optimally as possible for equipping.
• FIGS. 6a to 6f A method for producing an electronic module 100 according to a preferred embodiment of the present invention is shown in FIGS. 6a to 6f.
• the metal-ceramic substrate 1 is provided in a step not shown.
• Ceramic material is then applied in the form of a thin layer to form the insulation layer 40, at least partially, preferably over the entire surface.
• a targeted local Ab wear in certain areas on the top of the metal-ceramic substrate 1, the full-surface insulation layer 40 is reduced to an island-like insulation layer 40, the second length L2 is smaller than the first length L1 of the metal-ceramic substrate 1 or the first ceramic element 10.
• laser light 55 is used that is provided by a laser source 56 (see FIG. 6b).
• FIG. 6c shows the pre-composite that has been freed from the superfluous subregions of the insulation layer 40.
• a secondary initial component metallization 22 ′ is applied.
• this secondary initial component metallization 22 ' is applied as part of a deposition process, in particular a chemical or physical gas phase deposition process, such as, for example, as part of a sputtering, a PVD, CVD, PECVD or other thin film process.
• a deposition process in particular a chemical or physical gas phase deposition process, such as, for example, as part of a sputtering, a PVD, CVD, PECVD or other thin film process.
• the thickness of the secondary initial component metallization 22' is increased, for example in the context of a galvanic or electrochemical process, to form a secondary pre-component metallization 22 ".
• the secondary pre-construction part metallization 22 “ also extends over the entire extent of the primary Component metallization 21. This state in the manufacturing process is illustrated in FIG. 6e.
• FIG. 6f shows the electronics module 100 following structuring, in particular after parts of the secondary pre-component metallization 22 "have been removed for the purpose of forming the secondary component metallization 22 with the second thickness D2, which preferably has a structured course on the insulation layer 40, in which different metal sections, electrically insulated from one another by the insulation layer 40, are etcbil det on the insulation layer 40.
• a structuring takes place in the context of laser ablation or in the context of an etching process and / or mechanical processing.
• FIGS. 7a to 7e A method according to a second exemplary embodiment of the present invention is shown in FIGS. 7a to 7e.
• the setting method in FIGS. 7a to 7e differs essentially from that from FIGS. 6a to 6f in that the structured insulation layer 40 is not applied over the entire surface and then partially removed again, but rather the application using a masking 61 the insulation layer 40 on the primary component metallization 21 has already been carried out only partially. This advantageously saves the removal of partial areas of the insulation layer 40 applied over the entire surface.
• the method steps illustrated in FIGS. 7c to 7e essentially correspond to those illustrated in FIGS. 6e to 6f.
• FIGS. 8a to 8f show a method for positioning an electronic module 100 according to a third exemplary embodiment of the present invention.
• the embodiment in FIGS. 8a to 8f differs from the embodiment in FIGS running direction is narrower than 1000 pm, in particular narrower than 500 ⁇ m and particularly preferably narrower than 250 ⁇ m During the subsequent metallization of the insulation layer 40, in particular during the multi-level metallization described in FIGS the recess is thus filled, whereby a via 26 is formed in the insulation layer 40 or is possible.
• FIGS. 9a to 9f A method for producing an electronic module 100 according to a fourth exemplary embodiment of the present invention is shown in FIGS. 9a to 9f.
• the embodiment of FIGS. 9a to 9f differs from the embodiment of FIGS. 6a to 6e in that in the structuring of the metallization, which is provided for forming the secondary component metallization 22 (step between 9e and 9f), the secondary pre-component metallization 22 " is structured in such a way that a side contact 27 is formed.
• the side contact 27 extends beyond the edge of the insulation layer 20 and realizes an electrically conductive connection with the primary component metallization 21, which lies under the section of the secondary component metallization 22 that protrudes from the outermost edge of the insulation layer 40.
• FIGS. 10a to 10f A method for producing an electronic module 100 according to a fifth exemplary embodiment of the present invention is shown in FIGS. 10a to 10f.
• the embodiment of FIGS. 10a to 10f differs from the embodiment of FIGS. 6a to 6e in that the primary component metallization 21 is structured or is provided in a structured manner.
• an isolation groove or a free area is formed in the primary component metallization 21 between two metal sections of the primary component metallization 21, which are arranged next to one another in a direction running parallel to the main extension plane HSE.
• the insulation layer 40 runs through the insulation trench, ie the insulation layer 40 covers both the metal sections of the primary component parts.
• the secondary component metallization 22 preferably produced by means of initial component metallization 22 'and pre-component metallization 22 ′′, is structured in such a way that the secondary component metallization 22 runs over the area of the insulation layer 40 that runs inside or through the insulation trench.
• FIGS. 11a to 11f show a method for producing an electronic module 100 according to a sixth exemplary embodiment of the present invention.
• the embodiment of FIGS. 11a to 11f differs from the embodiment of FIGS. 6a to 6e in that the primary component metallization 21 is structured. It is further provided that the recess formed by the structuring or the corresponding isolation trench is filled with a filling compound 29. In particular, the recess or the isolation trench is completely filled.
• a secondary component metallization 22 is formed, which runs over the recess or the isolation trench. This makes it possible in front of geouser to expand the freedom of design in the formation of mutually isolated metal sections.
• FIGS. 8a-8f to 11a-11f can also be produced using the method from the exemplary embodiment in FIGS. 7a to 7e.

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• Condensed Matter Physics & Semiconductors (AREA)
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• 2020
  • 2020-03-10 DE DE102020106521.3A patent/DE102020106521A1/de active Pending
• 2021
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  • 2021-03-08 CN CN202180020693.9A patent/CN115280492A/zh active Pending
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