EP4027458A1 - Dispositif électronique - Google Patents

Dispositif électronique Download PDF

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Publication number
EP4027458A1
EP4027458A1 EP22150111.7A EP22150111A EP4027458A1 EP 4027458 A1 EP4027458 A1 EP 4027458A1 EP 22150111 A EP22150111 A EP 22150111A EP 4027458 A1 EP4027458 A1 EP 4027458A1
Authority
EP
European Patent Office
Prior art keywords
electrode
connecting pad
electronic device
solder
disposed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
EP22150111.7A
Other languages
German (de)
English (en)
Inventor
Chen-Lin Yeh
Chin-Lung Ting
Chung-Kuang Wei
Jen-Hai Chi
Yi-Hung Lin
Yan-Zheng Wu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Innolux Corp
Original Assignee
Innolux Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from CN202111603375.3A external-priority patent/CN114725071A/zh
Application filed by Innolux Corp filed Critical Innolux Corp
Publication of EP4027458A1 publication Critical patent/EP4027458A1/fr
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01Q—ANTENNAS, i.e. RADIO AERIALS
    • H01Q1/00—Details of, or arrangements associated with, antennas
    • H01Q1/12—Supports; Mounting means
    • H01Q1/22—Supports; Mounting means by structural association with other equipment or articles
    • H01Q1/2283—Supports; Mounting means by structural association with other equipment or articles mounted in or on the surface of a semiconductor substrate as a chip-type antenna or integrated with other components into an IC package
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01Q—ANTENNAS, i.e. RADIO AERIALS
    • H01Q15/00—Devices for reflection, refraction, diffraction or polarisation of waves radiated from an antenna, e.g. quasi-optical devices
    • H01Q15/0006—Devices acting selectively as reflecting surface, as diffracting or as refracting device, e.g. frequency filtering or angular spatial filtering devices
    • H01Q15/0013—Devices acting selectively as reflecting surface, as diffracting or as refracting device, e.g. frequency filtering or angular spatial filtering devices said selective devices working as frequency-selective reflecting surfaces, e.g. FSS, dichroic plates, surfaces being partly transmissive and reflective
    • H01Q15/002—Devices acting selectively as reflecting surface, as diffracting or as refracting device, e.g. frequency filtering or angular spatial filtering devices said selective devices working as frequency-selective reflecting surfaces, e.g. FSS, dichroic plates, surfaces being partly transmissive and reflective said selective devices being reconfigurable or tunable, e.g. using switches or diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01Q—ANTENNAS, i.e. RADIO AERIALS
    • H01Q15/00—Devices for reflection, refraction, diffraction or polarisation of waves radiated from an antenna, e.g. quasi-optical devices
    • H01Q15/0006—Devices acting selectively as reflecting surface, as diffracting or as refracting device, e.g. frequency filtering or angular spatial filtering devices
    • H01Q15/006—Selective devices having photonic band gap materials or materials of which the material properties are frequency dependent, e.g. perforated substrates, high-impedance surfaces
    • H01Q15/0066—Selective devices having photonic band gap materials or materials of which the material properties are frequency dependent, e.g. perforated substrates, high-impedance surfaces said selective devices being reconfigurable, tunable or controllable, e.g. using switches

Definitions

  • the disclosure relates to an electronic device.
  • a radio frequency (RF) device is employed to transmit or receive electromagnetic waves, and is thus an indispensable part of wireless communication technology. How to improve directivity of the radio frequency device so that the electromagnetic wave propagates in a specific direction is one of research and development focuses for researchers in the related field.
  • the disclosure provides an electronic device, in which improvement to directivity of a radio frequency device can be facilitated.
  • an electronic device includes a substrate, a first electrode, a second electrode, a modulation element, a first solder, and a switch element.
  • the first electrode is disposed on the substrate.
  • the second electrode is disposed on the substrate.
  • the modulation element is disposed on the substrate and includes at least two connecting pads.
  • the first solder is disposed between the first electrode and one connecting pad of the modulation element.
  • the switch element is disposed on the substrate.
  • the one connecting pad of the modulation element is electrically connected to the switch element sequentially through the first solder, the first electrode, and the second electrode.
  • the terms “about”, “equal to”, “equal”, “same”, “substantially”, or “generally” mentioned herein typically mean within a range of 10% of a given value, or within a range of 5%, 3%, 2%, 1%, or 0.5% of the given value.
  • the terms “the given range is from a first value to a second value” and “the given value falls within a range of a first value to a second value” each mean that the given range includes the first value, the second value, and other values in between.
  • bonds and connection may mean that two structures are in direct contact, or may also mean that two structures are not in direct contact, and other structures are disposed between the two structures.
  • the terms regarding bonding and connection may also include the case where both structures are movable or both structures are fixed.
  • electrical connection refers to series connection between two elements through direct or indirect connection.
  • the two elements may be directly connected, or the two elements may be connected in series through one or more conductive elements.
  • electricalally coupling refers to two elements separated from each other without any other conductive element between the two elements to connect the two in series.
  • the electronic device of the disclosure may include, but is not limited to, a radio frequency device or an electronic device having a radio frequency element.
  • the electronic device may include a bendable or flexible electronic device.
  • the radio frequency element may include a frequency selective surface (FSS), RF-Filter, polarizer, resonator, antenna, or the like.
  • FSS frequency selective surface
  • RF-Filter RF-Filter
  • polarizer polarizer
  • resonator antenna
  • the radio frequency device will be taken as the electronic device below to describe the content of the disclosure. Nonetheless, the disclosure is not limited thereto.
  • FIG. 1A and FIG. 1B are respectively a schematic partial cross-sectional view and a schematic partial top view of an electronic device according to a first embodiment of the disclosure.
  • FIG. 1B omits illustration of some elements and/or film layers of the electronic device.
  • FIG. 1A for the cross-section of section line A-A' in FIG. 1B .
  • an electronic device 1 may include a substrate 10, a first electrode 11, a second electrode 12, a modulation element 13, a first solder 14, and a switch element 15.
  • the first electrode 11 is disposed on the substrate 10.
  • the second electrode 12 is disposed on the substrate 10.
  • the modulation element 13 is disposed on the substrate 10 and includes at least two connecting pads, for example, a connecting pad P1 and a connecting pad P2.
  • the first solder 14 is disposed between the first electrode 11 and one connecting pad (e.g., the connecting pad P1) of the modulation element 13.
  • the switch element 15 is disposed on the substrate 10.
  • the one connecting pad (e.g., the connecting pad P1) of the modulation element 13 is electrically connected to the switch element 15 sequentially through the first solder 14, the first electrode 11, and the second electrode 12.
  • the substrate 10 is configured to carry elements.
  • the substrate 10 may be a rigid substrate, a bendable substrate, or a flexible substrate.
  • the substrate 10 may include, but is not limited to, a glass substrate, a polymer film, a printed circuit board, a base layer formed of ceramics, or a combination of the above.
  • the first electrode 11 is disposed between the substrate 10 and the second electrode 12, and the second electrode 12 is disposed between the first electrode 11 and the switch element 15.
  • the first electrode 11 and the second electrode 12 serve as an intermediate medium for electrically connecting the switch element 15 and the modulation element 13.
  • the materials of the first electrode 11 and the second electrode 12 may include, but is not limited to, copper, aluminum, any material with high conductivity, or a combination of the above.
  • the modulation element 13 is disposed corresponding to the first electrode 11. For example, the modulation element 13 at least partially overlaps the first electrode 11 in the normal direction (e.g., a third direction D3) of the substrate 10. From the top view of the electronic device 1, as shown in FIG. 1B , the modulation element 13 respectively has a width W1 and a width W2 in a first direction D1 and a second direction D2.
  • the width W1 and the width W2 may be greater than or equal to 20 micrometers and less than or equal to 1000 micrometers (20 ⁇ m ⁇ W1 ⁇ 1000 ⁇ m; 20 ⁇ m ⁇ W2 ⁇ 1000 ⁇ m). Nonetheless, the disclosure is not limited thereto.
  • the modulation element 13 includes a variable capacitor.
  • the variable capacitor may be formed by a liquid crystal device, a variable capacitor diode, micro electro mechanical systems (MEMS), or the like. Nonetheless, the disclosure is not limited thereto.
  • the transmission medium of the electromagnetic wave may include, but is not limited to, a transmission line, a waveguide structure, a free space, or the like.
  • the electromagnetic wave may include, but is not limited to, a planar wave, a cylindrical wave, a spherical wave, or the like.
  • the frequency range of the electromagnetic wave may include, but is not limited to, radio frequency, millimeter wave, Terahertz (THz), infrared light, visible light, or the like.
  • the connecting pad P1 of the modulation element 13 is welded on the first electrode 11 through the first solder 14.
  • the first solder 14 may include, but is not limited to, a solder ball, a copper pillar, any other suitable metal, or a metal alloy.
  • the switch element 15 is configured to drive the modulation element 13.
  • the switch element 15 may include a thin film transistor (TFT).
  • TFT thin film transistor
  • the material of the channel layer (not shown) of the thin film transistor may include, but is not limited to, low-temperature polysilicon, amorphous silicon, oxide semiconductor, organic semiconductor, III-V compound semiconductor, or the like.
  • the electronic device 1 may also include other elements or layers.
  • the electronic device 1 may also include a third electrode 16 and a second solder 17. Nonetheless, the disclosure is not limited thereto.
  • the third electrode 16 is disposed on the substrate 10.
  • the third electrode 16 and the first electrode 11 may be manufactured in the same layer.
  • the third electrode 16 and the first electrode 11 may both belong to a first conductive layer C1.
  • the third electrode 16 and the first electrode 11 may have the same material and may be formed by the same patterning process.
  • the second solder 17 is disposed between the third electrode 16 and the other connecting pad (e.g., the connecting pad P2) of the modulation element 13.
  • the other connecting pad (e.g., the connecting pad P2) of the modulation element 13 may be electrically connected to the third electrode 16 through the second solder 17.
  • the connecting pad P2 of the modulation element 13 is welded on the third electrode 16 through the second solder 17.
  • the second solder 17 may include, for example but not limited to, a tin ball, a copper pillar, any other suitable metals, or a metal alloy.
  • the electronic device 1 may also include a fourth electrode 18.
  • the fourth electrode 18 is arranged on the substrate 10.
  • the third electrode 16 is disposed between the fourth electrode 18 and the substrate 10.
  • the fourth electrode 18 and the second electrode 12 may be manufactured in the same layer.
  • the fourth electrode 18 and the second electrode 12 may both belong to a second conductive layer C2.
  • the fourth electrode 18 and the second electrode 12 may have the same material and may be formed by the same patterning process.
  • the first conductive layer C1 may also include a conductive pattern PT1 and a conductive pattern PT2 in addition to the first electrode 11 and the third electrode 16.
  • the first electrode 11 is disposed between the conductive pattern PT1 and the third electrode 16.
  • the first electrode 11, the conductive pattern PT1, and the third electrode 16 are separated from each other.
  • a gap G1 is present between the first electrode 11 and the conductive pattern PT1
  • a gap G2 is present between the first electrode 11 and the third electrode 16.
  • the third electrode 16 is disposed between the first electrode 11 and the conductive pattern PT2.
  • the third electrode 16, the first electrode 11, and the conductive pattern PT2 are separated from each other.
  • a gap G3 is present between the third electrode 16 and the conductive pattern PT2.
  • the conductive pattern PT1 is disposed between the second electrode 12 and the substrate 10, and the second electrode 12 is disposed between the switch element 15 and the conductive pattern PT1.
  • the gap G1 between the conductive pattern PT1 and the first electrode 11 may be covered by the second electrode 12.
  • the conductive pattern PT2 is disposed between the fourth electrode 18 and the substrate 10.
  • the gap G3 between the conductive pattern PT2 and the third electrode 16 may be covered by the fourth electrode 18.
  • the modulation element 13 is disposed corresponding to the gap G2 between the first electrode 11 and the third electrode 16. For example, the modulation element 13 at least partially overlaps the gap G2 in the third direction D3.
  • the first conductive layer C1 and the second conductive layer C2 may each be a metal layer.
  • the electromagnetic wave transmitted below the first conductive layer C1 may be transmitted to the modulation element 13 from the region (e.g., the gap G2) that is not covered by the first conductive layer C1 or the second conductive layer C2, and output from the electronic device 1 after operation (e.g., adjustment of the phase, amplitude, transmission direction, or the like of the electromagnetic wave) of the modulation element 13.
  • the electronic device 1 may also include an isolation layer 19.
  • the first conductive layer C1 and the second conductive layer C2 may be separated from each other by the isolation layer 19.
  • the conductive pattern PT1 may be separated from the second electrode 12 and the switch element 15 by the isolation layer 19
  • the conductive pattern PT2 may be separated from the fourth electrode 18 by the isolation layer 19.
  • the isolation layer 19 may have an opening A1 and an opening A2.
  • the opening A1 and the opening A2 respectively expose the first electrode 11 and the third electrode 16.
  • the second electrode 12 is electrically connected to the first electrode 11 through the opening A1.
  • the fourth electrode 18 is electrically connected to the third electrode 16 through the opening A2.
  • the material of the isolation layer 19 may include, but is not limited to, silicon nitride (SiNx), silicon oxide (SiOx), epoxy resin, acrylic, solder resist, silicon materials, bismaleimide, polyimide, or a combination of the above.
  • the electronic device 1 may also include a passivation layer 20.
  • the passivation layer 20 covers the switch element 15, the second electrode 12, and the isolation layer 19.
  • the material of the passivation layer 20 may include, but is not limited to, silicon nitride, silicon oxide, epoxy resin, acrylic, solder resist, silicon materials, bismaleimide, polyimide, or a combination of the above.
  • the electronic device 1 may have a through hole TH1-1 and a through hole TH1-2.
  • the through hole TH1-1 may be located between the opening A1 and the through hole TH1-2, and the through hole TH1-1 penetrates the passivation layer 20 and the isolation layer 19 and exposes the first electrode 11.
  • the through hole TH1-2 may be located between the through hole TH1-1 and the opening A2, and the through hole TH1-2 penetrates the passivation layer 20 and the isolation layer 19 and exposes the third electrode 16.
  • the electronic device 1 may also include a connecting pad P3 and a connecting pad P4.
  • the connecting pad P3 is disposed in the through hole TH1-1 and on the first electrode 11.
  • the first solder 14 is also disposed in the through hole TH1-1 and may be electrically connected between the connecting pad P1 and the connecting pad P3.
  • the connecting pad P4 is disposed in the through hole TH1-2 and on the third electrode 16.
  • the second solder 17 is also disposed in the through hole TH1-2 and may be electrically connected between the connecting pad P2 and the connecting pad P4.
  • the connecting pad P1 of the modulation element 13 may be electrically connected to the switch element 15 sequentially through the first solder 14, the connecting pad P3, the first electrode 11, and the second electrode 12, for example.
  • the connecting pad P2 of the modulation element 13 may be electrically connected to ground sequentially through the second solder 17, the connecting pad P4, the third electrode 16, and the fourth electrode 18, for example.
  • the voltage (e.g., a DC voltage) received by the connecting pad P1 is different from a voltage (e.g., a ground voltage) received by the connecting pad P2.
  • the materials of the connecting pad P3 and the connecting pad P4 may include, but is not limited to, nickel gold, nickel palladium gold, silver, gold, nickel, tin, organic solderability preservative (OSP), other conductive materials, or a combination of the above.
  • the size of the connecting pad P3 and the connecting pad P4 may be 10 micrometers ⁇ 10 micrometers to 160 micrometers ⁇ 160 micrometers (10 ⁇ m ⁇ 10 ⁇ m ⁇ size ⁇ 160 ⁇ m ⁇ 160 ⁇ m). Nonetheless, the disclosure is not limited thereto.
  • the electronic device 1 may also include a protection layer 21.
  • the protection layer 21 is disposed on the passivation layer 20, and the protection layer 21 may cover the modulation element 13 and wrap the connecting pad P1, the connecting pad P2, the first solder 14, and the second solder 17. Nonetheless, the disclosure is not limited thereto.
  • the cross-sectional shape of the protection layer 21 may include a hemispherical shape, but is not limited thereto. It should be noted that the hemisphere is not limited to half of a sphere.
  • the material of the protection layer 21 may include, but is not limited to, epoxy resin, acrylic, solder resist, silicon materials, bismaleimide, polyimide, parylene, or a combination of the above.
  • FIG. 2A and FIG. 2B are respectively a schematic partial cross-sectional view and a schematic partial top view of an electronic device according to a second embodiment of the disclosure.
  • FIG. 2B omits illustration of some elements and/or film layers of the electronic device.
  • FIG. 2A for the cross-section of section line B-B' in FIG. 2B .
  • the electronic device 1A includes the substrate 10, the first electrode 11, the second electrode 12, the modulation element 13, the first solder 14, the switch element 15, the third electrode 16, the second solder 17, the fourth electrode 18, a dielectric film 19A, the passivation layer 20, the protection layer 21, a dielectric layer 22, the conductive pattern PT1, the conductive pattern PT2, the connecting pad P3, the connecting pad P4, a connecting pad P5, and a connecting pad P6.
  • the dielectric film 19A is configured to carry the second conductive layer C2 (including the second electrode 12 and the fourth electrode 18), the switch element 15, and the passivation layer 20.
  • the material of the dielectric film 19A may include, but is not limited to, epoxy resin, acrylic, solder resist, silicon materials, bismaleimide, polyimide, or a combination of the above.
  • a maximum thickness T19A of the dielectric film 19A in the third direction D3 is greater than or equal to 5 ⁇ m and less than or equal to 500 ⁇ m. Nonetheless, the disclosure is not limited thereto.
  • the dielectric film 19A may be attached to the first conductive layer C1 (including the first electrode 11, the third electrode 16, the conductive pattern PT1, and the conductive pattern PT2) through the dielectric layer 22.
  • the material of the dielectric layer 22 may include, for example but not limited to, epoxy resin, acrylic, solder resist, silicon materials, bismaleimide, polyimide, any adhesive material, or a combination of the above.
  • a maximum thickness T22 of the dielectric layer 22 in the third direction D3 may be greater than 1/10000 times the wavelength of the electromagnetic wave and less than 100 times the wavelength of the electromagnetic wave. In some embodiments, the maximum thickness T22 of the dielectric layer 22 in the third direction D3 is greater than or equal to 5 ⁇ m and less than or equal to 50 ⁇ m. Nonetheless, the disclosure is not limited thereto.
  • the dielectric layer 22 is disposed between the first conductive layer C1 and the dielectric film 19A, and the dielectric film 19A is disposed between the second conductive layer C2 and the dielectric layer 22.
  • the passivation layer 20 may have an opening A3 and an opening A4.
  • the opening A3 and the opening A4 respectively expose the second electrode 12 and the fourth electrode 18.
  • the connecting pad P5 and the connecting pad P6 are respectively disposed in an opening A5 and an opening A6.
  • the materials of the connecting pad P5 and the connecting pad P6 may include, but is not limited to, nickel gold, nickel palladium gold, silver, gold, nickel, tin, organic solderability preservative, other conductive materials, or a combination of the above.
  • the electronic device 1A may have a through hole TH1 and a through hole TH2.
  • the through hole TH1 penetrates the passivation layer 20, the dielectric film 19A, and the dielectric layer 22 and exposes the first electrode 11.
  • the through hole TH2 penetrates the passivation layer 20, the dielectric film 19A, and the dielectric layer 22 and exposes the third electrode 16.
  • the connecting pad P3 is disposed in the through hole TH1 and on the first electrode 11.
  • the connecting pad P4 is disposed in the through hole TH2 and on the third electrode 16.
  • the first solder 14 is disposed on the connecting pad P5, and the first solder 14 is connected to the connecting pad P3 disposed on the first electrode 11 through the through hole TH1.
  • the first solder 14 electrically connects the connecting pad P1, the connecting pad P3, and the connecting pad P5.
  • the first solder 14 may be in direct contact with the sidewall surface of the second electrode 12, so that the first electrode 11 may be electrically connected to the switch element 15 sequentially through the first solder 14 and the second electrode 12.
  • the first electrode 11 may be electrically connected to the switch element 15 sequentially through the connecting pad P3, the first solder 14, and the second electrode 12. Nonetheless, the disclosure is not limited thereto.
  • the second solder 17 is disposed on the connecting pad P6, and the second solder 17 is connected to the connecting pad P4 disposed on the third electrode 16 through the through hole TH2.
  • the second solder 17 electrically connects the connecting pad P2, the connecting pad P4, and the connecting pad P6.
  • the second solder 17 may be in direct contact with the sidewall surface of the fourth electrode 18, so that the third electrode 16 may be electrically connected to ground sequentially through the second solder 17 and the fourth electrode 18.
  • the third electrode 16 may be electrically connected to ground sequentially through the connecting pad P4, the second solder 17, and the fourth electrode 18. Nonetheless, the disclosure is not limited thereto.
  • Respectively disposing the switch element 15 and the first conductive layer C1 on different substrates (e.g., the substrate 10 and the dielectric film 19A) and then attaching the dielectric film 19A to the first conductive layer C1 through the dielectric layer 22 facilitate improving the warpage of the first conductive layer C1 caused by the mismatch between thermal expansion coefficients of the first conductive layer C1 and the substrate 10 during a high-temperature manufacturing process (e.g., the manufacturing of the switch element 15).
  • FIG. 3A and FIG. 3B are respectively a schematic partial cross-sectional view and a schematic partial top view of an electronic device according to a third embodiment of the disclosure.
  • FIG. 3B omits illustration of some elements and/or film layers of the electronic device.
  • FIG. 3A for the cross-section of section line C-C' in FIG. 3B .
  • the electronic device 1B includes the substrate 10, the first electrode 11, the second electrode 12, the modulation element 13, the first solder 14, the switch element 15, the third electrode 16, the second solder 17, the fourth electrode 18, the dielectric film 19A, the passivation layer 20, the protection layer 21, the dielectric layer 22, a third solder 23, a fourth solder 24, the conductive pattern PT1, the conductive pattern PT2, the connecting pad P3, the connecting pad P4, the connecting pad P5, the connecting pad P6, a connecting pad P7, and a connecting pad P8.
  • the electronic device 1B may have a through hole TH3 and a through hole TH4 in addition to the through hole TH1 and the through hole TH2.
  • the through hole TH3 penetrates the passivation layer 20, the dielectric film 19A, and the dielectric layer 22 and exposes the first electrode 11.
  • the through hole TH4 penetrates the passivation layer 20, the dielectric film 19A, and the dielectric layer 22 and exposes the third electrode 16.
  • the through hole TH4, the through hole TH2, the through hole TH1, and the through hole TH3 are arranged in the second direction D2, for example.
  • the through hole TH3 is located between the opening A3 and the through hole TH1, and the through hole TH4 is located between the opening A4 and the through hole TH2.
  • the connecting pad P7 is disposed in the through hole TH3 and on the first electrode 11.
  • the connecting pad P8 is disposed in the through hole TH4 and on the third electrode 16.
  • the materials of the connecting pad P7 and the connecting pad P8 may include, but is not limited to, nickel gold, nickel palladium gold, silver, gold, nickel, tin, organic solderability preservative, other conductive materials, or a combination of the above.
  • the first solder 14 electrically connects the connecting pad P1 and the connecting pad P3, and the first solder 14 is separated from the second electrode 12 and the connecting pad P5.
  • the third solder 23 is disposed on the connecting pad P5, and the third solder 23 is connected to the connecting pad P7 disposed on the first electrode 11 through the through hole TH3.
  • the third solder 23 may be in direct contact with the sidewall surface of the second electrode 12, so that the connecting pad P1 of the modulation element 13 may be electrically connected to the switch element 15 sequentially through the first solder 14 and the second electrode 12.
  • the connecting pad P1 may be electrically connected to the switch element 15 sequentially through the first solder 14, the connecting pad P3, the first electrode 11, the connecting pad P7, the third solder 23, and the second electrode 12.
  • the second solder 17 electrically connects the connecting pad P2 and the connecting pad P4, and the second solder 17 is separated from the fourth electrode 18 and the connecting pad P6.
  • the fourth solder 24 is disposed on the connecting pad P6, and the fourth solder 24 is connected to the connecting pad P8 disposed on the third electrode 16 through the through hole TH4.
  • the fourth solder 24 may be in direct contact with the sidewall surface of the fourth electrode 18, so that the connecting pad P2 of the modulation element 13 may be electrically connected to ground sequentially through the second solder 17 and the fourth electrode 18.
  • the connecting pad P2 may be electrically connected to ground sequentially through the second solder 17, the connecting pad P4, the third electrode 16, the connecting pad P8, the fourth solder 24, and the fourth electrode 18.
  • the third solder 23 and the fourth solder 24 may include, for example but not limited to, solder balls, copper pillars, other suitable metals, or metal alloys.
  • the protection layer 21 may further cover the third solder 23 and the fourth solder 24.
  • each solder is connected between two connecting pads can increase the process yield or facilitate an increase in the productivity capacity.
  • FIG. 4A and FIG. 4B are respectively a schematic partial cross-sectional view and a schematic partial top view of an electronic device according to a fourth embodiment of the disclosure.
  • FIG. 4B omits illustration of some elements and/or film layers of the electronic device.
  • FIG. 4A for the cross-section of section line D-D' in FIG. 4B .
  • the through hole TH1 and the through hole TH2 in FIG. 3A and FIG. 3B are replaced with a through hole TH5.
  • the through hole TH5 penetrates the passivation layer 20, the dielectric film 19A, and the dielectric layer 22 and exposes the first electrode 11, the third electrode 16, and the substrate 10 exposed by the first electrode 11 and the third electrode 16.
  • the modulation element 13 is disposed in the through hole TH5.
  • the connecting pad P1 of the modulation element 13 is bonded to the connecting pad P3 disposed on the first electrode 11 through the first solder 14, and the connecting pad P2 of the modulation element 13 is bonded to the connecting pad P4 disposed on the third electrode 16 through the second solder 17.
  • the modulation element 13 By forming a through hole (e.g., the through hole TH5) with a relatively large pore size, the modulation element 13 can be conveniently disposed or the adjustable range of the modulation element 13 can be increased.
  • a through hole e.g., the through hole TH5
  • FIG. 5A and FIG. 5B are respectively a schematic partial cross-sectional view and a schematic partial top view of an electronic device according to a fifth embodiment of the disclosure.
  • FIG. 5B omits illustration of some elements and/or film layers of the electronic device.
  • FIG. 5A for the cross-section of section line E-E' in FIG. 5B .
  • the main differences between an electronic device 1D and the electronic device 1A of FIG. 2A and FIG. 2B are described as follows.
  • a first conductive layer C1' does not include the conductive pattern PT1 and the conductive pattern PT2.
  • the electronic device 1D does not include the through hole TH1, the through hole TH2, the connecting pad P3, and the connecting pad P4.
  • the modulation element 13 is electrically coupled to the first electrode 11, and one connecting pad (e.g., the connecting pad P1) of the modulation element 13 is electrically connected to the switch element 15.
  • the first solder 14 is, for example, electrically connected to the connecting pad P1 and the connecting pad P5.
  • the connecting pad P1 of the modulation element 13 is electrically connected to the switch element 15 sequentially through the first solder 14, the connecting pad P5, and the second electrode 12, for example.
  • the modulation element 13 is also electrically coupled to the third electrode 16.
  • the third electrode 16 is electrically coupled to the connecting pad P2 of the modulation element 13.
  • the second solder 17 is, for example, electrically connected to the connecting pad P2 and the connecting pad P6.
  • the connecting pad P2 of the modulation element 13 is, for example, electrically connected to ground sequentially through the second solder 17, the connecting pad P6, and the fourth electrode 18.
  • the first conductive layer C1' and a second conductive layer C2' may each be a metal layer.
  • the electromagnetic wave transmitted below the first conductive layer C1' may be transmitted to the modulation element 13 sequentially through the gap G2 of the first conductive layer C1' and a gap G4 of the second conductive layer C2'.
  • the electromagnetic wave may be output from the electronic device 1D after operation (e.g., adjustment of the phase, amplitude, transmission direction, or the like of the electromagnetic wave) of the modulation element 13.
  • the size of the gap G2 may be smaller than, equal to, or larger than the gap G4, which is not particularly limited herein.
  • the design in which the first conductive layer C1' and the second conductive layer C2' are overlapped in the third direction D3 facilitates an increase in the adjustable capacitance.
  • FIG. 6A and FIG. 6B are respectively a schematic partial cross-sectional view and a schematic partial top view of an electronic device according to a sixth embodiment of the disclosure.
  • FIG. 6B omits illustration of some elements and/or film layers of the electronic device.
  • FIG. 6A for the cross-section of section line F-F' in FIG. 6B .
  • the electronic device 1E includes the through hole TH2 and the connecting pad P4.
  • the third electrode 16 is electrically connected to the connecting pad P2 of the modulation element 13.
  • the second solder 17 may be disposed on the connecting pad P6 and electrically connected between the connecting pad P2 and the connecting pad P4 through the through hole TH2.
  • the first solder 14 may be disposed on the connecting pad P5 and electrically connected between the connecting pad P1 and the connecting pad P3 through the through hole TH1 (see FIG. 2A ).
  • the second solder 17 may be electrically connected between the connecting pad P2 and the connecting pad P6 (see FIG. 5A ).
  • the third electrode 16 may be electrically connected to ground. Nonetheless, the disclosure is not limited thereto. In some other embodiments, the third electrode 16 may receive a first DC voltage, and the fourth electrode 18 may receive a second DC voltage. Nonetheless, the disclosure is not limited thereto. In some other embodiments, the manufacturing of the third electrode 16 may be omitted.
  • FIG. 7 to FIG. 9 are schematic partial cross-sectional views of manufacturing process flows of the electronic device according to the first embodiment of the disclosure.
  • the first conductive layer C1 is formed on the substrate 10.
  • the first conductive layer C1 is a patterned conductive layer and may include the first electrode 11, the third electrode 16, the conductive pattern PT1, and the conductive pattern PT2. Nonetheless, the disclosure is not limited thereto.
  • the isolation layer 19, the second conductive layer C2, the switch element 15, and the passivation layer 20 are sequentially formed on the substrate 10.
  • the second conductive layer C2 is a patterned conductive layer and may include the second electrode 12 and the fourth electrode 18. Nonetheless, the disclosure is not limited thereto.
  • the switch element 15 may be directly formed on the substrate 10 through a photolithography process to facilitate the manufacturing. In some other embodiments, the switch element 15 may be bonded onto the substrate 10 through conductive bumps (not shown) to reduce the manufacturing cost.
  • the through hole TH1-1 and the through hole TH1-2 penetrating the passivation layer 20 and the isolation layer 19 are formed.
  • the through hole TH1-1 and the through hole TH1-2 may be formed by, for example but not limited to, photolithography and etching.
  • the connecting pad P3 and the connecting pad P4 are formed in the through hole TH1-1 and the through hole TH1-2, respectively.
  • the connecting pad P3 and the connecting pad P4 may be formed by, for example but not limited to, chemical plating, immersion, electrolysis, or the like.
  • the first solder 14 and the second solder 17 are respectively formed on the connecting pad P3 and the connecting pad P4 by printing.
  • the connecting pad P1 and the connecting pad P2 of the modulation element 13 are respectively disposed on the first solder 14 and the second solder 17.
  • the connecting pad P1 and the connecting pad P2 of the modulation element 13 are fixed on the first solder 14 and the second solder 17 through solder reflow.
  • the protection layer 21 is formed. As such, the manufacturing of the electronic device 1 is preliminarily completed.
  • FIG. 10 to FIG. 13 are schematic partial cross-sectional views of manufacturing process flows of the electronic device according to the second embodiment of the disclosure.
  • the first conductive layer C1 and the dielectric layer 22 are sequentially formed on the substrate 10.
  • the dielectric film 19A, the second conductive layer C2 (including the second electrode 12 and the fourth electrode 18), and the passivation layer 20 are sequentially formed on a carrier CR.
  • the carrier board CR may include a rigid carrier board, such as a glass substrate. Nonetheless, the disclosure is not limited thereto.
  • the steps shown in FIG. 11 may be performed after the steps shown in FIG. 10 . In some other embodiments, the steps shown in FIG. 10 may be performed after the steps shown in FIG. 11 .
  • the carrier board CR is removed, and the dielectric film 19A is attached to the dielectric layer 22.
  • the carrier CR may be removed, for example, by laser lift-off, namely by irradiating a release layer (not shown) disposed between the carrier CR and the dielectric film 19A with laser to separate the carrier CR and the dielectric film 19A. Nonetheless, the disclosure is not limited thereto.
  • the through hole TH1 and the through hole TH2 penetrating the passivation layer 20, the dielectric film 19A, and the dielectric layer 22 are formed to expose the first electrode 11 and the third electrode 16.
  • the through hole TH1 and the through hole TH2 may be formed by, for example but not limited to, laser drilling. In other embodiments, at least one of the through hole TH1 and the through hole TH2 may also be formed by photolithography and etching, laser drilling, or a combination of the above.
  • a pore size R1 (e.g., a diameter) of the through hole TH1 and a pore size R2 (e.g., a diameter) of the through hole TH2 may be greater than or equal to 40 ⁇ m to facilitate subsequent formation of solders in the through hole TH1 and the through hole TH2. Nonetheless, the disclosure is not limited thereto.
  • the connecting pad P5, the connecting pad P3, the connecting pad P4, and the connecting pad P6 are respectively formed in the opening A3, the through hole TH1, the through hole TH2, and the opening A4.
  • the connecting pad P5, the connecting pad P3, the connecting pad P4, and the connecting pad P6 may be formed by, for example but not limited to, chemical plating, immersion, electrolysis, or the like.
  • the first solder 14 is formed on the connecting pad P3 and the connecting pad P5 and the second solder 17 is formed on the connecting pad P4 and the connecting pad P6 by printing or the like.
  • the connecting pad P1 and the connecting pad P2 of the modulation element 13 are respectively disposed on the first solder 14 and the second solder 17.
  • the connecting pad P1 and the connecting pad P2 of the modulation element 13 are fixed on the first solder 14 and the second solder 17 through solder reflow.
  • the protection layer 21 is formed. As such, the manufacturing of the electronic device 1A is preliminarily completed.
  • the manufacturing methods of the electronic device 1B to the electronic device 1E are generally similar to the manufacturing method of the electronic device 1A, and will thus not be described in detail below.
  • the electronic device 1A to the electronic device 1E may also be modified according to FIG. 1A , where the conductive layers, the switch element, the modulation element, the solders, the isolation layer, the passivation layer, the connecting pads, and the protection layer are disposed on the same substrate (e.g., the substrate 10).
  • the switch element and other elements/film layers are all disposed on the same side of the substrate, the disclosure is not limited thereto.
  • the switch element may also be disposed below the substrate, so that the switch element and other elements/film layers are respectively disposed on opposite sides of the substrate.
  • the switch element may be electrically connected to the second electrode through circuits (e.g., vias or other circuits) not shown.
  • FIG. 14 and FIG. 15 are respectively schematic partial cross-sectional views of an electronic device according to a seventh embodiment and an eighth embodiment of the disclosure.
  • FIG. 14 and FIG. 15 For the schematic partial top view of the electronic devices of FIG. 14 and FIG. 15 , reference may be made to FIG. 1B .
  • an electronic device 1F and the electronic device 1A of FIG. 2A are described as follows.
  • the dielectric film 19A is disposed on the substrate 10
  • a through hole TH6 that penetrates the dielectric film 19A and the dielectric layer 22 and exposes the first electrode 11 and the third electrode 16 is formed.
  • the second conductive layer C2 is formed on the substrate 10.
  • the second electrode 12 of the second conductive layer C2 is disposed on the dielectric film 19A, extends into the through hole TH6, and is in contact with the first electrode 11.
  • the fourth electrode 18 of the second conductive layer C2 is disposed on the dielectric film 19A, extends into the through hole TH6, and is in contact with the third electrode 16.
  • the switch element 15 and the passivation layer 20 are formed.
  • the connecting pad P3 and the connecting pad P4 are respectively formed in the opening A3 and the opening A4 of the passivation layer 20.
  • the connecting pad P1 and the connecting pad P2 of the modulation element 13 are fixed on the connecting pad P3 and the connecting pad P4 through the first solder 14 and the second solder 17.
  • the protection layer 21 is formed. As such, the manufacturing of the electronic device 1F is preliminarily completed.
  • the dielectric film 19A and the dielectric layer 22 at the gap G2 are removed when the through hole TH6 is formed. Accordingly, in the electronic device 1F, the dielectric film 19A and the dielectric layer 22 are not present below the modulation element 13.
  • the second electrode 12 is in contact with the first electrode 11, and the second electrode 12 is separated from the connecting pad P3 by the passivation layer 20; the fourth electrode 18 is in contact with the third electrode 16, and the fourth electrode 18 is separated from the connecting pad P4 by the passivation layer 20.
  • the opening A3 exposes part of the second electrode 12, and the connecting pad P3 is disposed on the first electrode 11 and covers the part of the second electrode 12 exposed by the opening A3.
  • the opening A4 exposes part of the fourth electrode 18, and the connecting pad P4 is disposed on the third electrode 16 and covers the part of the fourth electrode 18 exposed by the opening A4.
  • FIG. 16A to FIG. 16D are schematic partial views of manufacturing process flows of an electronic device according to a ninth embodiment of the disclosure, wherein FIGs. 16A and 16B are schematic partial top views, and FIGs. 16C and 16D are schematic partial cross-sectional views.
  • a plurality of switches SW are formed on a substrate SUB.
  • the substrate SUB may include, but is not limited to, a glass substrate, a polymer film, a printed circuit board, a base layer formed of ceramics, or a combination of the above.
  • the switches SW may include thin film transistors (TFTs).
  • the material of the channel layer (not shown) of the thin film transistor may include, but is not limited to, low-temperature polysilicon, amorphous silicon, oxide semiconductor, organic semiconductor, III-V compound semiconductor, or the like.
  • the plurality of switches SW may be arranged along the first direction D1 and the second direction D2.
  • a plurality of bonding pads P15 are formed on the plurality of switches SW.
  • the materials of the connecting pads P15' may include, but is not limited to, nickel gold, nickel palladium gold, silver, gold, nickel, tin, organic solderability preservative (OSP), other conductive materials, or a combination of the above.
  • OSP organic solderability preservative
  • a cutting process is performed on the substrate SUB to form a plurality of switch elements 15 (one switch element 15 is shown in FIG. 16C and FIG. 16D ) separated from each other.
  • a laser (not shown) is utilized to cut the substrate SUB along cutting lines (see dash lines in FIG. 16B ).
  • the switch element 15 and the modulation element 13 are then bonded to the substrate 10 through solders CT.
  • the bonding pads P15 of the switch element 15 are bonded to connecting pads P15' on the substrate 10 through solders CT.
  • the solders CT may include, for example but not limited to, a tin ball, a copper pillar, any other suitable metals, or a metal alloy.
  • the materials of the bonding pads P15 may include, but is not limited to, nickel gold, nickel palladium gold, silver, gold, nickel, tin, organic solderability preservative (OSP), other conductive materials, or a combination of the above. Please refer to the previous description for the method of bonding the modulation element 13 to the substrate 10, which will not be repeated here.
  • an electronic device 1H is formed after a protection layer 21 and a protection layer 21' are formed on the passivation layer 20.
  • the protection layer 21 may cover the modulation element 13 and wrap the connecting pad P1, the connecting pad P2, the first solder 14, and the second solder 17.
  • the protection layer 21' may cover the switch element 15 and wrap the connecting pads P15' and the solders CT.
  • the material of the protection layer 21' may include, but is not limited to, epoxy resin, acrylic, solder resist, silicon materials, bismaleimide, polyimide, parylene, or a combination of the above. Materials of the protection layer 21' and the protection layer 21 may be the same or different.
  • dielectric constant (Dk) and dissipation factor (Df) of the protection layer 21 may be lower than those of the protection layer 21', respectively.
  • the dissipation factor of the protection layer 21 may be less than 0.01, but is not limited thereto.
  • the equivalent capacitance in the radio frequency circuit can be controlled, so that the phase and the amplitude of the electromagnetic wave change correspondingly, thus controlling the direction of the electromagnetic wave or improving directivity of the radio frequency device.
  • the protection scope of the disclosure includes the above-mentioned process, machine, manufacturing, material composition, device, method, and step.
  • each claim forms an independent embodiment, and the protection scope of the disclosure also includes a combination of each of the claims and embodiments.
  • the protection scope of the disclosure should be subject to the appended claims.

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  • Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Micromachines (AREA)
EP22150111.7A 2021-01-06 2022-01-04 Dispositif électronique Pending EP4027458A1 (fr)

Applications Claiming Priority (3)

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US202163134186P 2021-01-06 2021-01-06
CN202111284065 2021-11-01
CN202111603375.3A CN114725071A (zh) 2021-01-06 2021-12-24 电子装置

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030003862A1 (en) * 2001-05-31 2003-01-02 Yoshitaka Yoshida Electronic component and mobile communication device using the electronic component
US20090153421A1 (en) * 2007-12-12 2009-06-18 Ahmadreza Rofougaran Method and system for an integrated antenna and antenna management
US20190295972A1 (en) * 2018-03-23 2019-09-26 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor packages and methods of forming same

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030003862A1 (en) * 2001-05-31 2003-01-02 Yoshitaka Yoshida Electronic component and mobile communication device using the electronic component
US20090153421A1 (en) * 2007-12-12 2009-06-18 Ahmadreza Rofougaran Method and system for an integrated antenna and antenna management
US20190295972A1 (en) * 2018-03-23 2019-09-26 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor packages and methods of forming same

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