EP3985657B1 - Anzeigevorrichtung - Google Patents

Anzeigevorrichtung Download PDF

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Publication number
EP3985657B1
EP3985657B1 EP19934878.0A EP19934878A EP3985657B1 EP 3985657 B1 EP3985657 B1 EP 3985657B1 EP 19934878 A EP19934878 A EP 19934878A EP 3985657 B1 EP3985657 B1 EP 3985657B1
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EP
European Patent Office
Prior art keywords
conversion circuit
circuit
core
connector
board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
EP19934878.0A
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English (en)
French (fr)
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EP3985657A1 (de
EP3985657A4 (de
Inventor
Yuan-Liang Wu
Yuyeh Chen
Lei Sun
Zihan Liu
Jun Shi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Xianyang Caihong Optoelectronics Technology Co Ltd
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Xianyang Caihong Optoelectronics Technology Co Ltd
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Priority claimed from PCT/CN2019/095757 external-priority patent/WO2020258392A1/zh
Application filed by Xianyang Caihong Optoelectronics Technology Co Ltd filed Critical Xianyang Caihong Optoelectronics Technology Co Ltd
Publication of EP3985657A1 publication Critical patent/EP3985657A1/de
Publication of EP3985657A4 publication Critical patent/EP3985657A4/de
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Publication of EP3985657B1 publication Critical patent/EP3985657B1/de
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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0271—Adjustment of the gradation levels within the range of the gradation scale, e.g. by redistribution or clipping
    • G09G2320/0276—Adjustment of the gradation levels within the range of the gradation scale, e.g. by redistribution or clipping for the purpose of adaptation to the characteristics of a display device, i.e. gamma correction
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/028—Generation of voltages supplied to electrode drivers in a matrix display other than LCD
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2370/00—Aspects of data communication
    • G09G2370/08—Details of image data interface between the display device controller and the data line driver circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2370/00—Aspects of data communication
    • G09G2370/14—Use of low voltage differential signaling [LVDS] for display data communication

Definitions

  • a flexible flat cable (FFC) is usually used to connect the system board and the horizontal direction circuit board for signal transmission between them.
  • FFC flexible flat cable
  • CN 107241562 A discloses a circuit system of an ultra-high definition liquid crystal television.
  • the circuit system includes a TCON driving module and a universal core panel, where the TCON driving module integrates a TCON driving portion, an upper screen interface and a U-P interface; and the universal core panel includes a master control SOC chip of the core, and integrates the U-P interface and a corresponding interface peripheral circuit.
  • the U-P interface is used for connecting the universal core panel and the TCON driving module.
  • US 2009/0284455 A1 discloses a liquid crystal display in which a system board and a timing control board can be used in common in a 60 Hz driving mode and a 120 Hz driving mode without being modified.
  • the liquid crystal display includes a system board for identifying a driving frequency of video data and supplying the video data and control signals at a first driving frequency or second driving frequency as a result of the identification, a timing control board equipped with a timing controller for processing the video data and control signals from the system board, the timing control board supplying the processed video data and control signals at the first or second driving frequency, and a liquid crystal panel for displaying an image based on the video data and control signals supplied from the timing control board.
  • CN 107396022 A discloses a data transmission device and a liquid crystal display device.
  • the data transmission device is used for transmitting signals for a liquid crystal display panel in the liquid crystal display device
  • the data transmission device includes a video processing board and a time series control board
  • the video processing board converts original configuration data into first configuration data according to a preset protocol, converts original video data into first video data according to a preset protocol and outputs the first configuration data and the first video data
  • the time series control board converts the first configuration data into the original configuration data according to the preset protocol, converts the first video data into the original video data according to the preset protocol, outputs the original configuration data after power-on and outputs a first signal when the original configuration data is not output
  • the first signal is used for enabling the liquid crystal display panel to display black pictures, where the original configuration data is used for configuring data when the liquid crystal display panel displays normally.
  • the invention provides a display device.
  • the invention is set out in the appended set of claims.
  • the display device of the embodiment disposes the driving circuit board assembly on the X-board, so that the X-board has some of TCON functions.
  • the system board also referred to as mainboard, shorted as MB
  • the horizontal direction circuit board XB
  • the display device of the embodiment stores the optical performance adjustment parameters in the nonvolatile memory of the X-board in the form of the parameter table, and debugging of each parameter in the optical performance adjustment parameter table is changed from the whole machine manufacturer to the panel manufacturer; because the optical performance adjustment parameters are strongly related to the panel, the optical performance adjustment parameter tables required for different panels are different, and the panel manufacturers know more about the optical characteristics of their own panels. Therefore, they can flexibly adjust the panel optical characteristics according to their own panel characteristics, which can liberate the whole machine manufacturers from the tedious work of adjusting optical characteristics, so as to accelerate the development speed of the whole machine.
  • a display device 10 provided by an embodiment of the invention includes: a display panel 111, a X-board 113, a system board 13 and a connecting part (also referred to as connecting member) CL1.
  • the display panel 111 is disposed with a gate driving circuit and a source driving circuit.
  • the X-board 113 is disposed with a driving circuit board assembly 1130.
  • the display device 10 is an active-matrix display device in the illustrated embodiment, for example, a TCONLESS liquid crystal television (LCD TV).
  • the display panel 111 includes a display area 1111, a gate driving circuit electrically connected to the display area 1111 and a source driving circuit electrically connected to the display area 1111.
  • the display area 1111 is disposed with a plurality of data lines DL, a plurality of gate lines GL and a plurality of pixels P respectively electrically connected to corresponding one of plurality of data lines DL and corresponding one of the plurality of gate lines GL.
  • Each of the plurality of pixels P is located at the intersection of the corresponding gate line GL and the corresponding data line DL.
  • the gate driving circuit includes, for example, two GOA (gate on array, gate driving circuit integrated on the array substrate) circuits 1113, which are located on the peripheral area of the display area 1111 and are divided on opposite sides of the display area 1111, that is, the gate driving circuit of the display panel 111 is a bilateral GOA circuit.
  • the GOA circuit 1113 is electrically connected to the gate lines GL in the display area 1111 to provide gate driving signals to each of the plurality of gate lines GL in the display area 1111.
  • the source driving circuit includes, for example, a plurality of chip-on-flex (COF) type source drivers 1115, such as twelve COF type source drivers 1115 shown in FIG. 1 .
  • COF chip-on-flex
  • the X-board 113 can be a whole independent circuit board or a plurality of circuit sub-boards juxtaposed with each other. If it is the plurality of circuit sub-boards juxtaposed with each other, the driving circuit board assembly 1130 can be disposed on one of the plurality of circuit sub-boards, and adjacent two circuit sub-boards of the plurality of circuit sub-boards form an electrical connection through another connecting part connected between connectors respectively disposed on the adjacent two circuit sub-boards.
  • the circuit sub-board 113a is electrically connected to the display area 1111 through a plurality of COF type source drivers 1115, for example, seven COF type source drivers 1115, and electrically connected to the GOA circuit 1113 on the right side of the display panel 111 using the rightmost COF type source driver 1115.
  • the circuit sub-board 113b is provided with a connector CN4.
  • the circuit sub-board 113b is electrically connected to the display area 1111 through a plurality of COF type source drivers 1115, for example, five COF type source drivers 1115, and electrically connected to the GOA circuit 1113 on the left side of the display panel 111 using the leftmost COF type source driver 1115.
  • the connecting part CL2 is, for example, a flexible circuit board or flexible flat cable (FFC), so that the signal generated from the circuit sub-board 113a is transmitted to the circuit sub-board 113b through the connecting part CL2.
  • FFC flexible circuit board or flexible flat cable
  • the display control circuit 1131 is electrically connected to the first connector CN1, the connector CN3 and a plurality of COF type source drivers 1115, for example, seven COF type source drivers 1115.
  • the display control circuit 1131 is not only electrically connected to the seven COF type source drivers 1115 on the right through a printed circuit board (PCB) of the circuit sub-board 113a, but also connected to the five COF type source drivers 1115 on the left through the connector CN3, the connecting part CL2, the connector CN4 and the PCB of the circuit sub-board 113b.
  • PCB printed circuit board
  • the X-board 113 is also provided with a plurality of mini low voltage differential signaling (Mini-LVDS) interfaces, which are arranged between the COF type source drivers 1115 and the display control circuit 1131, and the first connector includes a point-to-point (P2P) interface.
  • Min-LVDS mini low voltage differential signaling
  • P2P point-to-point
  • the display control circuit 1131 includes a signal conversion circuit 11312, which is electrically connected with the first connector CN1 and the Mini-LVDS interface, and is configured to receive a P2P interface signal containing image data through the first connector, generate source control signals and second interface type image data signals according to the P2P interface signal, and output the source control signals and the second interface type image data signals to the source driving circuit through the plurality of Mini-LVDS interfaces; the second interface type image data signals are Mini-LVDS interface signals.
  • a signal conversion circuit 11312 which is electrically connected with the first connector CN1 and the Mini-LVDS interface, and is configured to receive a P2P interface signal containing image data through the first connector, generate source control signals and second interface type image data signals according to the P2P interface signal, and output the source control signals and the second interface type image data signals to the source driving circuit through the plurality of Mini-LVDS interfaces; the second interface type image data signals are Mini-LVDS interface signals.
  • the interface of the source driver needs to be adjusted accordingly. For example, if the signal sent by the SOC is transmitted through the P2P interface, the corresponding source driver interface can only use the P2P interface, resulting in an increase in the overall manufacturing cost and test cost.
  • the connector CL1 transmits the signal from the SOC to the signal conversion circuit 11312 of the display control circuit 1131 through the P2P interface, the signal conversion circuit 11312 can convert the P2P interface signal into an interface signal corresponding to the panel source driver.
  • the interface of the COF type source driver 1115 is the Mini-LVDS interface
  • the P2P interface signal is correspondingly converted into the Mini-LVDS signal by the signal conversion circuit
  • the Mini-LVDS signal is sent to the interface of the COF type source driver 1115 of the panel, that is, the conversion of the interface signal is completed through the signal conversion circuit 11312, so as to complete the data transmission without changing the original Mini-LVDS interface on the panel, by adding the signal conversion circuit (for example, in the form of a chip) in the display control circuit of the driving circuit board assembly.
  • the signal conversion circuit 11312 can generate the timing control signals required by the display panel, the debugging and revision of the panel can be completed by the panel manufacturer, and the whole machine manufacturer can reduce the development cost without any change; on the other hand, new panel technology can be completed by the signal conversion circuit 11312, and the system board 13 does not need any change.
  • the display control circuit 1131 further includes a direct-current (DC) voltage conversion circuit 11314, a level conversion circuit 11316 and a Gamma correction circuit 11318.
  • the signal conversion circuit 11312 is electrically connected to the connector CN1, the level conversion circuit 11316 and the source driving circuit, and configured to receive reference timing signals such as STV and CKV and a P2P interface signal containing image data (the image data such as RGB data) through the first connector, generate source control signals such as TP and POL and second interface type image data signals such as Mini-LVDS according to the P2P interface signal, and output them to the source driving circuit, and generate initial gate control signals such as ST_in, CKx_in, LC_in and Reset_in according to the reference timing signals such as STV and CKV to the level conversion circuit 11316.
  • the DC voltage conversion circuit 11314 is electrically connected to the connector CN1 and configured to receive an input DC voltage such as Vin, and generate gate switching voltages such as VGH and VGL and a reference voltage such as VAA according to the input DC voltage such as Vin, and output the gate switching voltages and the reference voltage to the level conversion circuit 11316 and the Gamma correction circuit 11318 respectively.
  • the level conversion circuit 11316 is configured to generate gate control signals such as ST, CKx, LCx and Reset according to the gate switching voltages such as VGH and VGL and the initial gate control signal such as ST_in, CKx_in, LC_in, Reset_in to the gate driving circuit.
  • the Gamma correction circuit 11318 is configured to generate a plurality of Gamma voltages such as GMAx according to the reference voltage such as VAA to the source driving circuit.
  • CKx_in is, for example, four high-frequency clock signals CK1 ⁇ CK4, CKx is, for example, eight high-frequency clock signals CK1 ⁇ CK8, and LCx is two low-frequency clock signals LC1 ⁇ LC2 relative to CKx
  • GMAx is, for example, fourteen channel Gamma voltages such as GMA1 ⁇ GMA14
  • VGH is, for example, + 20V ⁇ + 30V as the gate on voltage
  • VGL is, for example, about - 5V as the gate off voltage, but this invention is not limited thereto.
  • the P2P interface signal includes multiple pairs of differential signals, which is another interface type different from the Mini-LVDS interface, and is very suitable for short-distance signal transmission from the system board 13 to the circuit sub-board 113a, which can be known mature USI-T, EPI, CMPI and ISP interface, etc.
  • the DC voltage conversion circuit 11314 is not limited to generating the above VGH, VGL and VAA, but is also used to provide power supply voltages such as digital voltage VDD and analog voltage HVAA (not shown in the figure) to the signal conversion circuit 11312, the level conversion circuit 11316, the Gamma correction circuit 11318, the gate driving circuit and the source driving circuit.
  • the Demura IP core 1331 is configured for performing Mura (i.e., a phenomenon of various traces caused by uneven display brightness) elimination (also referred to as Demura) operation according to the Demura parameter table 11331.
  • the white balance adjustment IP core 1332 is configured for performing white balance adjustment operation according to the white balance adjustment parameter table 11332.
  • the color shift compensation IP core 1333 is configured for performing color shift compensation operation according to the color shift compensation parameter table 11333 to make the display panel 111 achieve low color shift display quality.
  • the OverDrive IP core 1334 is configured for performing overvoltage driving (also referred to as OverDrive) operation according to the OverDrive parameter table 11334.
  • the units described as separate components may be or may not be physically separated, and the components illustrated as units may be or may not be physical units, that is, may be located in one place, or may be distributed to multiple network units. Some or all of the units may be selected according to actual needs to achieve the purposes of the solutions of the embodiments.
  • each functional unit in each embodiment of the invention may be integrated into one processing unit, or each unit may be physically separated, or two or more units may be integrated into one unit.
  • the above integrated unit can be implemented in a form of hardware or in a form of hardware with a software functional unit(s).
  • the above integrated unit implemented in the form of the software functional unit(s) can be stored in a computer readable storage medium.
  • the above software functional unit(s) is/are stored in a storage medium and include(s) several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to perform some of the steps of various embodiments of the invention.
  • a computer device which may be a personal computer, a server, or a network device, etc.
  • the foregoing storage medium may be a U-disk, a mobile hard disk, a read-only memory (ROM), a random-access memory (RAM), a magnetic disk, or an optical disk, which can store program codes.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Claims (8)

  1. Ein Anzeigegerät (10), umfassend:
    ein Anzeigefeld (111), das eine Gatter-Treiberschaltung und eine Quelle-Treiberschaltung umfasst;
    eine waagerechte Leiterplatte (X-Platte) (113), wobei eine Treiberschaltungsbaukomponente (1130) auf der X-Platte (113) angeordnet ist; wobei der Treiberschaltungsbaukomponente (1130) eine Anzeigesteuerschaltung (1131) und einen ersten Stecker (CN1) umfasst und der Anzeigesteuerschaltung (1131) mit der Gatter-Treiberschaltung, der Quelle-Treiberschaltung und dem ersten Stecker (CN1) verbunden ist, und ein nicht-flüchtiges Speichermedium (1133) auf der X-Platte (113) angeordnet ist und elektrisch mit dem ersten Stecker (CN1) verbunden ist;
    eine Systemplatte (13), wobei ein zweiter Stecker (CN2) und ein System-on-Chip (133) auf der Systemplatte (13) angeordnet sind und der System-on-Chip (133) mit dem zweiten Stecker (CN2) verbunden ist; und
    ein Verbindungsteil (CL1), das zwischen dem ersten Stecker (CN1) und dem zweiten Stecker (CN2) verbunden ist;
    wobei das Anzeigegerät (10) dadurch gekennzeichnet ist, dass
    der Anzeigesteuerschaltung (1131) eine Signalumwandlungsschaltung (11312), eine Gleichspannungs-Umsetzungsschaltung (11314) und eine Pegelumwandlungsschaltung (11316) umfasst; der Signalumwandlungsschaltung (11312) ist elektrisch mit dem ersten Stecker (CN1) und der Quelle-Treiberschaltung verbunden und der Pegelumwandlungsschaltung (11316) ist elektrisch mit der Gleichspannungs-Umsetzungsschaltung (11314) und der Gatter-Treiberschaltung verbunden;
    der Signalumwandlungsschaltung (11312) dazu bestimmt ist, ein Punkt-zu-Punkt (P2P)-Schnittstellen-Signal, das Bildinformationen enthält, über den ersten Stecker (CN1) zu empfangen und Quelle-Steuerungssignale und Mini-Low-Voltage-Differential-Signaling (Mini-LVDS)-Schnittstellen-Signale gemäß dem P2P-Schnittstellen-Signal zu erzeugen und der Quelle-Steuerungssignale und der Mini-LVDS-Schnittstellen-Signale an der Quelle-Treiberschaltung auszugeben;
    der Pegelumwandlungsschaltung (11316) dazu bestimmt ist, Gatter-Steuerungssignale gemäß Gatter-Schaltspannungen, der von der Gleichspannungs-Umsetzungsschaltung (11314) erzeugt werden, und Referenztakt-Signale zu erzeugen und der Gatter-Steuerungssignale an der Gatter-Treiberschaltung auszugeben;
    der nicht-flüchtiges Speichermedium (1133) eine Optik-Leistungs-Anpassungs-Parameter-Tabelle (11330) speichert; und der Systemplatte (13) einen Optik-Leistungs-Anpassungs-IP-Kern (1330) umfasst;
    der System-on-Chip (133) dazu bestimmt ist, der Optik-Leistungs-Anpassungs-Parameter-Tabelle (11330), der im nicht-flüchtiges Speichermedium (1133) gespeichert ist, über den zweiten Stecker (CN2), das Verbindungsteil (CL1) und den ersten Stecker (CN1) zu lesen und der Optik-Leistungs-Anpassungs-Parameter-Tabelle (11330) in den Optik-Leistungs-Anpassungs-IP-Kern (1330) zu laden; und
    der Optik-Leistungs-Anpassungs-IP-Kern (1330) einen oder mehrere aus der Gruppe bestehend aus einem Demura-IP-Kern (1331), einem Weißabgleich-Anpassungs-IP-Kern (1332), einem Farbversatz-Kompensations-IP-Kern (1333), einem OverDrive-IP-Kern (1334) und einem Rundung-Bearbeitungs-IP-Kern (1335) umfasst; und der Optik-Leistungs-Anpassungs-Parameter-Tabelle (11330) entsprechend einen oder mehrere aus der Gruppe bestehend aus einer Demura-Parameter-Tabelle (11331), einer Weißabgleich-Anpassungs-Parameter-Tabelle (11332), einer Farbversatz-Kompensations-Parameter-Tabelle (11333), einer OverDrive-Parameter-Tabelle (11334) und einer Rundung-Bearbeitungs-Parameter-Tabelle (11335) umfasst.
  2. Der Anzeigegerät (10) nach Anspruch 1, wobei der X-Platte (113) mindestens zwei nebeneinander angeordnete Schaltkreis-Teilplatten umfasst, der Treiberschaltungsbaukomponente (1130) auf einer der mindestens zwei Schaltkreis-Teilplatten angeordnet ist und angrenzende zwei Schaltkreis-Teilplatten (113a, 113b) der mindestens zwei Schaltkreis-Teilplatten eine elektrische Verbindung durch ein weiteres Verbindungsteil (CL2) bilden, das zwischen den jeweils auf den angrenzenden zwei Schaltkreis-Teilplatten (113a, 113b) angeordneten Steckern (CN3, CN4) verbunden ist.
  3. Der Anzeigegerät (10) nach Anspruch 1, wobei eine Vielzahl von Mini-LVDS-Schnittstellen auf der X-Platte (113) angeordnet sind und der erste Stecker (CN1) ein P2P-Schnittstellen enthält.
  4. Der Anzeigegerät (10) nach Anspruch 3, wobei der Gleichspannungs-Umsetzungsschaltung (11314) elektrisch mit dem ersten Stecker (CN1) verbunden ist und dazu bestimmt ist, eine Eingangs-Gleichspannung über den ersten Stecker (CN1) zu empfangen, der Gatter-Schaltspannungen gemäß der Eingangs-Gleichspannung zu erzeugen und der Gatter-Schaltspannungen an der Pegelumwandlungsschaltung (11316) auszugeben.
  5. Der Anzeigegerät (10) nach Anspruch 4, wobei der Art der Integration der Gleichspannungs-Umsetzungsschaltung (11314), der Pegelumwandlungsschaltung (11316) und der Signalumwandlungsschaltung (11312) eine der folgenden ist:
    der Gleichspannungs-Umsetzungsschaltung (11314), der Pegelumwandlungsschaltung (11316) und der Signalumwandlungsschaltung (11312) werden in dieselbe Chip integriert;
    der Gleichspannungs-Umsetzungsschaltung (11314) und der Pegelumwandlungsschaltung (11316) werden in dieselbe Chip integriert und der Signalumwandlungsschaltung (11312) wird in einen anderen Chip integriert;
    der Gleichspannungs-Umsetzungsschaltung (11314) und der Signalumwandlungsschaltung (11312) werden in dieselbe Chip integriert und der Pegelumwandlungsschaltung (11316) wird in einen anderen Chip integriert;
    der Pegelumwandlungsschaltung (11316) und der Signalumwandlungsschaltung (11312) werden in dieselbe Chip integriert und der Gleichspannungs-Umsetzungsschaltung (11314) wird in einen anderen Chip integriert; und
    der Gleichspannungs-Umsetzungsschaltung (11314), der Pegelumwandlungsschaltung (11316) und der Signalumwandlungsschaltung (11312) werden jeweils in unterschiedliche Chips integriert.
  6. Der Anzeigegerät (10) nach Anspruch 3, wobei der Anzeigesteuerschaltung (1131) ferner eine Gamma-Korrekturschaltung (11318) umfasst; wobei der Gleichspannungs-Umsetzungsschaltung (11314) elektrisch mit dem ersten Stecker (CN1) verbunden ist und dazu bestimmt ist, eine Eingangs-Gleichspannung über den ersten Stecker (CN1) zu empfangen, der Gatter-Schaltspannungen und eine Referenzspannung gemäß der Eingangs-Gleichspannung zu erzeugen und derGatter-Schaltspannungen und der Referenzspannung jeweils an der Pegelumwandlungsschaltung (11316) und der Gamma-Korrekturschaltung (11318) auszugeben;
    wobei der Gamma-Korrekturschaltung (11318) dazu bestimmt ist, eine Vielzahl von Gamma-Spannungen gemäß der Referenzspannung zu erzeugen und der Vielzahl von Gamma-Spannungen an der Quelle-Treiberschaltung auszugeben.
  7. Der Anzeigegerät (10) nach Anspruch 1, wobei der Signalumwandlungsschaltung (11312) ferner dazu bestimmt ist, der Referenztakt-Signale über den ersten Stecker (CN1) zu empfangen, anfängliche Gatter-Steuerungssignale gemäß der Referenztakt-Signale zu erzeugen und der anfänglichen Gatter-Steuerungssignale an der Pegelumwandlungsschaltung (11316) auszugeben; und der Pegelumwandlungsschaltung (11316) speziell dazu bestimmt ist, der Gatter-Steuerungssignale gemäß der Gatter-Schaltspannungen und dem anfänglichen Gatter-Steuerungssignal zu erzeugen und der Gatter-Steuerungssignale an der Gatter-Treiberschaltung auszugeben.
  8. Der Anzeigegerät (10) nach Anspruch 1, wobei der Optik-Leistungs-Anpassungs-IP-Kern (1330) den Demura-IP-Kern (1331), den Weißabgleich-Anpassungs-IP-Kern (1332), den Farbversatz-Kompensations-IP-Kern (1333), den OverDrive-IP-Kern (1334) und den Rundung-Bearbeitungs-IP-Kern (1335) umfasst; und
    der System-on-Chip (133) dazu bestimmt ist, den Demura-IP-Kern (1331), den Weißabgleich-Anpassungs-IP-Kern (1332), den Farbversatz-Kompensations-IP-Kern (1333), den OverDrive-IP-Kern (1334) und den Rundung-Bearbeitungs-IP-Kern (1335) nacheinander zu steuern, um eine Demura-Operation, einen Weißabgleich, eine Farbversatz-Kompensation, eine OverDrive-Operation und eine Rundung-Bearbeitung gemäß der Demura-Parameter-Tabelle (11331), der Weißabgleich-Anpassungs-Parameter-Tabelle (11332), der Farbversatz-Kompensations-Parameter-Tabelle (11333), der OverDrive-Parameter-Tabelle (11334) und der Rundung-Bearbeitungs-Parameter-Tabelle (11335) jeweils durchzuführen.
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