EP3955112A1 - Procédé et appareil de détection d'erreurs de mémoire - Google Patents

Procédé et appareil de détection d'erreurs de mémoire Download PDF

Info

Publication number
EP3955112A1
EP3955112A1 EP21174358.8A EP21174358A EP3955112A1 EP 3955112 A1 EP3955112 A1 EP 3955112A1 EP 21174358 A EP21174358 A EP 21174358A EP 3955112 A1 EP3955112 A1 EP 3955112A1
Authority
EP
European Patent Office
Prior art keywords
data
shared memory
processing domain
diagnostic code
memory resource
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
EP21174358.8A
Other languages
German (de)
English (en)
Inventor
Anthony G. Gibart
Joseph P. Izzo
Jonathan R. Engdahl
Benjamin H. Nave
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Rockwell Automation Technologies Inc
Original Assignee
Rockwell Automation Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rockwell Automation Technologies Inc filed Critical Rockwell Automation Technologies Inc
Publication of EP3955112A1 publication Critical patent/EP3955112A1/fr
Pending legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1004—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's to protect a block of data words, e.g. CRC or checksum

Definitions

  • the subject matter disclosed herein relates to detecting a memory error in a system with multiple processing domains, and, more specifically, to an industrial controller configured to meet safety integrity level three (SIL-3) functional safety with a single processor chip.
  • SIL-3 safety integrity level three
  • Industrial controllers are special-purpose computers used in controlling industrial processes. Under the direction of a stored control program, an industrial controller examines a series of inputs reflecting the status of the controlled process and changes a series of outputs controlling the process.
  • the inputs and outputs may be binary, that is, on or off, or analog, providing a value within a substantially continuous range.
  • the inputs may be obtained from sensors attached to the controlled process, and the outputs may be signals to actuators on the controlled process.
  • Safety industrial control systems are industrial control systems intended to ensure the safety of humans working in the environment of an industrial process. Such systems may include the electronics associated with emergency-stop buttons, light curtains, and other machine lockouts. Safety industrial control systems are not optimized for "availability", that is being able to function for long periods of time without error, but rather for "safety” which is being able to accurately detect an operating condition requiring a shut down. Safety industrial controllers normally provide a predetermined safe state for their outputs upon a safety shutdown, the predetermined values of these outputs being intended to put the industrial process into its safest static mode.
  • Safety industrial control systems may be associated with a "safety integrity level” (SIL) indicating a given amount of risk reduction.
  • SIL safety integrity level
  • Standard IEC EN 61508 defines four SIL levels of SIL-1 to SIL-4 with higher numbers representing higher amounts of risk reduction.
  • SIL-3 functional safety high diagnostic coverage of critical components is required such that a failure of a critical component does not go undetected.
  • a common method for providing the required diagnostic coverage is to provide redundant components.
  • Each component is configured to generate an identical signal, execute identical processing steps, or the like. While one of the components may be selected as an active component and may be configured to interface with the controlled machine or process, both the active component and a backup component operate in tandem and operation of the components may be compared to each other. A comparison of signals generated or processing steps executed should return identical results if both components are operating normally. A difference between the operation of the two components indicates failure of one of the components and the system may take the necessary steps to enter a safe operating state.
  • a method for detecting a memory error includes writing data to a memory address in a shared memory resource from a first processing domain, generating a diagnostic code with the first processing domain as a function of the data and of the memory address, and appending the diagnostic code to the data such that the diagnostic code is written in the shared memory resource with the corresponding data.
  • the data and the diagnostic code are read from the shared memory resource back to the first processing domain, and the first processing domain verifies that the data read from the shared memory resource matches the data written to the shared memory resource.
  • an apparatus for detecting a memory error includes a shared memory resource configured to store data, a memory controller, a first processing domain, and a second processing domain.
  • the memory controller is configured to manage reading the data from and writing the data to the shared memory resource.
  • the first processing domain is in communication with the memory controller and is configured to write the data to the shared memory resource via the memory controller, generate a first diagnostic code corresponding to the first processing domain, the data to be written, and to a memory address at which the data is to be written, and append the first diagnostic code to the data as it is written to the shared memory resource.
  • the second processing domain is in communication with the memory controller and is configured to write the data to the shared memory resource via the memory controller, generate a second diagnostic code corresponding to the second processing domain, the data to be written, and to a memory address at which the data is to be written, and append the second diagnostic code to the data as it is written to the shared memory resource.
  • Either the first or the second processing domain is further configured to read the data from the shared memory resource via the memory controller, and verify that the data read from the shared memory resource matches the data written to the shared memory resource.
  • a method for detecting a memory error writes data to a memory address in a shared memory resource via a shared memory controller from either a first processing domain or a second processing domain and appends a diagnostic code to the data as the data is written by either the first processing domain or the second processing domain.
  • the diagnostic code is generated as a function of the data, the memory address, and the corresponding processing domain from which it is written.
  • the data is read from the memory address in the shared memory resource with the corresponding processing domain that wrote the data to the memory address, and the data read from the memory address in the shared memory resource is verified that it matches the data written to the memory address using the diagnostic code appended to the data.
  • the subject matter disclosed herein discloses an improved system for managing memory usage for multiple processing domains. More specifically, an improved method and apparatus is described for detecting a memory error in a system with multiple processing domains on a single integrated circuit die, where each of the processing domains utilizes a shared memory resource accessed via a shared memory controller. Each processing domain issues read and write commands to the shared memory controller for storing data in and reading data from the shared memory resource. As data is written to the shared memory resource, the processing domain generates a diagnostic code that may be used when reading the data back from the shared memory resource to verify that the data read is the same as the data that was written.
  • the diagnostic code is generated as a function of the data being written, the memory address to which the data is being written, and of a unique identifier corresponding to the processing domain which is writing the data.
  • a checksum such as a cyclic redundancy check (CRC)
  • CRC checksum is generated by an algorithm which receives data to be stored as an input and passes the data through a function, such as a polynomial function which outputs a unique signature based on the data received and on the function generating the signature.
  • each processing domain may utilize a unique polynomial or other processing algorithm by which the checksum is generated.
  • the resulting diagnostic code is a function of the processing domain which generated the code. The diagnostic code is stored with the data in the shared memory for verification when the data is read back from the shared memory resource.
  • the processing domain When the data is read back from the shared memory resource, the processing domain separates the diagnostic code and the data being read.
  • the processing domain generates another diagnostic code as a function of the data being read, the memory address from which the data is being read, and of the unique identifier corresponding to the processing domain which is reading the data. Inclusion of the memory address in generation of the diagnostic code allows the processing domain to check, for example, whether another set of data was erroneously written by the memory controller to that address. Because the diagnostic code includes the memory address, data that should have been written to a different address will include a diagnostic code that was generated as a function of the different address.
  • the diagnostic code Even if identical data intended for a different memory location is written to a particular address, the diagnostic code will correspond to the different memory address and the error made by the memory controller in writing data to an incorrect memory location will be detected when reading the data.
  • including a unique identifier and/or using a unique algorithm by which the diagnostic code is generated within each processing domain ensures that only the domain that wrote the data to the shared memory resource will be able to read the data from the memory resource.
  • the other diagnostic code is generated in an identical manner to the initial diagnostic code as the data is read from the shared memory resource. The other diagnostic code is then compared to the initial diagnostic code. If both diagnostic codes are the same, the processing domain can be confident that the data read from the shared memory resource is the same as the data that was originally written.
  • the microprocessor 10 includes a first processing domain 100 and a second processing domain 200.
  • the first processing domain 100 includes a first processor core 105
  • the second processing domain 200 includes a second processor core 205.
  • the microprocessor 10 is shown with two cores 105, 205 and two processing domains 100, 200, this is for ease of illustration and is not intended to be limiting. It is contemplated that the microprocessor 10 may include more than two cores and processing domains.
  • Each processing domain 100, 200 further includes a local cache memory 110, 210.
  • the first processor core 105 can read from and write to the first cache 110
  • the second processor core 205 can read from and write to the second cache 210.
  • Each processing domain 100, 200 is also in communication with a shared memory resource 30 via a common memory controller 20. Although illustrated as a single block, it is contemplated that the shared memory resource 30 may be a single memory chip or multiple memory chips each in communication with the memory controller 20.
  • the first processing domain 100 includes a first write channel 115 receiving data from the first processing core 105.
  • the first write channel 115 is in communication with a first diagnostic circuit 120 to generate a diagnostic code corresponding to data being written to the shared memory resource 30.
  • the first processing domain 100 also includes a first read channel 125 receiving data from the memory controller 20.
  • the first read channel 125 is also in communication with the first diagnostic circuit 120 to generate a diagnostic code corresponding to data being read from the shared memory resource 30.
  • a first compare circuit 130 is in communication with both the first read channel 125 and the first diagnostic circuit 120 to compare the diagnostic code generated when writing the data to the diagnostic code generated when reading the data.
  • the second processing domain 200 includes a second write channel 215 receiving data from the second processing core 205. The second write channel 215 is in communication with a second diagnostic circuit 220 to generate a diagnostic code corresponding to data being written to the shared memory resource 30.
  • the second processing domain 200 also includes a second read channel 225 receiving data from the memory controller 20. The second read channel 225 is also in communication with the second diagnostic circuit 220 to generate a diagnostic code corresponding to data being read from the shared memory resource 30.
  • a second compare circuit 230 is in communication with both the second read channel 225 and the second diagnostic circuit 220 to compare the diagnostic code generated when writing the data to the diagnostic code generated when reading the data.
  • circuits may be combined in whole or in part with other circuits.
  • the diagnostic circuit 120, 220 and the compare circuit 130, 230 may be formed as a single circuit.
  • the separate circuits are utilized for ease of illustration and for ease of discussion of various functions performed during a read or write between the processor 10 and the shared memory resource 30.
  • each channel 115, 125, 215, 225 is illustrated as a separate communication channel.
  • the separate channels are illustrated for ease of illustration and discussion of the communication along each channel. It is contemplated that a single communication bus may be provided for each processing domain 100, 200 where a single processing bus includes both the respective read and write channel for the corresponding processing domain.
  • each processor core 105, 205 may be implemented on a separate processor rather than as a multi-core processor, where each of the separate processors writes to the shared memory controller 20 and shared memory 30.
  • each processing domain 100, 200 is able to detect memory errors related to data written to the shared memory resource 30 by the respective processing domain.
  • the process will be discussed with respect to the first processing domain 100. This is not intended to be limiting and it is understood that the second processing domain 200 or still additional processing domains may be configured to execute the same steps to detect a memory error for data written to the shared memory resource 30 by the corresponding processing domain.
  • Fig. 3 steps for writing data to the shared memory resource 30 are illustrated.
  • the data and address are prepared by the processing core 105 for writing to the shared memory resource 30.
  • an exemplary data packet 50 is illustrated which includes a header 52, data 54 to be written, and a diagnostic code 56.
  • the address 53 at which the data 54 is to be written is included in the header information.
  • This data packet 50 is intended to be exemplary only and not limiting. It is contemplated that the header 52 may include only an address 53 at which the data 54 is to be written.
  • the header may also include, for example, a source, indicating to the memory controller 20 from which processing domain 100 the data is being sent, or other control commands and or status flags to manage the read and write process between each processing domain 100 and the shared memory resource.
  • a source indicating to the memory controller 20 from which processing domain 100 the data is being sent, or other control commands and or status flags to manage the read and write process between each processing domain 100 and the shared memory resource.
  • an address bus separate from a data bus, may be provided between each processing domain 100 and the memory controller 20, where the address 53 at which the data 54 is to be written within the shared memory resource 30 is provided on the address bus by the processor core 105 and the data 54 is provided on the data bus by the processor core 105.
  • the processing domain 100 next generates a diagnostic code 56 for the data to be written to the shared memory resource 30, as shown in step 304.
  • the diagnostic circuit 120 receives the data 54 and address 53 at which the data is to be written. These may be provided in a single data packet 50 or via separate buses within the processing domain 100.
  • the diagnostic circuit 120 is then configured to generate a diagnostic code as a function of the data 54 and of the address 53 at which the data is to be written.
  • the data 54 may include, for example, between sixteen and one hundred twenty-eight (16-128) bits.
  • the address may similarly be defined by a sixteen to one hundred twenty-eight (16-128) bit memory location.
  • the length of the data 54 and the length of the address 53 are defined by the shared memory resource 30 and/or the memory controller 20 used to transfer the data 54 between the processing domain 100 and the shared memory resource.
  • the data 54 and address 53 are provided to the diagnostic circuit and passed through a suitable algorithm to generate the diagnostic code 56.
  • the diagnostic code may be generated via a hash algorithm, where the hash algorithm is configured to map a set of data values to a set of code values with a high probability that a change in the data values will result in a change in the code generated.
  • the diagnostic code 56 may be a CRC checksum, and the algorithm may be any suitable algorithm to generate the CRC checksum.
  • the diagnostic code 56 may be generated by an Error Correcting Code (ECC) or a Secure Hash Algorithm (SHA).
  • ECC Error Correcting Code
  • SHA Secure Hash Algorithm
  • a unique identifier for each processing domain 100 may be included with the data 54 and the address 53 to further identify the data 54 as having been written to the shared memory resource 30 by a particular processing domain 100.
  • one bit of the address 53 or of the data 54 to be stored to the shared memory resource 30 may be used to define the unique identifier. If there are only two processing domains, as illustrated in Fig. 1 , the highest address bit may be used to define a particular processing domain.
  • the first processing domain 100 may be assigned zero (0) as an identifier, and the second processing domain 200 may be assigned one (1) as an identifier.
  • the processing core 105 may write an address to the lower thirty-one (31) bits.
  • the upper bit may be tied to a logical zero for the first processing domain 100 and to a logical one for the second processing domain 200 such that the address is always defined as a function of the processing domain.
  • each processing core 105 may be configured to set the upper bit to the respective identifier as it writes the remaining bits of the address.
  • two bits may be reserved for unique identifiers if there are four processing domains and so on for a greater number of processing domains.
  • a separate data byte may be defined in which up to two hundred fifty-five unique codes may be defined for separate processing domains.
  • the source of the data 54 may be included in the header 52 and may serve as the unique identifier.
  • the separate data byte may be passed to the algorithm generating the diagnostic code in tandem with the data 54 and the address 53, such that the CRC is determined as a function of the unique identifier, the data, and the address at which the data is to be written.
  • the unique identifier may be a unique algorithm selected for each processing domain 100.
  • a different diagnostic code 56 or checksum, would be generated for the processing domain according to the selected algorithm.
  • identical data being written to the same address would still generate a different diagnostic code 56 for each processing domain 100.
  • the processing domain 100 could verify that data read back from the shared memory resource 30 was, in fact, written by that processing domain, as will be discussed in more detail below.
  • the diagnostic code 56 is written to the shared memory resource 30 along with the data 54 at the desired address 53, as shown in step 306.
  • the diagnostic circuit 120 appends the diagnostic code 56 to the data 54 and transmits both the data 54 and the diagnostic code 56 to the memory controller 20 via a data bus.
  • the address 53 may be passed to the memory controller 20 either directly from the processing core 105 or via the diagnostic circuit 120 on an address bus.
  • the address 53 is passed first to the diagnostic circuit 120, for example, in a header 52, and the data packet 50 is passed as a single object from the diagnostic circuit 120 to the memory controller 20.
  • the memory controller 20 manages storing the data 54 and the diagnostic code 56 in the shared memory resource 30.
  • the processing domain 100 issues a read request to the memory controller 20.
  • the read request identifies a memory address 53 from which the processing domain 100 wishes to read data 54.
  • the memory controller 20 manages the data access with the shared memory resource 30 and provides the requested data 54 from the shared memory resource 30.
  • the diagnostic code 56 corresponding to the data 54 is also read.
  • the data 54 and diagnostic code 56 are stored in consecutive bytes of memory and, therefore, a read of the shared memory resource 30 defines the desired address 53 and requests a length of data to be read that is sufficient to return both the data 54 and the diagnostic code 56 which was previously stored with the data 54.
  • the processing domain 100 performs a check on the data read back from the shared memory resource 30 to verify that it corresponds to the data originally written.
  • the read channel 125 is configured to split the data 54 and the diagnostic code 56 from each other for separate processing.
  • the read channel 125 may, for example, connect the portion of the data bus on which the data 54 is transmitted to the diagnostic circuit 120 and the portion of the data bus on which the diagnostic code 56 is transmitted to a compare circuit 130.
  • step 404 another diagnostic code is generated during the read process.
  • the diagnostic circuit 120 utilizes the same algorithm used during the write process to generate the new diagnostic code.
  • the diagnostic circuit 120 receives the data 54 read from the shared memory resource 30 by the memory controller 20.
  • the diagnostic circuit 120 may also receive the desired memory address 53 from which the data 54 was read directly from the processing core 105. The same address may be passed both to the diagnostic circuit 120 and to the memory controller 20 during the read request to avoid potential errors in the address being introduced while reading the data.
  • the diagnostic circuit 120 is also aware of the unique identifier corresponding to the processing domain 100. Whether the unique identifier is part of the memory address, a separate bit or byte embedded within the data, or a unique algorithm used to generate the diagnostic code, the diagnostic circuit 120 utilizes the unique identifier to generate the diagnostic code in an identical manner during the read process as it does during the write process. As a result, the two diagnostic codes should be identical.
  • the diagnostic circuit 120 After generating the second diagnostic code during the read process, the diagnostic circuit 120 passes the second diagnostic code to the compare circuit 130. As shown in step 406, the compare circuit 130 is configured to determine whether the original diagnostic code, obtained from the shared memory resource 30 is the same as the new diagnostic code generated during the read process. If the two diagnostic codes match, the data 54 which was read from the shared memory resource 30 is verified as matching the data which was originally written and, as shown in step 408, the data is then passed to the processing core 105 for subsequent use by the application or control program which originally initiated the read request. If, however, the two diagnostic codes do not match, the compare circuit 130 generates an error, as shown in step 410 and the processor core 105 takes action based on receiving an error message rather than upon receiving the requested data.
  • the two diagnostic codes do not match, this could be an indication of an error occurring at a number of different steps between the microprocessor 10 and the shared memory resource 30. For example, an error may occur in the data being written to or read from the shared memory resource. If the data does not match between a write and a read, different diagnostic codes will be generated. Because two processing domains 100, 200 are sharing a single memory controller, the potential exists for an error in an address line during a write resulting in one processing domain 100 overwriting a memory address reserved for the other processing domain 200. However, when the second processing domain 200 attempts to read data from that address, the diagnostic code which was saved with the data was generated as a function of a different address.
  • the second processing domain 200 when the data is read back, the second processing domain 200 generates a different diagnostic code, using the address at which the first processing domain erroneously wrote to rather than the address at which the data was intended to be stored.
  • the second processing domain is aware that the data stored in that memory location is not the same data as was previously written to that address by the second processing domain.
  • the processing domain 100 that detected the error may notify the other processing domain 200 of the error. It is contemplated that a separate communication bus or dedicated signal lines may exist between the two processing domains 100, 200 by which such an error notification may be transmitted.

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Security & Cryptography (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
EP21174358.8A 2020-08-14 2021-05-18 Procédé et appareil de détection d'erreurs de mémoire Pending EP3955112A1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US16/993,986 US11249839B1 (en) 2020-08-14 2020-08-14 Method and apparatus for memory error detection

Publications (1)

Publication Number Publication Date
EP3955112A1 true EP3955112A1 (fr) 2022-02-16

Family

ID=76011697

Family Applications (1)

Application Number Title Priority Date Filing Date
EP21174358.8A Pending EP3955112A1 (fr) 2020-08-14 2021-05-18 Procédé et appareil de détection d'erreurs de mémoire

Country Status (2)

Country Link
US (1) US11249839B1 (fr)
EP (1) EP3955112A1 (fr)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20220081730A (ko) * 2020-12-09 2022-06-16 현대자동차주식회사 차량용 제어기의 가상 고장코드 판단 방법 및 장치

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030131197A1 (en) * 2002-01-07 2003-07-10 Morrison John M. Shared cache for data integrity operations
US6757766B1 (en) * 1998-11-24 2004-06-29 Siemens Aktiengesellschaft Bus system for a highly scalable multiprocessor system and method for transmitting information in the bus system
US20100188972A1 (en) * 2009-01-27 2010-07-29 Knapp David J Fault tolerant network utilizing bi-directional point-to-point communications links between nodes
US20160034368A1 (en) * 2014-08-01 2016-02-04 Renesas Electronics Corporation Semiconductor device

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6237124B1 (en) * 1998-03-16 2001-05-22 Actel Corporation Methods for errors checking the configuration SRAM and user assignable SRAM data in a field programmable gate array
US20080147908A1 (en) * 2006-12-13 2008-06-19 Microchip Technology Incorporated Direct Memory Access Controller with Error Check
US7870299B1 (en) * 2008-02-06 2011-01-11 Westinghouse Electric Co Llc Advanced logic system
JP5038549B2 (ja) * 2010-03-11 2012-10-03 三菱電機株式会社 メモリ診断方法、メモリ診断装置およびメモリ診断プログラム
US8332722B1 (en) * 2010-08-11 2012-12-11 Microelectronics Research and Development Corporation Method and architecture for performing scrubbing of an FPGA's configuration memory
US11675659B2 (en) * 2016-07-15 2023-06-13 Advanced Micro Devices, Inc. DDR memory error recovery
US10303899B2 (en) * 2016-08-11 2019-05-28 Intel Corporation Secure public cloud with protected guest-verified host control
US11461485B2 (en) * 2016-08-12 2022-10-04 ALTR Solutions, Inc. Immutable bootloader and firmware validator
US10055164B2 (en) * 2016-09-07 2018-08-21 Sandisk Technologies Llc Data storage at an access device
US11200106B2 (en) * 2019-08-12 2021-12-14 Advanced Micro Devices, Inc. Data integrity for persistent memory systems and the like
US20200272533A1 (en) * 2020-05-14 2020-08-27 Intel Corporation Detecting memory mismatch between lockstep systems using a memory signature

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6757766B1 (en) * 1998-11-24 2004-06-29 Siemens Aktiengesellschaft Bus system for a highly scalable multiprocessor system and method for transmitting information in the bus system
US20030131197A1 (en) * 2002-01-07 2003-07-10 Morrison John M. Shared cache for data integrity operations
US20100188972A1 (en) * 2009-01-27 2010-07-29 Knapp David J Fault tolerant network utilizing bi-directional point-to-point communications links between nodes
US20160034368A1 (en) * 2014-08-01 2016-02-04 Renesas Electronics Corporation Semiconductor device

Also Published As

Publication number Publication date
US20220050740A1 (en) 2022-02-17
US11249839B1 (en) 2022-02-15

Similar Documents

Publication Publication Date Title
EP2095234B1 (fr) Système mémoire avec unité de code correcteur d'erreur et autre agencement de traitement
CN114328316B (zh) Dma控制器、soc系统及基于dma控制器的数据搬运方法
US9665448B2 (en) Semiconductor integrated circuit
US8868517B2 (en) Scatter gather list for data integrity
EP3955112A1 (fr) Procédé et appareil de détection d'erreurs de mémoire
US6539338B1 (en) Self-diagnostic testing of a network interface adapter
US10585772B2 (en) Power supply diagnostic strategy
CN111428280B (zh) SoC安全芯片密钥信息完整性存储及错误自修复方法
EP4266178A1 (fr) Validation de code de correction d'erreur
CN111913668A (zh) 一种ip复用下检纠查存储器数据准确性的方法
CN111880961A (zh) 用于透明寄存器数据错误检测和纠正的系统和方法
EP3882774B1 (fr) Dispositif de traitement de données
CN115904230A (zh) 一种数据校验方法、系统及装置
WO2021043246A1 (fr) Procédé et appareil de lecture de données
JPH0316655B2 (fr)
US20240134743A1 (en) Electronic device, electronic system, method for operating an electronic device, and method for operating an electronic system
CN116341011B (zh) 一种检测系统及方法
JP2013109532A (ja) 診断修復装置、診断修復方法、及び診断修復プログラム
US20230359523A1 (en) Memory integrity check
JP3358701B2 (ja) ベリファイ方法およびベリファイ装置
JP2017134507A (ja) メモリ管理システム
EP2590080B1 (fr) Correction d'erreur
CN115827336A (zh) 一种cpu中冗余plc的校验方法、装置及介质
CN117932702A (zh) 一种寄存器译码保护系统及方法
CN117371053A (zh) 嵌入式系统的数据处理方法、装置、半导体芯片及存储介质

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE APPLICATION HAS BEEN PUBLISHED

AK Designated contracting states

Kind code of ref document: A1

Designated state(s): AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: REQUEST FOR EXAMINATION WAS MADE

17P Request for examination filed

Effective date: 20220721

RBV Designated contracting states (corrected)

Designated state(s): AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: EXAMINATION IS IN PROGRESS

17Q First examination report despatched

Effective date: 20221122