EP3944224A1 - Procédé de commande d'un d'affichage - Google Patents

Procédé de commande d'un d'affichage Download PDF

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Publication number
EP3944224A1
EP3944224A1 EP20187071.4A EP20187071A EP3944224A1 EP 3944224 A1 EP3944224 A1 EP 3944224A1 EP 20187071 A EP20187071 A EP 20187071A EP 3944224 A1 EP3944224 A1 EP 3944224A1
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EP
European Patent Office
Prior art keywords
dimming
pixel
gate
driving transistor
display
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP20187071.4A
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German (de)
English (en)
Inventor
Lynn VERSCHUEREN
Marc AMEYS
Jan Genoe
Wim Dehaene
Kris Myny
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Katholieke Universiteit Leuven
Interuniversitair Microelektronica Centrum vzw IMEC
Original Assignee
Katholieke Universiteit Leuven
Interuniversitair Microelektronica Centrum vzw IMEC
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Application filed by Katholieke Universiteit Leuven, Interuniversitair Microelektronica Centrum vzw IMEC filed Critical Katholieke Universiteit Leuven
Priority to EP20187071.4A priority Critical patent/EP3944224A1/fr
Publication of EP3944224A1 publication Critical patent/EP3944224A1/fr
Withdrawn legal-status Critical Current

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3258—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the voltage across the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0439—Pixel structures
    • G09G2300/0465—Improved aperture ratio, e.g. by size reduction of the pixel circuit, e.g. for improving the pixel density or the maximum displayable luminance or brightness
    • G—PHYSICS
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0202—Addressing of scan or signal lines
    • G09G2310/0221—Addressing of scan or signal lines with use of split matrices
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0247—Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/06—Adjustment of display parameters
    • G09G2320/0626—Adjustment of display parameters for control of overall brightness
    • G09G2320/0633—Adjustment of display parameters for control of overall brightness by amplitude modulation of the brightness of the illumination source
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/06—Adjustment of display parameters
    • G09G2320/0626—Adjustment of display parameters for control of overall brightness
    • G09G2320/064—Adjustment of display parameters for control of overall brightness by time modulation of the brightness of the illumination source
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2360/00—Aspects of the architecture of display systems
    • G09G2360/14—Detecting light within display terminals, e.g. using a single or a plurality of photosensors
    • G09G2360/144—Detecting light within display terminals, e.g. using a single or a plurality of photosensors the light being ambient light

Definitions

  • the present inventive concept relates to a method of driving an active-matrix display, to a display backplane configured to carry out the method, and to a display comprising the backplane.
  • AMOLED active-matrix OLED displays
  • dimming i.e., the control of the overall brightness level of the whole display, or at least a substantial part the display, is important for the overall performance of the display.
  • Accurate dimming in a wide range needs to be performed together with the controlling of pixel-level luminance levels.
  • Good grey-level luminance control is needed at all overall brightness settings.
  • An objective of the present inventive concept is to provide a method of driving a display comprising an active matrix, allowing for reduced power consumption and/or increased resolution at a given dimming performance.
  • a method of driving a display comprising an active matrix comprising a plurality of pixel circuits, each pixel circuit of said plurality of pixel circuits comprising a pixel-driving transistor, each said pixel-driving transistor comprising a first gate and a second gate, said method comprising:
  • a second gate such as a back gate, on the pixel-driving transistor is used to implement common dimming in a dimming area, which may correspond to the whole or a part of the display. This allows dimming, i.e., the changing of the average brightness of the pixels in the dimming area, without adding an additional transistor in the current path of the pixel circuit.
  • each said second gate is a back gate of the respective pixel-driving transistor.
  • Changing the voltage on the back gate of the pixel-driving transistor may shift the threshold voltage ( V T ) of that transistor.
  • V T threshold voltage
  • each said first gate is a front gate of the respective pixel-driving transistor.
  • one of said first gate and said second gate is a front gate of the respective pixel-driving transistor and the other of said first gate and said second gate is a back gate of said pixel-driving transistor.
  • said luminance signal is an analog voltage.
  • each pixel of, e.g., an AMOLED display may be accurately controlled without modifying the true colors.
  • said dimming signal is pulse-width modulated, PWM.
  • the method is carried out according to a timing scheme, wherein:
  • said dimming signal is either held high, or low.
  • said dimming area is a first dimming area
  • said method further comprising: dimming and controlling a second dimming area according to said timing scheme, wherein a dimming phase of said second dimming area at least partially does not coincide with said dimming phase of the timing scheme of said first dimming area.
  • each said pixel circuit comprises a second pixel-driving transistor, said dimming further comprising: applying a second common dimming signal at each respective second gate of the second pixel-driving transistor comprised in each pixel circuit comprised in said dimming area.
  • This may be generalized to more than two pixel-driving transistors.
  • each said pixel circuit comprises a plurality of pixel-driving transistors, the dimming comprising: applying a respective further common dimming signal at each respective second gate of each second pixel-driving transistor comprised in each pixel circuit comprised in said dimming area.
  • said pixel circuit comprised in said dimming area further comprises a control transistor and a capacitor, wherein, during said controlling, said luminance level is set by charging said capacitor through said control transistor.
  • said controlling, said luminance level of said pixel is set by addressing said control transistor on one or more control lines and said analog voltage is set through a data line.
  • said display is an OLED, LED, QLED, ⁇ LED, or PeLED display.
  • said driving transistor is a field-effect transistor, such as a thin-film transistor (TFT) or a metal-oxide-semiconductor field-effect transistor (MOSFET).
  • TFT thin-film transistor
  • MOSFET metal-oxide-semiconductor field-effect transistor
  • an active-matrix display backplane comprising the active matrix above and configured to carry out the method above.
  • Fig. 1 shows a schematic of a pixel circuit 100, which may form part of an active matrix of a display backplane and drive a pixel of a display (cf. Fig. 6 ).
  • the display may be an OLED, LED, QLED, ⁇ LED, or PeLED display, wherein each pixel of the display comprises a light-emitting diode (LED) 126, which may be an OLED, driven by each respective display-circuit 100.
  • the LED 126 may, as shown in Fig. 1 at a first terminal, which may be an anode, be connected to a supply voltage V DD 124, which may be a common supply voltage of the backplane.
  • the pixel-circuit comprises a pixel-driving transistor 102, which may, for example, be a thin-film transistor (TFT) or a metal-oxide-semiconductor field-effect transistor (MOSFET).
  • TFT thin-film transistor
  • MOSFET metal-oxide-semiconductor field-effect transistor
  • the pixel-driving transistor 102 may, at a first terminal 108, which may be a source terminal or a drain terminal, be connected to the second terminal of the LED 126, which may be a cathode of the LED 126.
  • a second terminal 110 which may be a drain terminal if the first terminal is a source terminal, or a source terminal if the first terminal 108 is a drain terminal
  • the first pixel-driving transistor 102 may be connected to a ground 112, which may be a common ground to the backplane.
  • the pixel-driving transistor 102 comprises two further terminals in the in the form of a first gate 104, which, as shown, may be front gate, as known per se, of the pixel-driving transistor 102, and a second gate 106, which, as shown, may be, respectively, a back gate, of the pixel-driving transistor, as known per se.
  • the roles of the first gate and the second gate, relative to what will be described in the following, may be reversed, so that the first gate is the back gate of the pixel-driving transistor 102 and the second gate is the front gate of the pixel-driving transistor 102.
  • the pixel-driving transistor 102 may at second gate 106 be connected to a global, i.e., common signal BG used for dimming in the dimming area in which the pixel circuit 100 is comprised.
  • one of the first gate and the second gate may a front gate of the pixel-driving transistor 102 and the other of the first gate and the second gate may be a back gate of said pixel-driving transistor.
  • the pixel-driving transistor 102 of the pixel circuit 100 may drive the pixel of which the LED 126 forms part, controlled by the first gate 104 and the second gate 106 of the pixel-driving transistor 102.
  • the pixel circuit 100 may further comprise a capacitor 122 connected between the first gate 104 of the pixel-driving transistor 102 and ground 112.
  • the pixel circuit 100 may comprise a control transistor 114, which is connected at a first terminal 120 to the first gate 104 of the pixel driving transistor 102 and to a capacitor 122.
  • the capacitor 122 may function as a pixel capacitor and thus be connected to the front gate 104 of the pixel-driving transistor 102 and the first terminal 120, which may be a source terminal or a drain terminal, of the control transistor 114.
  • the capacitor 122 may be charged through a data line DATA connected to a second terminal 118 of the control transistor 114.
  • the first terminal 120 may be a source terminal and the second terminal 118 may be a drain terminal, or vice versa.
  • the configuration with the pixel circuit 100 comprising the pixel-driving transistor 102, the control transistor 114 and the capacitor 122, may be referred to as a 2T1C - 2 transistor 1 capacitor - configuration of the pixel circuit 100.
  • the pixel of the pixel circuit 100 of Fig. 1 may belong to a dimming area.
  • the dimming area comprises a plurality of pixel circuits 100, each controlling a (sub)pixel of the display.
  • the dimming area corresponds to the whole display.
  • the display may also comprise several dimming areas, as will be exemplified below in conjunction with Fig. 6 .
  • the control transistor 114 may function as a selection transistor, allowing a luminance, i.e., gray-level, data signal into the front gate 104 of the pixel-driving transistor 102.
  • a back gate (not shown) of the control transistor may be connected to the front gate 116 of the control transistor 114.
  • a dimming area may be dimmed by applying a dimming signal BG at the respective second gate 106 of the pixel-driving transistor 102 at each pixel circuit of each pixel comprised in the dimming area.
  • the dimming signal is common - or global - in the sense the same dimming signal is applied at each pixel in the dimming area.
  • the luminance level of the pixel connected, i.e., associated with, a pixel circuit 100 comprised in the dimming area may be controlled by applying a luminance signal at the first gate 104 of the pixel-driving transistor 102 of the pixel circuit 100.
  • the luminance signal applied on the front gate 104 of the pixel-driving transistor 102 may be determined by the image content to be shown on the display, while the common dimming signal applied on the back gate 106 of the pixel-driving transistor depends on the common overall brightness setting for the dimming area, or the whole display, and can thus vary depending on the ambient light environment where the display is located.
  • the threshold voltage ( V T ) of the pixel-driving transistor 102 shifts by changing the voltage on the back gate 106 of the transistor, the average brightness for the same data voltage range, as applied on the front gate 104 of the pixel-driving transistor can be changed by varying the back gate 106 voltage.
  • the back gate 106 voltage can be used to adjust the global brightness setting in the dimming area in which the pixel circuit 100 is comprised.
  • the dimming signal may be a digital pulse-width modulated (PWM) signal
  • the luminance signal may be an analog voltage
  • PWM digital pulse-width modulated
  • an analog data voltage is applied to the front gate 104 of the pixel-driving transistor 102 to set the correct luminance level, i.e., grey-level
  • a common PWM signal is applied to the back gate 106 of the pixel-driving transistor 102 to set the global brightness of the dimming area.
  • the dimming signal is a digital signal and thus has two possible values, namely a "high” voltage (digital “1”) or a “low” voltage (digital “0").
  • the dimming signal switching between the "low” state and the "high” state, the shifting of the threshold voltage of the pixel-driving transistor 102 results in the pixel driving transistor 102 being completely turned off, or controlled by the luminance signal, respectively.
  • the duty cycle of the PWM signal will impact the apparent brightness of the LED, and, as a result of the whole dimming area of which the LED forms part.
  • Fig. 8 shows the current through the LED 126 as a function of the front gate 104 voltage of pixel-driving transistor 102.
  • the dimming signal BG When the dimming signal BG is in a "high" state (digital "1"), the current through the drive pixel-driving transistor 102, and thus through the LED 126, is shown by a dotted line.
  • increasing the data voltage i.e., front gate 104 voltage of the pixel-driving transistor 102, results in increasing current through the pixel, and thus a brighter pixel.
  • the brightness of the pixel can be adjusted by varying this data voltage.
  • the data voltage may be different for every pixel, as determined by content of the image frame displayed.
  • the drive transistor is always off (not conducting current), as shown by a solid line, regardless of the data voltage, within a defined data voltage range. Since there is no current through the LED 126, the pixel will not emit any light.
  • this common dimming signal applied to the back gate 106 of the driving transistor 102 can switch the pixel on or off. If the display is switched on and off fast enough, the human eye will average the light intensity, and thus the apparent overall brightness of the display will be determined by the on-time (duty cycle, DC) of the PWM dimming signal. Typically, in very bright environments, the duty cycle (DC) will be larger, resulting in a brighter display.
  • DC duty cycle
  • the luminance level may be set by applying a selection signal SEL at the gate 116 of the control transistor 114 and applying a luminance level voltage as a DATA signal at the second terminal 118 of the control transistor 114, charging the capacitor 122 to that voltage.
  • the luminance level is set by charging the capacitor 122 through the control transistor 114.
  • a different luminance signal is applied at each different pixel comprised in the dimming area.
  • the dimming of the dimming area and the controlling of the luminance level of the pixel may be coinciding or disjunct in time, as will be exemplified below.
  • BG digital dimming
  • the data voltage can be implemented as either an analog signal or a digital signal.
  • the brightness of the pixel is determined by the analog gate voltage, whereas when it is implemented as a digital signal, the duty cycle will determine the (apparent) brightness of the pixel.
  • the common dimming signal can be either digital or analog.
  • the duty cycle will determine the common brightness setting of the dimming area, whereas an analog global dimming signal will control the V T of all the pixels, to adjust the achievable current levels, and thus the global brightness setting. Any combination of digital and analog signals is possible.
  • a digital data signal may be preferred, due to a color (wavelength) shift caused by changing the current through the LED.
  • the current through the LED is always the same, ensuring the correct color point remains.
  • the apparent brightness of the pixel is then determined by the duty cycle of the digital data signal, resulting in different grey-levels, corresponding to the image content.
  • the common dimming signal can be a global analog signal, applied to the back gate of the drive transistor of every pixel circuit. Adjusting this common dimming signal, will shift the threshold voltage ( V T ) of the pixel-driving transistor in every pixel, and hence determines the current through the pixels, and thus the overall brightness of the display. Although this change in current will shift the wavelength of all LEDs, the same color point can be achieved by selecting the correct global dimming voltages, which can be different for red, green, and blue, to compensate for the wavelength shifts.
  • Fig. 3 shows a display backplane comprising a plurality of pixel circuits 100 as described above in conjunction with Fig. 1 . Again, each pixel circuit 100 may, as shown, be connected to a respective LED 126.
  • the pixel circuits 100 may be arranged in a two-dimensional grid.
  • the backplane may, as shown, comprise a plurality of data lines DATA 1 , DATA 2 ... and a plurality of selection lines SEL 1 , SEL 2 ...
  • a display controller 300 may be connected to the backplane or be comprised in the same, and may comprise a plurality of data output lines DATA i 302 connected to the respective data lines DATA 1 302a, DATA 2 302b... of the backplane, and a plurality of selection output lines SEL j 304 connected to the respective selection lines SEL 1 304a, SEL 2 304b ... of the backplane.
  • the display controller 300 comprises a dimming output line BG 306 connected to each pixel circuit 100 of the backplane.
  • the display may comprise a plurality of dimming areas.
  • the display controller 300 may comprise a plurality of dimming output lines 306, each corresponding to a different dimming area and each connected to the second gates of the pixel-driving transistors of each of the pixel circuits 100 comprised in that dimming area.
  • each respective data line 302 DATA 1 302a, DATA 2 302b may be connected to the pixel circuits 100 along a first dimension of the backplane, for example, as shown, forming vertical columns in the display backplane.
  • Each data line may be connected to the second terminal 118 of the respective control transistor of the respective pixel circuit 100.
  • each respective selection line 304 SEL 1 304a, SEL 2 304b may be connected to the pixel circuits 100 along a second dimension of the backplane, for example, as shown, forming horizontal lines in the display backplane.
  • Each selection line may be connected to the gate 116 of the respective control transistor of the respective pixel circuit 100.
  • the display controller may successively scan each horizontal line by successively putting a digital signal in a "high” state on each selection line 304 SEL 1 304a, SEL 2 304b..., while simultaneously putting a digital signal in a "low” state on each other selection line. Simultaneously, the display controller puts respective analog voltages on each data line DATA 1 302a, DATA 2 302b... for setting the luminance of each respective pixel in the selected line.
  • the luminance level of a pixel is set by addressing the control transistor 114 on a control line, i.e., a selection line 304 SEL 1 304a, SEL 2 304b... and the analog voltage is set through a data line 302 DATA 1 302a, DATA 2 302b.
  • Fig. 5 shows a timing diagram 500 according to which the controlling of the luminance levels of the pixels and the dimming may be performed in a display comprising the backplane of Fig. 3 .
  • the controlling of the luminance levels of the pixels may be performed in a controlling phase 504, and the dimming performed in a dimming phase 506, where the controlling phase 504 and the dimming phase 506 are disjunct, i.e., non-coincident in time.
  • each selection line SEL 1 , SEL 2 is, in succession, put “high” by the display controller 300, as described above in conjunction with Fig. 3 , while the other selection lines are kept in a "low” state, while each data line carries analog luminance levels for each pixel in the line selected by the respective selection line.
  • the dimming signal BG may, as shown, be kept constant, either in a "high” state or in a "low” state.
  • dimming may be performed by pulse-width modulating the dimming signal BG, while each luminance signal is held constant by the corresponding capacitor 122 of each pixel circuit 100.
  • the method example is carried out according to a timing scheme, wherein the controlling of the luminance signal is carried out in the controlling phase 504, while the dimming signal BG is held constant, and the dimming is performed in the dimming phase 506, not coinciding with the controlling phase 504, where each luminance signal is held constant.
  • the scheme may then re-start for the next frame 502, as seen at the right edge of Fig. 5 .
  • the image frame 502 is split in two portions, one, the controlling phase 504 for scanning of the data to display the image, thus comprising a data-scanning subframe, and one, the dimming phase 506 to apply a common, i.e., global, PWM-modulated dimming signal BG.
  • the dimming signal BG is always kept at a constant voltage while the data is programmed on each pixel.
  • the dimming phase 506 no data is written.
  • the dimming signal BG may be kept constant either in a "high” state or in a “low” state. This holding of the dimming signal either "high” or “low” may be decided depending on the desired overall brightness level of the dimming area, as will be explained in the following.
  • the desired overall brightness level corresponds to an overall PWM duty cycle of 50%, or less.
  • the dimming signal BG is held “low", or at zero, during the controlling phase 504, while, during the dimming phase 506, a PWM dimming signal is applied as the dimming signal BG.
  • the PWM dimming signal may have a PWM duty cycle between 0% and 100% measured over the dimming cycle, corresponding, due to the dimming signal being held "low", or at zero, during the controlling phase 504, if the controlling phase 504 and the dimming phase 506 are of equal length, to an overall duty cycle in the range 0% to 50%.
  • the desired overall brightness level corresponds to an overall PWM duty cycle of 50%, or more.
  • the dimming signal BG is held "high", or at one, during the controlling phase 504, while, during the dimming phase 506, a PWM dimming signal is applied as the dimming signal BG.
  • the PWM dimming signal may have a PWM duty cycle between 0% and 100% measured over the dimming cycle, corresponding, due to the dimming signal being held "high", or at one, during the controlling phase 504, if the controlling phase 504 and the dimming phase 506 are of equal length, to an overall duty in the range 50% to 100%.
  • Fig. 6 schematically shows a display 600 having a first dimming area 602a and a second dimming area 602b.
  • the backplane of the display 600 comprises a plurality of data lines DATA 1 , DATA 2 , ..., DATA M , for example, as shown in Fig. 6 , corresponding to vertical columns of the display 600.
  • the display 600 comprises a plurality of selection lines.
  • selection lines SEL 1 , SEL 2 , ... , SEL N/2 correspond to pixels in the first dimming area 602a and selection lines SEL N/2+1 , SEL N/2+2 ,. ..., SEL N correspond to pixels in the second dimming area 602b.
  • a pixel circuit 100 (not shown, cf. Fig. 1 ) is located (cf. Fig. 3 ).
  • Dimming in the first dimming area 602a is controlled by a first dimming signal BG 1 connected to the respective second gates 106 of the pixel-driving transistors 102 (cf. Figs 1, 3 ) of the pixel circuits 100 comprised in the first dimming area 602a.
  • Dimming in the second dimming area 602b is controlled by a second dimming signal BG 2 connected to the respective second gates 106 of the pixel-driving transistors 102 (cf. Figs 1, 3 ) of the pixel circuits 100 comprised in the second dimming area 602b.
  • Fig. 7 shows a timing diagram 700 according to which the controlling and the dimming of the display 600, having two dimming areas 602a, 602b, may be performed.
  • controlling and dimming may be performed in a first phase 704 and a second phase 706, where the first phase 704 and the second phase 706 are disjunct, i.e., non-coincident in time.
  • each selection line of the first dimming area 602a SEL 1 , SEL 2 ,..., SELx , SEL N/2 is, in succession, put "high” by the display controller 300, while the other selection lines, in both dimming areas 602a, 602b are kept in a "low” state, while each data line carries analog luminance levels for each pixel in the line selected by the respective selection line.
  • the dimming signal BG 1 for the first dimming area 602a may, as shown, be kept constant, either in a "high” state or in a “low” state. A choice between these two options may be made as described above in conjunction with Fig. 5 depending on a desired overall brightness of the first dimming area 602a.
  • dimming may be performed in the second dimming area 602b by pulse-width modulating the dimming signal BG 2 , while each luminance signal in the second dimming area 602b is held constant by the corresponding capacitor 122 of each pixel circuit 100.
  • each selection line of the second dimming area SEL N/2+1 , SEL N/2+2 ,..., SEL N is, in succession, put "high” by the display controller 300, while the other selection lines, in both dimming areas 602a, 602b are kept in a "low” state, while each data line carries analog luminance levels for each pixel in the line selected by the respective selection line.
  • the dimming signal for the second dimming area BG 2 may, as shown, be kept constant, either in a "high” state or in a “low” state.
  • a choice between these two options may be made as described above in conjunction with Fig. 5 depending on a desired overall brightness of the second dimming area 602b.
  • dimming may be performed in the first dimming area 602a by pulse-width modulating the dimming signal BG 1 , while each luminance signal in the first dimming area 602a is held constant by the corresponding capacitor 122 of each pixel circuit 100.
  • controlling and dimming is performed according to the same timing scheme as described above in conjunction with Fig. 5 , separately for the first dimming area 602a and the second dimming area 602b.
  • controlling of the luminance signals in the first dimming area 602a is carried out in the first phase 704, thus corresponding to a controlling phase for the first dimming area 602a, while the dimming signal BG 1 for the first dimming area 602a is held constant, while the dimming in the first dimming area 602a is performed in the second phase 706, thus corresponding to a dimming phase for the first dimming area 602a and not coinciding with the first phase 704, where each luminance signal is held constant.
  • controlling of the luminance signals in the second dimming area 602b is carried out in the second phase 706, thus corresponding to a controlling phase for the second dimming area 602b, while the dimming signal BG 2 for the second dimming area 602b is held constant, while the dimming in the second dimming area 602b is performed in the first phase 704, thus corresponding to a dimming phase for the second dimming area 602b and not coinciding with the second phase 706, where each luminance signal is held constant.
  • the display 600 is divided into two sections, i.e., the first dimming area 602a and the second dimming area 602b, which may correspond to the top half and the bottom half of the display 600.
  • the dimming signal in this dimming area, BG 1 may be switched, such as pulse-width modulated, during the second phase 706.
  • the dimming signal in this dimming area, BG 2 may be switched, such as pulse-width modulated, during the first phase 704.
  • Fig. 2 shows a schematic of a second pixel circuit 200, comprising a first pixel-driving transistor 102 and a second pixel-driving transistor 202, connected in parallel.
  • the second pixel circuit 200 comprises an additional pixel-driving transistor 202.
  • the second pixel-driving transistor 202 may, just like the first pixel-driving transistor 102, at a first terminal 108, which may be a source terminal or a drain terminal, be connected to the second terminal of the LED 126.
  • a second terminal 110 which may be a drain terminal if the first terminal 108 is a source terminal, or a source terminal if the first terminal 108 is a drain terminal, the second pixel-driving transistor may be connected to ground 112.
  • the second pixel-driving transistor 202 may, just like the first pixel-driving transistor, comprise two further terminals in the in the form of a first gate 104, which, as shown, may be front gate of the pixel-driving transistor 202, and a second gate 206b, which, as shown, may be, respectively, a back gate of the pixel-driving transistor.
  • the roles of the first gate and the second gate of the second pixel-driving transistor may, relative to what will be described in the following, be reversed, so that the first gate is the back gate of the second pixel-driving transistor 202 and the second gate is the front gate of the second pixel-driving transistor 202.
  • first pixel-driving transistor 102 and the second pixel-driving transistor 202 may have different characteristics.
  • the first pixel-driving transistor 102 and the second pixel driving transistor 202 may have different W/L ratios and hence produce a different current through the LED 126 for the same front gate voltage and back gate voltage.
  • a third pixel-driving transistor there may be a third pixel-driving transistor, a fourth pixel-driving transistor, and so on, each connected just like the first pixel-driving transistor 102 and the second pixel-driving transistor 202.
  • pixel-driving transistors in the pixel circuit 200, which may each have different characteristics, such as different W/L.
  • the pixel circuit 200 of Fig. 2 may belong to a dimming area.
  • the dimming area comprises a plurality of pixels, each having a pixel circuit 200 according to Fig. 2 .
  • a dimming area may be dimmed by applying a first dimming signal BG 1 at the respective second gate 206a of the first pixel-driving transistor 102 at each pixel circuit 200 of each pixel comprised in the dimming area, and a second dimming signal BG 2 at the respective second gate 206b of the second pixel-driving transistor 202 at each pixel circuit 200 of each pixel comprised in the dimming area.
  • a dimming signal BG i is applied at the ith driving transistor in each pixel circuit.
  • Each dimming signal BG n is common in the sense the same dimming signal is applied at the respective second gate 106 at the respective driving transistor at each pixel in the dimming area.
  • each dimming signal may be a digital pulse-width modulated (PWM) signal.
  • multiple pixel-driving transistors 102, 202 may be used in parallel with different common dimming signals to select which of the drive transistors is used.
  • Each dimming signal may select which of the drive transistors are on. For example, when BG 1 is “high” and BG 2 is “low”, only the first pixel-driving transistor 102 will be on, so the overall brightness of the display in the dimming area will be determined by the W/L ratio of the first pixel-driving transistor 102. When BG 1 is “low” and BG 2 is “high”, only the second pixel-driving transistor 202 will be on, thus the overall brightness of the display in the dimming area will be determined by the W/L ratio of the second pixel-driving transistor 202.
  • both pixel-driving transistors 102, 202 When both BG 1 and BG 2 are "high", both pixel-driving transistors 102, 202 will be on, so that overall brightness of the display in the dimming area will be determined by the sum of the W/L ratio of the first pixel-driving transistor 102 and the W/L ratio of the second pixel-driving transistor 202. Hence, this allows for three different overall brightness settings in the dimming area. This principle may be generalized to more than two pixel-driving transistors, and thus to more than three different overall brightness settings.
  • the luminance level of the pixel connected, i.e., associated with, a pixel circuit 200 comprised in the dimming area may be controlled by applying a luminance signal at the first gate 104 of each pixel-driving transistor of the pixel circuit 200, such as, in the example of Fig. 2 , the first pixel-driving transistor 102 and the second pixel-driving transistor 202.
  • the luminance signal may, for example, be an analog voltage.
  • the luminance level may be set by applying a selection signal SEL at the gate 116 of the control transistor 114 and applying a luminance level voltage as a DATA signal at the second terminal 118 of the control transistor 114, charging the capacitor 122 to that voltage.
  • the luminance level is set by charging the capacitor 122 through the control transistor 114.
  • a different luminance signal is applied at each different pixel circuit comprised in the dimming area.
  • the dimming of the dimming area and the controlling of the luminance level of the pixel may be coinciding or disjunct in time, as will be exemplified below.
  • Fig. 4 shows a display backplane comprising a plurality of pixel circuits 200 as described above in conjunction with Fig. 2 .
  • Each pixel circuit 200 may, as shown, be connected to a respective LED 126.
  • the pixel circuits 200 may be arranged in a two-dimensional grid.
  • the backplane may, as shown, comprise a plurality of data lines DATA 1 , DATA 2 ... and a plurality of selection lines SEL 1 , SEL 2 ...
  • a display controller 300 may be connected to the backplane or be comprised in the same, and may comprise a plurality of data output lines DATA i 302 connected to the respective data lines DATA 1 302a, DATA 2 302b... of the backplane, a plurality of selection output lines SEL j 304 connected to the respective selection lines SEL 1 304a, SEL 2 304b ... of the backplane.
  • the display controller 300 comprises a first dimming output line BG 1 306a and a second dimming output line BG 2 306b, each connected to each pixel circuit 200 of the backplane, the display in the depicted case comprising only one dimming area.
  • the display may comprise a plurality of dimming areas.
  • the display controller may comprise a plurality of sets of dimming output lines 306, each set of dimming output lines corresponding to a different dimming area and each dimming line of a set of dimming lines connected to the display circuits 200 comprised in the corresponding dimming area.
  • each respective data line 302 DATA 1 302a, DATA 2 302b may be connected to the pixel circuits 200 along a first dimension of the backplane, for example, as shown, forming vertical columns in the display backplane.
  • Each data line may be connected to the second terminal 118 of the respective control transistor of the respective pixel circuit 200.
  • each respective selection line 304 SEL 1 304a, SEL 2 304b may be connected to the pixel circuits 200 along a second dimension of the backplane, for example, as shown, forming horizontal lines in the display backplane.
  • Each selection line may be connected to the gate 116 of the respective control transistor of the respective pixel circuit 200.
  • the display controller may successively scan each horizontal line by successively putting a digital signal in a "high” state on each selection line 304 SEL 1 304a, SEL 2 304b..., which simultaneously putting a digital signal in a "low” state on each other selection line. Simultaneously, the display controller puts respective analog voltages on each data line DATA 1 302a, DATA 2 302b... for setting the luminance of each respective pixel in the selected line.
  • the luminance level of a pixel is set by addressing the control transistor 114 on a control line, i.e., a selection line 304 SEL 1 304a, SEL 2 304b... and the analog voltage is set through a data line DATA 1 302a, DATA 2 302b.
  • the back gate and (front)gate of the pixel-driving transistors can be interchanged while staying within the concept of this invention.
  • the principle of this invention was explained for a simple 2T1C pixel circuit, but can easily be applied to different pixel circuits.
  • the implementation of Figs 2 and 4 with multiple pixel-driving transistors in parallel, is not limited to two drive transistors in parallel, but can be elaborated to any number of drive transistors in parallel.

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  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040227707A1 (en) * 2000-04-27 2004-11-18 Semiconductor Energy Laboratory Co., Ltd. Light emitting device
US20060164345A1 (en) * 2005-01-26 2006-07-27 Honeywell International Inc. Active matrix organic light emitting diode display
JP2013131608A (ja) * 2011-12-21 2013-07-04 Canon Inc 発光装置
WO2020157152A1 (fr) * 2019-01-29 2020-08-06 Osram Opto Semiconductors Gmbh Mur vidéo, circuit d'attaque, commandes et procédé associé

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040227707A1 (en) * 2000-04-27 2004-11-18 Semiconductor Energy Laboratory Co., Ltd. Light emitting device
US20060164345A1 (en) * 2005-01-26 2006-07-27 Honeywell International Inc. Active matrix organic light emitting diode display
JP2013131608A (ja) * 2011-12-21 2013-07-04 Canon Inc 発光装置
WO2020157152A1 (fr) * 2019-01-29 2020-08-06 Osram Opto Semiconductors Gmbh Mur vidéo, circuit d'attaque, commandes et procédé associé

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