EP3944224A1

EP3944224A1 - Method of driving a display

Info

Publication number: EP3944224A1
Application number: EP20187071.4A
Authority: EP
Inventors: Lynn VERSCHUEREN; Marc AMEYS; Jan Genoe; Wim Dehaene; Kris Myny
Original assignee: Katholieke Universiteit Leuven; Interuniversitair Microelektronica Centrum vzw IMEC
Current assignee: Katholieke Universiteit Leuven; Interuniversitair Microelektronica Centrum vzw IMEC
Priority date: 2020-07-21
Filing date: 2020-07-21
Publication date: 2022-01-26

Abstract

A method of driving a display (600) is disclosed. The display (600) comprises an active matrix comprising a plurality of pixel circuits (100; 200), each pixel circuit (100; 200) of the plurality of pixel circuits comprising a pixel-driving transistor (102, 202), each pixel-driving transistor (102, 202) comprising a first gate (104) and a second gate (106, 206). The method comprises dimming a dimming area (602a, 602b) of the display (600) by applying a common dimming signal at the respective second gate (106, 206) of each pixel-driving transistor (102, 202) of the pixel circuits (100; 200) comprised in the dimming area (602a, 602b); and controlling a luminance level of a pixel connected to a pixel circuit comprised in the dimming area (602a, 602b) by applying a luminance signal at the first gate (104) of the pixel-driving transistor (102, 202) of the pixel circuit (100; 200).

Description

Technical field

The present inventive concept relates to a method of driving an active-matrix display, to a display backplane configured to carry out the method, and to a display comprising the backplane.

Background

Active-matrix displays are growing increasingly popular.
An example of such displays are active-matrix OLED displays (AMOLED), which provide wide viewing angle, high efficiency and high brightness amongst other attractive characteristics such as its low power consumption and ability to be manufactured on flexible substrates.
Since such displays can be used in many different environments, such as smartphones, smartwatches, or as displays in cars, the brightness of these displays needs to have a very large range, with good accuracy. For example, a display used outside on a sunny day needs a much higher brightness than that same display used in a dark environment, e.g., at night. In all environments, good grey-level (luminance) control is needed at a wide range of overall brightness, to achieve good image reproduction, with good contrast.
Therefore, dimming, i.e., the control of the overall brightness level of the whole display, or at least a substantial part the display, is important for the overall performance of the display. Accurate dimming in a wide range needs to be performed together with the controlling of pixel-level luminance levels. Good grey-level luminance control is needed at all overall brightness settings. At the same time, there is always a constant strive to reduce power consumption for mobile devices.

Summary

An objective of the present inventive concept is to provide a method of driving a display comprising an active matrix, allowing for reduced power consumption and/or increased resolution at a given dimming performance.
To this end, according to a first aspect, there is provided a method of driving a display, said display comprising an active matrix comprising a plurality of pixel circuits, each pixel circuit of said plurality of pixel circuits comprising a pixel-driving transistor, each said pixel-driving transistor comprising a first gate and a second gate, said method comprising:

dimming a dimming area of said display by applying a common dimming signal at the respective second gate of each pixel-driving transistor of the pixel circuits comprised in said dimming area; and
controlling a luminance level of a pixel connected to a said pixel circuit comprised in said dimming area by applying a luminance signal at the first gate of the pixel-driving transistor of said pixel circuit.

Through the present method, a second gate, such as a back gate, on the pixel-driving transistor is used to implement common dimming in a dimming area, which may correspond to the whole or a part of the display. This allows dimming, i.e., the changing of the average brightness of the pixels in the dimming area, without adding an additional transistor in the current path of the pixel circuit.
Compared to using no common dimming, higher display accuracy at a larger range of overall brightness may be achieved. At the same time, the need for an additional transistor to control the common dimming in the current path driving the pixel is eliminated, which would otherwise increase power consumption and/or reduce the achievable resolution, for example through the need for a higher supply voltage. This allows, for example, for an increased display resolution and/or a lower power consumption.
According to an embodiment, each said second gate is a back gate of the respective pixel-driving transistor.
Changing the voltage on the back gate of the pixel-driving transistor may shift the threshold voltage (V_T ) of that transistor. Thus if, the common dimming signal is applied to the back gate of the pixel-driving transistor of pixel circuits comprised in the dimming area, the threshold voltage of all these drive transistors will all shift, resulting in an overall change in brightness, i.e., dimming.
According to an embodiment, each said first gate is a front gate of the respective pixel-driving transistor.
According to an embodiment, one of said first gate and said second gate is a front gate of the respective pixel-driving transistor and the other of said first gate and said second gate is a back gate of said pixel-driving transistor.
According to an embodiment, said luminance signal is an analog voltage.
This way, the brightness of each pixel of, e.g., an AMOLED display may be accurately controlled without modifying the true colors.
According to an embodiment, said dimming signal is pulse-width modulated, PWM.
By applying the PWM modulated common dimming signal at the second gate of the pixel-driving transistor, instead of at a supply line of the display, one avoids having to quickly switch large currents under a high capacitive load, otherwise often associated therewith, making PWM modulated dimming feasible for a larger range of displays, such as displays having higher resolution.
According to an embodiment, the method is carried out according to a timing scheme, wherein:

said controlling is performed in a controlling phase, wherein said dimming signal is held constant during said controlling phase; and
said dimming is performed in a dimming phase not coinciding with said controlling phase, wherein said luminance signal is held constant during said dimming phase.

This allows for accurate control of each pixel luminance level in combination with accurate dimming control in a wide overall luminance range.
According to an embodiment, during said controlling phase, depending on a desired overall brightness level of said dimming area, said dimming signal is either held high, or low.
This further allows for accurate dimming in a wide overall luminance range.
According to an embodiment, said dimming area is a first dimming area, said method further comprising:
dimming and controlling a second dimming area according to said timing scheme, wherein a dimming phase of said second dimming area at least partially does not coincide with said dimming phase of the timing scheme of said first dimming area.
This relaxes the timing restrictions, increasing the time available to introduce the dimming signal onto the respective second gates of the respective pixel-driving transistors, allowing proper dimming at a wide range of global dimming settings even for a large display with a large capacitive load. In particular, any overall dimming duty cycle between 0% and 100% is always reachable, the latter meaning that no maximum overall brightness performance is lost through the present scheme.
According to an embodiment, each said pixel circuit comprises a second pixel-driving transistor, said dimming further comprising:
applying a second common dimming signal at each respective second gate of the second pixel-driving transistor comprised in each pixel circuit comprised in said dimming area.
While hereby an extra transistor is required in the pixel circuit, the power consumption will not increase, since both drive transistors are placed in parallel, and thus the power supply does not need to increase. Furthermore, the increase in pixel area will be limited because the individual drive transistors can be smaller than the drive transistor in an implementation with only one drive transistor. At the same time, this allows for an implementation of common dimming without a PWM signal, eliminating potential flickering problems. Thus, an implementation is achieved with reduced flickering, but without increased power requirements.
This may be generalized to more than two pixel-driving transistors.
Thus, according to an embodiment, each said pixel circuit comprises a plurality of pixel-driving transistors, the dimming comprising:
applying a respective further common dimming signal at each respective second gate of each second pixel-driving transistor comprised in each pixel circuit comprised in said dimming area.
According to an embodiment, said pixel circuit comprised in said dimming area further comprises a control transistor and a capacitor, wherein, during said controlling, said luminance level is set by charging said capacitor through said control transistor.
According to an embodiment, said controlling, said luminance level of said pixel is set by addressing said control transistor on one or more control lines and said analog voltage is set through a data line.
According to an embodiment, said display is an OLED, LED, QLED, µLED, or PeLED display.
According to an embodiment, said driving transistor is a field-effect transistor, such as a thin-film transistor (TFT) or a metal-oxide-semiconductor field-effect transistor (MOSFET).
Further, there is provided an active-matrix display backplane comprising the active matrix above and configured to carry out the method above.
Finally, there is provided a display comprising the backplane above.

Brief description of the drawings

The above, as well as additional objects, features and advantages of the present inventive concept, will be better understood through the following illustrative and non-limiting detailed description, with reference to the appended drawings. In the drawings like reference numerals will be used for like elements unless stated otherwise.

Fig. 1 is a schematic of a pixel circuit.
Fig. 2 is a schematic of a different pixel circuit.
Fig. 3 is a schematic of a display backplane comprising a plurality of pixel circuits according to Fig. 1.
Fig. 4 is a schematic of a display backplane comprising a plurality of pixel circuits according to Fig. 2.
Fig. 5 is a timing diagram.
Fig. 6 schematically shows a display having a first dimming area and a second dimming area.
Fig. 7 is a timing diagram.
Fig. 8 shows the effect of controlling and dimming through a pixel-driving transistor.

Detailed description

Fig. 1 shows a schematic of a pixel circuit 100, which may form part of an active matrix of a display backplane and drive a pixel of a display (cf. Fig. 6).
The display may be an OLED, LED, QLED, µLED, or PeLED display, wherein each pixel of the display comprises a light-emitting diode (LED) 126, which may be an OLED, driven by each respective display-circuit 100. The LED 126 may, as shown in Fig. 1 at a first terminal, which may be an anode, be connected to a supply voltage V _DD 124, which may be a common supply voltage of the backplane.
The pixel-circuit comprises a pixel-driving transistor 102, which may, for example, be a thin-film transistor (TFT) or a metal-oxide-semiconductor field-effect transistor (MOSFET).
As shown in Fig. 1, the pixel-driving transistor 102 may, at a first terminal 108, which may be a source terminal or a drain terminal, be connected to the second terminal of the LED 126, which may be a cathode of the LED 126. At a second terminal 110, which may be a drain terminal if the first terminal is a source terminal, or a source terminal if the first terminal 108 is a drain terminal, the first pixel-driving transistor 102 may be connected to a ground 112, which may be a common ground to the backplane.
Further, the pixel-driving transistor 102 comprises two further terminals in the in the form of a first gate 104, which, as shown, may be front gate, as known per se, of the pixel-driving transistor 102, and a second gate 106, which, as shown, may be, respectively, a back gate, of the pixel-driving transistor, as known per se.
Alternative to what is shown in Fig. 1, the roles of the first gate and the second gate, relative to what will be described in the following, may be reversed, so that the first gate is the back gate of the pixel-driving transistor 102 and the second gate is the front gate of the pixel-driving transistor 102.
The pixel-driving transistor 102 may at second gate 106 be connected to a global, i.e., common signal BG used for dimming in the dimming area in which the pixel circuit 100 is comprised.
Thus, one of the first gate and the second gate may a front gate of the pixel-driving transistor 102 and the other of the first gate and the second gate may be a back gate of said pixel-driving transistor.
In this way, the pixel-driving transistor 102 of the pixel circuit 100 may drive the pixel of which the LED 126 forms part, controlled by the first gate 104 and the second gate 106 of the pixel-driving transistor 102.
As shown in Fig. 1, the pixel circuit 100 may further comprise a capacitor 122 connected between the first gate 104 of the pixel-driving transistor 102 and ground 112.
Further, the pixel circuit 100 may comprise a control transistor 114, which is connected at a first terminal 120 to the first gate 104 of the pixel driving transistor 102 and to a capacitor 122. The capacitor 122 may function as a pixel capacitor and thus be connected to the front gate 104 of the pixel-driving transistor 102 and the first terminal 120, which may be a source terminal or a drain terminal, of the control transistor 114.
By applying a selection signal SEL at the gate 116 of the control transistor 114, the capacitor 122 may be charged through a data line DATA connected to a second terminal 118 of the control transistor 114. For example, the first terminal 120 may be a source terminal and the second terminal 118 may be a drain terminal, or vice versa.
The configuration with the pixel circuit 100 comprising the pixel-driving transistor 102, the control transistor 114 and the capacitor 122, may be referred to as a 2T1C - 2 transistor 1 capacitor - configuration of the pixel circuit 100.
The pixel of the pixel circuit 100 of Fig. 1 may belong to a dimming area. Conversely, the dimming area comprises a plurality of pixel circuits 100, each controlling a (sub)pixel of the display. In the simplest case, the dimming area corresponds to the whole display. However, the display may also comprise several dimming areas, as will be exemplified below in conjunction with Fig. 6.
The control transistor 114 may function as a selection transistor, allowing a luminance, i.e., gray-level, data signal into the front gate 104 of the pixel-driving transistor 102. Optionally, a back gate (not shown) of the control transistor may be connected to the front gate 116 of the control transistor 114.
In a first method example, for driving the display, a dimming area may be dimmed by applying a dimming signal BG at the respective second gate 106 of the pixel-driving transistor 102 at each pixel circuit of each pixel comprised in the dimming area. The dimming signal is common - or global - in the sense the same dimming signal is applied at each pixel in the dimming area.
Moreover, the luminance level of the pixel connected, i.e., associated with, a pixel circuit 100 comprised in the dimming area may be controlled by applying a luminance signal at the first gate 104 of the pixel-driving transistor 102 of the pixel circuit 100.
Thus, the luminance signal applied on the front gate 104 of the pixel-driving transistor 102 may be determined by the image content to be shown on the display, while the common dimming signal applied on the back gate 106 of the pixel-driving transistor depends on the common overall brightness setting for the dimming area, or the whole display, and can thus vary depending on the ambient light environment where the display is located.
Since the threshold voltage (V_T ) of the pixel-driving transistor 102 shifts by changing the voltage on the back gate 106 of the transistor, the average brightness for the same data voltage range, as applied on the front gate 104 of the pixel-driving transistor can be changed by varying the back gate 106 voltage. Hence, the back gate 106 voltage can be used to adjust the global brightness setting in the dimming area in which the pixel circuit 100 is comprised.
For example, the dimming signal may be a digital pulse-width modulated (PWM) signal, and/or the luminance signal may be an analog voltage. Thus, an analog data voltage is applied to the front gate 104 of the pixel-driving transistor 102 to set the correct luminance level, i.e., grey-level, while a common PWM signal is applied to the back gate 106 of the pixel-driving transistor 102 to set the global brightness of the dimming area.
In the case of PWM, the dimming signal is a digital signal and thus has two possible values, namely a "high" voltage (digital "1") or a "low" voltage (digital "0"). The dimming signal switching between the "low" state and the "high" state, the shifting of the threshold voltage of the pixel-driving transistor 102 results in the pixel driving transistor 102 being completely turned off, or controlled by the luminance signal, respectively. Hence, the duty cycle of the PWM signal will impact the apparent brightness of the LED, and, as a result of the whole dimming area of which the LED forms part.
Fig. 8 shows the current through the LED 126 as a function of the front gate 104 voltage of pixel-driving transistor 102.
When the dimming signal BG is in a "high" state (digital "1"), the current through the drive pixel-driving transistor 102, and thus through the LED 126, is shown by a dotted line. In this case, increasing the data voltage, i.e., front gate 104 voltage of the pixel-driving transistor 102, results in increasing current through the pixel, and thus a brighter pixel. Hence, the brightness of the pixel can be adjusted by varying this data voltage. The data voltage may be different for every pixel, as determined by content of the image frame displayed.
In contrast, when the dimming signal BG is in a "low" state (digital "0"), the drive transistor is always off (not conducting current), as shown by a solid line, regardless of the data voltage, within a defined data voltage range. Since there is no current through the LED 126, the pixel will not emit any light.
Hence, this common dimming signal applied to the back gate 106 of the driving transistor 102 can switch the pixel on or off. If the display is switched on and off fast enough, the human eye will average the light intensity, and thus the apparent overall brightness of the display will be determined by the on-time (duty cycle, DC) of the PWM dimming signal. Typically, in very bright environments, the duty cycle (DC) will be larger, resulting in a brighter display.
During the controlling of the luminance level, the luminance level may be set by applying a selection signal SEL at the gate 116 of the control transistor 114 and applying a luminance level voltage as a DATA signal at the second terminal 118 of the control transistor 114, charging the capacitor 122 to that voltage. Thus, during the controlling, the luminance level is set by charging the capacitor 122 through the control transistor 114.
Typically, a different luminance signal is applied at each different pixel comprised in the dimming area.
The dimming of the dimming area and the controlling of the luminance level of the pixel may be coinciding or disjunct in time, as will be exemplified below.
Although the approach exemplified here, with an analog data voltage and a digital dimming (BG) signal is mostly preferred, other implementations are possible and may be more suitable for some applications.
The data voltage can be implemented as either an analog signal or a digital signal. When it is implemented as an analog signal, the brightness of the pixel is determined by the analog gate voltage, whereas when it is implemented as a digital signal, the duty cycle will determine the (apparent) brightness of the pixel.
Similarly, the common dimming signal can be either digital or analog. When it is digital, the duty cycle will determine the common brightness setting of the dimming area, whereas an analog global dimming signal will control the V_T of all the pixels, to adjust the achievable current levels, and thus the global brightness setting. Any combination of digital and analog signals is possible.
For example, for an AMLED display, a digital data signal may be preferred, due to a color (wavelength) shift caused by changing the current through the LED. In this case the current through the LED is always the same, ensuring the correct color point remains. The apparent brightness of the pixel is then determined by the duty cycle of the digital data signal, resulting in different grey-levels, corresponding to the image content.
The common dimming signal can be a global analog signal, applied to the back gate of the drive transistor of every pixel circuit. Adjusting this common dimming signal, will shift the threshold voltage (V_T ) of the pixel-driving transistor in every pixel, and hence determines the current through the pixels, and thus the overall brightness of the display. Although this change in current will shift the wavelength of all LEDs, the same color point can be achieved by selecting the correct global dimming voltages, which can be different for red, green, and blue, to compensate for the wavelength shifts.
Fig. 3 shows a display backplane comprising a plurality of pixel circuits 100 as described above in conjunction with Fig. 1. Again, each pixel circuit 100 may, as shown, be connected to a respective LED 126.
The pixel circuits 100 may be arranged in a two-dimensional grid.
Further, the backplane may, as shown, comprise a plurality of data lines DATA₁, DATA₂... and a plurality of selection lines SEL₁, SEL₂...
Further, a display controller 300 may be connected to the backplane or be comprised in the same, and may comprise a plurality of data output lines DATA _i 302 connected to the respective data lines DATA ₁ 302a, DATA ₂ 302b... of the backplane, and a plurality of selection output lines SEL _j 304 connected to the respective selection lines SEL ₁ 304a, SEL ₂ 304b ... of the backplane.
In the depicted example, with the whole display comprising a single dimming area, the display controller 300 comprises a dimming output line BG 306 connected to each pixel circuit 100 of the backplane.
Alternatively, the display may comprise a plurality of dimming areas. In that case, the display controller 300 may comprise a plurality of dimming output lines 306, each corresponding to a different dimming area and each connected to the second gates of the pixel-driving transistors of each of the pixel circuits 100 comprised in that dimming area.
As shown in Fig. 3, in the backplane, each respective data line 302 DATA ₁ 302a, DATA ₂ 302b may be connected to the pixel circuits 100 along a first dimension of the backplane, for example, as shown, forming vertical columns in the display backplane. Each data line may be connected to the second terminal 118 of the respective control transistor of the respective pixel circuit 100.
Further, each respective selection line 304 SEL ₁ 304a, SEL ₂ 304b may be connected to the pixel circuits 100 along a second dimension of the backplane, for example, as shown, forming horizontal lines in the display backplane. Each selection line may be connected to the gate 116 of the respective control transistor of the respective pixel circuit 100.
During controlling of the luminance level for each pixel circuit 100, according to the first method example above, the display controller may successively scan each horizontal line by successively putting a digital signal in a "high" state on each selection line 304 SEL ₁ 304a, SEL ₂ 304b..., while simultaneously putting a digital signal in a "low" state on each other selection line. Simultaneously, the display controller puts respective analog voltages on each data line DATA ₁ 302a, DATA ₂ 302b... for setting the luminance of each respective pixel in the selected line.
Thus, during the controlling according to the first method example, the luminance level of a pixel is set by addressing the control transistor 114 on a control line, i.e., a selection line 304 SEL ₁ 304a, SEL ₂ 304b... and the analog voltage is set through a data line 302 DATA ₁ 302a, DATA ₂ 302b.
Fig. 5 shows a timing diagram 500 according to which the controlling of the luminance levels of the pixels and the dimming may be performed in a display comprising the backplane of Fig. 3.
As shown, during the displaying of an image frame 502, the controlling of the luminance levels of the pixels, may be performed in a controlling phase 504, and the dimming performed in a dimming phase 506, where the controlling phase 504 and the dimming phase 506 are disjunct, i.e., non-coincident in time.
In the controlling phase 504, each selection line SEL₁, SEL₂, is, in succession, put "high" by the display controller 300, as described above in conjunction with Fig. 3, while the other selection lines are kept in a "low" state, while each data line carries analog luminance levels for each pixel in the line selected by the respective selection line.
Meanwhile, still in the controlling phase 504 the dimming signal BG, may, as shown, be kept constant, either in a "high" state or in a "low" state.
Then, in the subsequent dimming phase 506, dimming may be performed by pulse-width modulating the dimming signal BG, while each luminance signal is held constant by the corresponding capacitor 122 of each pixel circuit 100.
Thus, the method example is carried out according to a timing scheme, wherein the controlling of the luminance signal is carried out in the controlling phase 504, while the dimming signal BG is held constant, and the dimming is performed in the dimming phase 506, not coinciding with the controlling phase 504, where each luminance signal is held constant.
The scheme may then re-start for the next frame 502, as seen at the right edge of Fig. 5.
Thus, the scheme according to the example of Fig. 5 may be summarized as follows. The image frame 502 is split in two portions, one, the controlling phase 504 for scanning of the data to display the image, thus comprising a data-scanning subframe, and one, the dimming phase 506 to apply a common, i.e., global, PWM-modulated dimming signal BG. During data scanning in the controlling phase 504, the dimming signal BG is always kept at a constant voltage while the data is programmed on each pixel. Conversely, during the application of the PWM dimming signal onto the display's BG node during the second part of the frame, i.e., the dimming phase 506, no data is written.
As noted above, in the controlling phase 504 the dimming signal BG, may be kept constant either in a "high" state or in a "low" state. This holding of the dimming signal either "high" or "low" may be decided depending on the desired overall brightness level of the dimming area, as will be explained in the following.
In a first case, the desired overall brightness level corresponds to an overall PWM duty cycle of 50%, or less. In this case, the dimming signal BG is held "low", or at zero, during the controlling phase 504, while, during the dimming phase 506, a PWM dimming signal is applied as the dimming signal BG. The PWM dimming signal may have a PWM duty cycle between 0% and 100% measured over the dimming cycle, corresponding, due to the dimming signal being held "low", or at zero, during the controlling phase 504, if the controlling phase 504 and the dimming phase 506 are of equal length, to an overall duty cycle in the range 0% to 50%.
In a second case, the desired overall brightness level corresponds to an overall PWM duty cycle of 50%, or more. In this case, the dimming signal BG is held "high", or at one, during the controlling phase 504, while, during the dimming phase 506, a PWM dimming signal is applied as the dimming signal BG. The PWM dimming signal may have a PWM duty cycle between 0% and 100% measured over the dimming cycle, corresponding, due to the dimming signal being held "high", or at one, during the controlling phase 504, if the controlling phase 504 and the dimming phase 506 are of equal length, to an overall duty in the range 50% to 100%.
Fig. 6 schematically shows a display 600 having a first dimming area 602a and a second dimming area 602b. Just as described above in conjunction with Fig. 3, the backplane of the display 600 comprises a plurality of data lines DATA₁, DATA₂, ..., DATA_M, for example, as shown in Fig. 6, corresponding to vertical columns of the display 600.
Further, again as in Fig. 3, the display 600 comprises a plurality of selection lines. In the example of Fig. 6, selection lines SEL₁, SEL₂, ... , SEL_N/2 correspond to pixels in the first dimming area 602a and selection lines SEL_N/2+1, SEL_N/2+2,. ..., SEL_N correspond to pixels in the second dimming area 602b.
At the intersection of each data line and selection line, a pixel circuit 100 (not shown, cf. Fig. 1) is located (cf. Fig. 3).
Dimming in the first dimming area 602a is controlled by a first dimming signal BG₁ connected to the respective second gates 106 of the pixel-driving transistors 102 (cf. Figs 1, 3) of the pixel circuits 100 comprised in the first dimming area 602a.
Dimming in the second dimming area 602b is controlled by a second dimming signal BG₂ connected to the respective second gates 106 of the pixel-driving transistors 102 (cf. Figs 1, 3) of the pixel circuits 100 comprised in the second dimming area 602b.
Fig. 7 shows a timing diagram 700 according to which the controlling and the dimming of the display 600, having two dimming areas 602a, 602b, may be performed.
As shown, during the displaying of an image frame 502, controlling and dimming may be performed in a first phase 704 and a second phase 706, where the first phase 704 and the second phase 706 are disjunct, i.e., non-coincident in time.
In the first phase 704, as was described above, each selection line of the first dimming area 602a SEL₁, SEL₂,..., SELx , SEL_N/2 is, in succession, put "high" by the display controller 300, while the other selection lines, in both dimming areas 602a, 602b are kept in a "low" state, while each data line carries analog luminance levels for each pixel in the line selected by the respective selection line.
Meanwhile, still in the first phase 704 the dimming signal BG₁ for the first dimming area 602a, may, as shown, be kept constant, either in a "high" state or in a "low" state. A choice between these two options may be made as described above in conjunction with Fig. 5 depending on a desired overall brightness of the first dimming area 602a.
Meanwhile, still in the first phase 704, dimming may be performed in the second dimming area 602b by pulse-width modulating the dimming signal BG₂, while each luminance signal in the second dimming area 602b is held constant by the corresponding capacitor 122 of each pixel circuit 100.
Thereafter, in the subsequent second phase 706, each selection line of the second dimming area SEL_N/2+1, SEL_N/2+2,..., SEL_N is, in succession, put "high" by the display controller 300, while the other selection lines, in both dimming areas 602a, 602b are kept in a "low" state, while each data line carries analog luminance levels for each pixel in the line selected by the respective selection line.
Meanwhile, still in the second phase 706 the dimming signal for the second dimming area BG₂, may, as shown, be kept constant, either in a "high" state or in a "low" state. A choice between these two options may be made as described above in conjunction with Fig. 5 depending on a desired overall brightness of the second dimming area 602b.
Meanwhile, still in the second phase 706, dimming may be performed in the first dimming area 602a by pulse-width modulating the dimming signal BG₁, while each luminance signal in the first dimming area 602a is held constant by the corresponding capacitor 122 of each pixel circuit 100.
Thus, controlling and dimming is performed according to the same timing scheme as described above in conjunction with Fig. 5, separately for the first dimming area 602a and the second dimming area 602b.
In particular, controlling of the luminance signals in the first dimming area 602a is carried out in the first phase 704, thus corresponding to a controlling phase for the first dimming area 602a, while the dimming signal BG₁ for the first dimming area 602a is held constant, while the dimming in the first dimming area 602a is performed in the second phase 706, thus corresponding to a dimming phase for the first dimming area 602a and not coinciding with the first phase 704, where each luminance signal is held constant.
Conversely, controlling of the luminance signals in the second dimming area 602b is carried out in the second phase 706, thus corresponding to a controlling phase for the second dimming area 602b, while the dimming signal BG₂ for the second dimming area 602b is held constant, while the dimming in the second dimming area 602b is performed in the first phase 704, thus corresponding to a dimming phase for the second dimming area 602b and not coinciding with the second phase 706, where each luminance signal is held constant.
Thus, in the example of Figs 6 and 7, the display 600 is divided into two sections, i.e., the first dimming area 602a and the second dimming area 602b, which may correspond to the top half and the bottom half of the display 600.
Since the data in the first dimming area 602a, is written only during the first phase 704, the dimming signal in this dimming area, BG₁, may be switched, such as pulse-width modulated, during the second phase 706.
Since the data in the second dimming area 602b, is written only during the second phase 706, the dimming signal in this dimming area, BG₂, may be switched, such as pulse-width modulated, during the first phase 704.
Fig. 2 shows a schematic of a second pixel circuit 200, comprising a first pixel-driving transistor 102 and a second pixel-driving transistor 202, connected in parallel. Thus, compared to the pixel circuit 100 described above in conjunction with Fig. 1, the second pixel circuit 200 comprises an additional pixel-driving transistor 202.
As shown in Fig. 2, the second pixel-driving transistor 202 may, just like the first pixel-driving transistor 102, at a first terminal 108, which may be a source terminal or a drain terminal, be connected to the second terminal of the LED 126. At a second terminal 110, which may be a drain terminal if the first terminal 108 is a source terminal, or a source terminal if the first terminal 108 is a drain terminal, the second pixel-driving transistor may be connected to ground 112.
Further, the second pixel-driving transistor 202 may, just like the first pixel-driving transistor, comprise two further terminals in the in the form of a first gate 104, which, as shown, may be front gate of the pixel-driving transistor 202, and a second gate 206b, which, as shown, may be, respectively, a back gate of the pixel-driving transistor.
Alternative to what is shown in Fig. 2, the roles of the first gate and the second gate of the second pixel-driving transistor may, relative to what will be described in the following, be reversed, so that the first gate is the back gate of the second pixel-driving transistor 202 and the second gate is the front gate of the second pixel-driving transistor 202.
This arrangement allows the first pixel-driving transistor 102 and the second pixel-driving transistor 202 to have different characteristics. For example, the first pixel-driving transistor 102 and the second pixel driving transistor 202 may have different W/L ratios and hence produce a different current through the LED 126 for the same front gate voltage and back gate voltage.
Further to what is shown in Fig. 2, there may be a third pixel-driving transistor, a fourth pixel-driving transistor, and so on, each connected just like the first pixel-driving transistor 102 and the second pixel-driving transistor 202.
Thus, there may be a plurality of pixel-driving transistors in the pixel circuit 200, which may each have different characteristics, such as different W/L.
Just as described above for the pixel circuit 100 of Fig. 1, the pixel circuit 200 of Fig. 2 may belong to a dimming area. Thus, the dimming area comprises a plurality of pixels, each having a pixel circuit 200 according to Fig. 2.
Still with reference to Fig. 2, in a second method example, for driving the display, a dimming area may be dimmed by applying a first dimming signal BG₁ at the respective second gate 206a of the first pixel-driving transistor 102 at each pixel circuit 200 of each pixel comprised in the dimming area, and a second dimming signal BG₂ at the respective second gate 206b of the second pixel-driving transistor 202 at each pixel circuit 200 of each pixel comprised in the dimming area.
Generally, with a plurality of driving transistors in the pixel circuit, a dimming signal BG_i is applied at the ith driving transistor in each pixel circuit.
Each dimming signal BG_n, such as BG₁ and BG₂, is common in the sense the same dimming signal is applied at the respective second gate 106 at the respective driving transistor at each pixel in the dimming area. For example, each dimming signal may be a digital pulse-width modulated (PWM) signal.
Thus, multiple pixel-driving transistors 102, 202 may be used in parallel with different common dimming signals to select which of the drive transistors is used.
Each dimming signal may select which of the drive transistors are on. For example, when BG₁ is "high" and BG₂ is "low", only the first pixel-driving transistor 102 will be on, so the overall brightness of the display in the dimming area will be determined by the W/L ratio of the first pixel-driving transistor 102. When BG₁ is "low" and BG₂ is "high", only the second pixel-driving transistor 202 will be on, thus the overall brightness of the display in the dimming area will be determined by the W/L ratio of the second pixel-driving transistor 202. When both BG₁ and BG₂ are "high", both pixel-driving transistors 102, 202 will be on, so that overall brightness of the display in the dimming area will be determined by the sum of the W/L ratio of the first pixel-driving transistor 102 and the W/L ratio of the second pixel-driving transistor 202. Hence, this allows for three different overall brightness settings in the dimming area. This principle may be generalized to more than two pixel-driving transistors, and thus to more than three different overall brightness settings.
Moreover, the luminance level of the pixel connected, i.e., associated with, a pixel circuit 200 comprised in the dimming area may be controlled by applying a luminance signal at the first gate 104 of each pixel-driving transistor of the pixel circuit 200, such as, in the example of Fig. 2, the first pixel-driving transistor 102 and the second pixel-driving transistor 202.
The luminance signal may, for example, be an analog voltage.
During the controlling, the luminance level may be set by applying a selection signal SEL at the gate 116 of the control transistor 114 and applying a luminance level voltage as a DATA signal at the second terminal 118 of the control transistor 114, charging the capacitor 122 to that voltage. Thus, during the controlling, the luminance level is set by charging the capacitor 122 through the control transistor 114.
Typically, a different luminance signal is applied at each different pixel circuit comprised in the dimming area.
The dimming of the dimming area and the controlling of the luminance level of the pixel may be coinciding or disjunct in time, as will be exemplified below.
Fig. 4 shows a display backplane comprising a plurality of pixel circuits 200 as described above in conjunction with Fig. 2. Each pixel circuit 200 may, as shown, be connected to a respective LED 126.
The pixel circuits 200 may be arranged in a two-dimensional grid.
Further, the backplane may, as shown, comprise a plurality of data lines DATA₁, DATA₂... and a plurality of selection lines SEL₁, SEL₂...
Further, a display controller 300 may be connected to the backplane or be comprised in the same, and may comprise a plurality of data output lines DATA _i 302 connected to the respective data lines DATA ₁ 302a, DATA ₂ 302b... of the backplane, a plurality of selection output lines SEL _j 304 connected to the respective selection lines SEL ₁ 304a, SEL ₂ 304b ... of the backplane.
Further, the display controller 300 comprises a first dimming output line BG ₁ 306a and a second dimming output line BG ₂ 306b, each connected to each pixel circuit 200 of the backplane, the display in the depicted case comprising only one dimming area.
Alternatively, the display may comprise a plurality of dimming areas. In that case, the display controller may comprise a plurality of sets of dimming output lines 306, each set of dimming output lines corresponding to a different dimming area and each dimming line of a set of dimming lines connected to the display circuits 200 comprised in the corresponding dimming area.
As shown in Fig. 4, in the backplane, each respective data line 302 DATA ₁ 302a, DATA ₂ 302b may be connected to the pixel circuits 200 along a first dimension of the backplane, for example, as shown, forming vertical columns in the display backplane. Each data line may be connected to the second terminal 118 of the respective control transistor of the respective pixel circuit 200.
Further, each respective selection line 304 SEL ₁ 304a, SEL ₂ 304b may be connected to the pixel circuits 200 along a second dimension of the backplane, for example, as shown, forming horizontal lines in the display backplane. Each selection line may be connected to the gate 116 of the respective control transistor of the respective pixel circuit 200.
During controlling according to the second method example above, the display controller may successively scan each horizontal line by successively putting a digital signal in a "high" state on each selection line 304 SEL ₁ 304a, SEL ₂ 304b..., which simultaneously putting a digital signal in a "low" state on each other selection line. Simultaneously, the display controller puts respective analog voltages on each data line DATA ₁ 302a, DATA ₂ 302b... for setting the luminance of each respective pixel in the selected line.
Thus, during the controlling according to the first method example, the luminance level of a pixel is set by addressing the control transistor 114 on a control line, i.e., a selection line 304 SEL ₁ 304a, SEL ₂ 304b... and the analog voltage is set through a data line DATA ₁ 302a, DATA ₂ 302b.
In the above the inventive concept has mainly been described with reference to a limited number of examples. However, as is readily appreciated by a person skilled in the art, other examples than the ones disclosed above are equally possible within the scope of the inventive concept, as defined by the appended claims.
For example, the back gate and (front)gate of the pixel-driving transistors can be interchanged while staying within the concept of this invention. Furthermore, the principle of this invention was explained for a simple 2T1C pixel circuit, but can easily be applied to different pixel circuits. Moreover, the implementation of Figs 2 and 4, with multiple pixel-driving transistors in parallel, is not limited to two drive transistors in parallel, but can be elaborated to any number of drive transistors in parallel.
Further, embodiments were described throughout this disclosure using n-type transistor. The described embodiments are equally valid for p-type transistors, provided that the ground 112 and supply voltage 124 are swapped.

Claims

A method of driving a display (600), said display (600) comprising an active matrix comprising a plurality of pixel circuits (100; 200), each pixel circuit (100; 200) of said plurality of pixel circuits comprising a pixel-driving transistor (102, 202), each said pixel-driving transistor (102, 202) comprising a first gate (104) and a second gate (106, 206), said method comprising:
dimming a dimming area (602a, 602b) of said display (600) by applying a common dimming signal at the respective second gate (106, 206) of each pixel-driving transistor (102, 202) of the pixel circuits (100; 200) comprised in said dimming area (602a, 602b); and

controlling a luminance level of a pixel connected to a said pixel circuit comprised in said dimming area (602a, 602b) by applying a luminance signal at the first gate (104) of the pixel-driving transistor (102, 202) of said pixel circuit (100; 200).
The method of claim 1, wherein each said second gate (106, 206) is a back gate of the respective pixel-driving transistor.
The method of any one of claims 1-2, wherein each said first gate (104) is a front gate of the respective pixel-driving transistor (102; 202).
The method of claim 1, wherein one of said first gate (104) and said second gate (106) is a front gate of the respective pixel-driving transistor and the other of said first gate (104) and said second gate (106) is a back gate of said pixel-driving transistor.
The method of any one of claims 1-4, wherein said luminance signal is an analog voltage.
The method of any one of claims 1-5, wherein said dimming signal is pulse-width modulated, PWM.
The method of any one of claims 1-6, carried out according to a timing scheme, wherein:
said controlling is performed in a controlling phase (504; 704, 706), wherein said dimming signal is held constant during said controlling phase; and

said dimming is performed in a dimming phase (506; 706, 704) not coinciding with said controlling phase, wherein said luminance signal is held constant during said dimming phase.
The method of claim 7, wherein, during said controlling phase (504; 704, 706), depending on a desired overall brightness level of said dimming area, said dimming signal is either held high, or low.
The method of any one of claims 7-8, wherein said dimming area (602a) is a first dimming area, said method further comprising:
dimming and controlling a second dimming area (602b) according to said timing scheme, wherein a dimming phase (704) of said second dimming area (602b) at least partially does not coincide with said dimming phase (706) of the timing scheme of said first dimming area (602a).
The method of any one of claims 1-9, each said pixel circuit (200) comprising a second pixel-driving transistor (202), said dimming further comprising:
applying a second common dimming signal at each respective second gate (206b) of the second pixel-driving transistor (202) comprised in each pixel circuit (200) comprised in said dimming area (602a, 602b).
The method of any one of claims 1-10, wherein said pixel circuit (100; 200) comprised in said dimming area (602a, 602b) further comprises a control transistor (114) and a capacitor (122), wherein, during said controlling, said luminance level is set by charging said capacitor (122) through said control transistor (114).
The method of any one of claims 1-11, wherein, during said controlling, said luminance level of said pixel is set by addressing said control transistor (114) on one or more control lines (304, 304a, 304b) and said analog voltage is set through a data line (302, 302a, 302b).
The method of any one of claims 1-12, wherein said display (600) is an OLED, LED, QLED, µLED, or PeLED display and/or said driving transistor (102, 202) is a TFT or a MOSFET.
An active-matrix display backplane comprising said active matrix and configured to carry out the method of any one of claims 1-13.
A display (600) comprising the backplane of claim 14.