Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
  • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
  • H01L21/76—Making of isolation regions between components
  • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
  • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
  • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
  • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
  • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
  • H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
  • H01L21/3043—Making grooves, e.g. cutting
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
  • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
  • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
  • H01L21/7806—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices involving the separation of the active layers from a substrate

Definitions

• TITLE PROCESS FOR TRANSFERRING A USEFUL LAYER ON A
• the present invention relates to the field of microelectronics. It relates in particular to a method of transferring a useful layer onto a support substrate.
• a method of transferring a useful layer 3 onto a support substrate 4, shown in FIG. 1, is known from the state of the art; this process described in particular in documents WO2005043615 and WO2005043616 and designated by the name “Smart Cut TM” comprises the following steps:
• the species implanted at the level of the buried fragile plane 2 are at the origin of the development of microcavities.
• the thermal embrittlement treatment has the effect of promoting the growth and pressurization of these microcavities.
• additional external forces energy pulse
• the initiation of a fracture wave in the buried fragile plane 2 is operated, which wave propagates in a self-sustaining manner, leading the transfer of the useful layer 3 by detachment at the level of the buried fragile plane 2.
• This process can be used for the manufacture of silicon on insulator substrates (SOI - “Silicon on insulator”).
• the donor substrate 1 and the support substrate 4 are each formed from a silicon wafer, the standardized diameter of which is typically 200mm, 300mm, or even 450 mm for the next generations.
• One and / or the other of the donor substrate 1 and of the support substrate 4 are oxidized at the surface.
• SOI substrates must meet very precise specifications. This is particularly the case for the average thickness and the uniformity of thickness of the useful layer 3. Compliance with these specifications is required for the proper functioning of the semiconductor devices which will be formed in and on this useful layer 3. .
• the architecture of these semiconductor devices requires the availability of SOI substrates having a very low average thickness of the useful layer 3, for example less than 50 nm, and having very good uniformity of thickness of the layer. useful 3.
• the expected thickness uniformity can be of the order of 5% at most, corresponding to variations typically ranging from +/- 0.3nm to +/- lnm over the entire surface of the useful layer 3.
• additional finishing steps such as etching or heat treatments for surface smoothing, are carried out after the useful layer 3 is transferred to the support substrate 4, it is important that the surface morphological properties (in particular, thickness uniformity and surface roughness) are as favorable as possible after transfer, to ensure that specifications are maintained finals.
• certain useful layers 3 may comprise, after transfer, irregular patterns of the marbling type resulting in local variations in thickness, the amplitude of which is of the order of one nm or half a nanometer. These mottles can be distributed over the whole of the useful layer 3, or over only a part. They contribute to the non-uniformity of the useful layer 3.
• This type of non-uniformity of thickness of the useful layer 3 is very difficult to eliminate by the usual finishing techniques (etching, sacrificial oxidation, heat treatment of smoothing) because the latter are not effective in erasing irregular patterns of this. amplitude.
• the present invention relates to a method of transferring a useful layer onto a support substrate and aims in particular to improve the uniformity of thickness of the useful layers transferred.
• the invention relates to a method of transferring a useful layer onto a support substrate, comprising the following steps:
• a donor substrate comprising a buried fragile plane, the useful layer being delimited by a front face of the donor substrate and the buried fragile plane;
• step e) is carried out when the bonded structure undergoes a thermal gradient defining a hot region and a cold region of said bonded structure, the stress being locally exerted in the cold region. , and the hot region experiencing a temperature below the maximum plateau temperature.
• the thermal gradient is chosen between 20 ° C and 100 ° C, preferably between 60 ° C and 90 ° C, more preferably around 80 ° C; • the maximum bearing temperature is between 300 ° C and 600 ° C;
• step d) is carried out in heat treatment equipment and the initiation of step e) is carried out when the bonded structure leaves said heat treatment equipment;
• the heat treatment equipment is a furnace of horizontal or vertical configuration, suitable for the collective treatment of a plurality of bonded structures
• step e • the initiation of step e) is carried out when the hot region of the bonded structure undergoes a temperature of between 150 ° C and 250 ° C;
• the thermal budget for embrittlement is between 40% and 95% of a thermal budget for fracture, the thermal budget for fracture being that which leads to a spontaneous initiation of the fracture wave in the brittle plane buried during annealing ;
• the donor substrate and the support substrate are made of monocrystalline silicon, and in which the plane buried fragile is formed by ion implantation of light species in the donor substrate, said light species being chosen from hydrogen and helium or a combination of hydrogen and helium.
• FIG. 1 shows a method of transferring a thin film according to the state of the art
• FIG. 2 presents a transfer method according to the invention
• FIGS. 3a and 3b show “haze” maps on the surface of useful layers comprising non-uniformities of thickness after transfer;
• FIG. 4 shows a “haze” map on the surface of a useful layer transferred by a transfer method according to the invention
• FIG. 5 shows a step of a transfer method according to the invention
• FIG. 6 presents a graph showing the evolution of the temperatures and of the thermal gradient seen by a bonded structure in a step of a transfer process according to the invention
• FIG. 7 shows a step of a transfer method according to the invention.
• the invention relates to a method of transferring a useful layer 3 onto a support substrate 4.
• the useful layer 3 is so named because it is intended to be used for the manufacture of components in the fields of microelectronics or microsystems.
• the useful layer and the support substrate can be of various types depending on the type of component and the intended application. Since silicon is the semiconductor material most used at present, the useful layer and the support substrate can in particular be made of monocrystalline silicon but are of course not limited to this material.
• the transfer method according to the invention first of all comprises a step a) of supplying a donor substrate 1, from which the useful layer 3 will be obtained.
• the donor substrate 1 comprises a buried fragile plane 2 (FIG. 2 - a). ).
• the latter is advantageously formed by ion implantation of light species in the donor substrate 1, at a defined depth.
• the light species are preferably chosen from hydrogen and helium, or a combination of hydrogen and helium, because these species are favorable to the formation of microcavities around the defined depth of implantation, giving rise to the buried fragile plane 2.
• the useful layer 3 is delimited by a front face of the donor substrate 1 and the buried fragile plane 2.
• the donor substrate 1 can be formed by at least one material chosen from among silicon, germanium, silicon carbide, compound semiconductors IV-IV, III-V or II-VI, piezoelectric materials (for example, LiNb03 , LiTa03, ...), etc. It may also include one or more surface layer (s) arranged on its front face 1a and / or on its rear face 1b, of all kinds, for example dielectric (s).
• the transfer process also comprises a step b) of providing a support substrate 4 (FIG. 2 - b)).
• the support substrate can for example be formed by at least one material chosen from among silicon, silicon carbide, glass, sapphire, aluminum nitride, or any other material capable of being available in the form of a substrate. It can also include one or more surface layer (s) of all types, for example dielectric (s).
• the transfer method according to the invention is the manufacture of SOI substrates.
• the donor substrate 1 and the support substrate 4 are made of monocrystalline silicon, and one and / or the other of said substrates comprises a surface layer of silicon oxide 6 on its front face.
• the transfer method then comprises a step c) of assembly, using a bonding interface 7, of the donor substrate 1, at its front face 1a, and of the support substrate 4, to form a bonded structure 5 (FIG. 2 - c )).
• the assembly can be carried out by any known method, in particular by direct bonding by molecular adhesion, by thermocompression, by electrostatic bonding, etc. These techniques, which are well known from the state of the art, will not be described in detail here. It is nevertheless recalled that, prior to assembly, the donor 1 and support 4 substrates will have undergone cleaning and / or surface activation sequences, so as to guarantee the quality of the bonding interface 7 in terms of defectivity. and bonding energy.
• a step d) of annealing the bonded structure 5 is then carried out, to apply to said structure 5 a thermal embrittlement budget and bring the buried fragile plane to a defined level of embrittlement. (figure 2 - d)).
• the time / temperature pairs applied during annealing determine the thermal budget undergone by the bonded structure 5.
• the temperature range in which the annealing can be operated for this embrittlement of the buried plane 2 depends essentially on the type of bonded structure 5 (homo-structure or hetero-structure) and on the nature of the donor substrate 1.
• the annealing of step d) reaches a maximum plateau temperature typically between 200 ° C and 600 ° C, advantageously between 300 and 500 ° C, and even more advantageously between 350 ° C and 450 ° C.
• the maximum plateau temperature may more generally, for materials used for the donor substrate 1 and / or for the support substrate 4 other than silicon, typically be between 200 ° C and 800 ° C.
• Annealing may include a temperature rise ramp (typically between 200 ° C. and the maximum plateau temperature) and a plateau at the maximum temperature. In general, such an annealing will have a duration of between a few tens of minutes and several hours, depending on the maximum annealing bearing temperature.
• the level of embrittlement of the buried brittle plane 2 is defined by the surface occupied by the microcavities present in the buried brittle plane 2.
• the characterization of this surface occupied by the microcavities can be perform by infrared microscopy.
• the level of embrittlement can increase from a low level ( ⁇ 1%, below the detection threshold of the characterization instruments) to more than 80%, depending on the thermal budget applied to the bonded structure 5 during annealing.
• the thermal embrittlement budget is always kept below a thermal fracture budget, for which the spontaneous initiation of the fracture wave in the buried fragile plane 2 is obtained during annealing.
• the thermal budget for embrittlement is between 40% and 95% of the thermal budget for fracture.
• the heat treatment equipment 20 in which the annealing of step d) is carried out is preferably a furnace of horizontal or vertical configuration, suitable for the collective treatment of a plurality of bonded structures 5.
• a step e) of initiation of a fracture wave along the buried fragile plane 2 is then carried out, by applying a stress to the bonded structure 5 (figure 2 - d )).
• the fracture wave propagates in a self-sustaining manner, leading to the separation of the bonded structure 5 at the level of the buried fragile plane 2.
• a self-sustaining propagation reflects the fact that once initiated, the wave of fracture propagates by itself, without the application of external stress and over the entire extent of the buried fragile plane 2, so as to detach completely the useful layer 3 of the donor substrate 1 and to transfer it to the support substrate 4.
• the stress is local and applied to the periphery of the bonded structure 5. It may be of mechanical origin or of any other origin such as for example localized heating carried out by a laser or an input of energy by ultrasound.
• a local mechanical stress can be produced by inserting a bevel, facing the bonding interface 7 of the bonded structure 5, between chamfered edges respectively of the donor substrate 1 and of the support substrate 4 of said bonded structure 5. This has the effect of generating a tensile stress in the buried fragile plane 2.
• the transfer method provides that the initiation of the fracture wave in step e) is performed by application of 'a stress external to the buried brittle plane 2 while the bonded structure 5 undergoes a thermal gradient defining a hot region and a cold region of said bonded structure 5.
• the external stress is locally exerted in the cold region of the bonded structure 5.
• the maximum temperature seen by the hot region is always lower than the maximum plateau temperature annealing.
• the choice is made to initiate step e) when the bonded structure 5 undergoes a thermal gradient greater than 20 ° C and less than 100 ° C, in particular between 60 ° C and 90 ° C, preferably of the order of 80 ° C.
• This particular configuration makes it possible to limit the variations in thickness of the useful layer 3, which may appear in the form of regular or irregular patterns of amplitude of the order of one nm or half a nanometer.
• the applicant has identified that the non-uniformities of thickness caused by the propagation of the fracture wave can have two distinct origins: on the one hand, an excess of energy released at the start of propagation (creating patterns regular steps of about 1cm), on the other hand, a lack of energy released at the end of propagation creating an instability of the fracture (causing an irregular pattern).
• the energy released by the fracture is directly proportional to the temperature of the material in which it propagates. Thus, if one initiates in the hot region of the bonded structure 5, the fracture will first release a lot of energy (which is unfavorable in terms of regular patterns) then will release less energy at the end of propagation. (which is unfavorable in terms of irregular patterns).
• FIGS. 3a and 3b show “haze” maps of useful layers 3 after a fracture, respectively spontaneous occurring during annealing, and mechanical initiated at room temperature after an embrittlement annealing. Note that the initiation of the aforementioned mechanical fracture was made by local mechanical stress exerted on the bonded structure 5 and generating a stress in the buried brittle plane 2. We notice, in each case, patterns (regular or irregular) which degrade the uniformity of thickness of useful layer 3 after transfer (between 0.5 and 1.5 nm in amplitude).
• FIG. 4 shows a “haze” map on the surface of a useful layer 3 transferred by a transfer method in accordance with the invention: in this case, after a fracture initiated while the bonded structure 5 undergoes a thermal gradient d 'approximately 80 ° C, by a local mechanical stress exerted in the cold region of the bonded structure 5 generating a stress in the buried fragile plane 2. No pattern, neither regular nor irregular of the marbling type is present, the non- local uniformity of the haze signal does not exceed 2%. The uniformity of thickness of the useful layer 3 is thus greatly improved.
• a fracture wave initiated in the cold region of the bonded structure 5 when a thermal gradient greater than 20 ° C and less than 100 ° C applies to said structure 5, leads to good thickness uniformity of the useful layer 3 after transfer.
• the bonded structure 5 can be located in the heat treatment equipment 20 (as illustrated in FIG. 2 - d)) or outside said equipment 20 (FIG. 7), when the initiation of the fracture wave of step e) is carried out.
• the initiation of the fracture wave is carried out when the bonded structure 5 leaves the heat treatment equipment 20 in which the annealing of step d) has been carried out: a gradient thermal exists in general on the bonded structure 5 when it leaves said equipment (FIGS. 5 and 6). This gradient is generally due to the geometry of the furnace 20 and to the presence of a system for maintaining the bonded structures 5, which influence the heat dissipation.
• the initiation of step e) is carried out at the outlet of the heat treatment equipment 20 when the hot region (or typically the hottest point) of the bonded structure 5 is at a temperature of between 150 ° C and 250 ° C, preferably around 200 ° C.
• the energy stored in the system bonded structure 5 + buried fragile plane 2
• the energy stored in the buried fragile plane 2 due to the presence of gaseous species under pressure in the microcavities is suitable for efficient self-sustaining propagation, further improving the surface condition of the useful layer 3 after transfer.
• the transfer method according to the invention can be used for the manufacture of SOI substrates in which the useful layer 3 is very thin, in particular between a few nanometers and 50 nm.
• donor 1 and support 4 substrates in monocrystalline silicon each in the form of a wafer 300 mm in diameter.
• the donor substrate is covered with a layer of silicon oxide 6 50 nm thick.
• the buried fragile plane 2 is formed in the donor substrate 1 by co-implantation of hydrogen and helium ions under the following conditions:
• H implantation energy 38 keV, dose 1E16 H / cm2,
• He implantation energy 25 keV, dose 1E16 He / cm2.
• the buried fragile plane 2 is located at a depth of approximately 290 nm, from the surface 1a of the donor substrate 1. It delimits, with the oxide layer 6, a useful layer 3 of approximately 240 nm.
• the assembly of the donor substrate 1 and the support substrate 4 is made by direct bonding by molecular adhesion, to form the bonded structure 5.
• the donor 1 and support 4 substrates Prior to assembly, will have undergone cleaning and / or sequences. known surface activation, so as to guarantee the quality of the bonding interface 7 in terms of defectivity and bonding energy.
• a furnace 20 of horizontal configuration is used to collectively perform the annealing of a plurality of bonded structures such as that described above.
• This type of heat treatment equipment 20 comprises a loading shovel 21 which supports nacelles 22 in which the bonded structures 5 are positioned (FIG. 7).
• the loading shovel 21 moves between a retracted position, in which the bonded structures 5 are inside the oven 20, and an extended position, in which they are outside the oven 20.
• a system of bevels 10 can be positioned on each nacelle 22, below the bonded structures 5.
• the loading shovel 21 moves in the retracted position for carrying out the annealing.
• the annealing includes a temperature rise ramp from 200 ° C to 380 ° C, a plateau at 380 ° C for 2 minutes and a temperature drop ramp down to 225 ° C.
• the loading shovel 21 moves to its extended position.
• each bonded structure 5 As illustrated in FIG. 6, from the moment when each bonded structure 5 leaves the oven 20, the temperature it undergoes decreases and a thermal gradient appears.
• the cold zone of the bonded structure 5 is located in a low region B, that is to say close to the nacelle 21 and the loading shovel 22.
• Each bonded structure 5 will pass through an exit zone 23 in which it undergoes a thermal gradient preferably between 60 ° C and 90 °, and in particular of the order of 80 ° C +/- 10 ° C, or even 80 ° C +/- 5 ° C.
• a support device 11 located above the bonded structures 5 will exert a supporting force successively on each bonded structure 5, so that the bevel 10 below the latter ( in the cold region) is inserted, facing the bonding interface 7, between the chamfered edges of the assembled substrates of the bonded structure 5 (FIG. 7).
• the insertion of the bevel 10 generates a local stress and in tension at the level of the buried fragile plane 2 making it possible to initiate the fracture wave in the cold region of each bonded structure 5, successively, as they pass under the support device 11.
• the initiation of the fracture wave is thus carried out for each bonded structure, in its cold region (lower region B) when it undergoes a thermal gradient of the order of 80 ° C (approximately 70 ° C in the example in figure 6).
• the exit zone 23 in which the initiation of the fracture wave is operated corresponds to a zone in which each bonded structure 5 undergoes, in its coldest region (lower region B ) a temperature of the order of 130 ° C, its central region C seeing an intermediate temperature of the order of 180 ° C and its high region H a temperature of the order of 200 ° C.
• the SOI substrate is obtained after transfer (transferred assembly 5a) and the remainder 5b of the donor substrate. A very good uniformity of thickness of the useful layers 3 transferred is obtained (similar to the result of FIG. 4).
• Finishing steps applied to the transferred assemblies 5a include chemical cleanings and at least one high temperature smoothing heat treatment.
• the SOI substrates comprise a useful layer 3 with a thickness of 50 nm, the final thickness non-uniformity of which is of the order of 0.45nm. It should be noted that, in comparison, SOI substrates in which the useful layer 3 comprises regular or irregular patterns after fracture, may have final thickness non-uniformities greater than or equal to 0.7 nm.

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• Engineering & Computer Science (AREA)
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• Condensed Matter Physics & Semiconductors (AREA)
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• 2019
  • 2019-03-15 FR FR1902674A patent/FR3093859B1/fr active Active
• 2020
  • 2020-02-24 TW TW109105911A patent/TWI824112B/zh active
  • 2020-02-26 JP JP2021555273A patent/JP7500911B2/ja active Active
  • 2020-02-26 EP EP20713948.6A patent/EP3939078A1/fr active Pending
  • 2020-02-26 WO PCT/FR2020/050369 patent/WO2020188169A1/fr active Application Filing
  • 2020-02-26 SG SG11202109921Q patent/SG11202109921QA/en unknown
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  • 2020-02-26 US US17/435,631 patent/US11876015B2/en active Active
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