EP3886179A1 - Diode empilée à semi-conducteur en ingaas à blocage haut - Google Patents

Diode empilée à semi-conducteur en ingaas à blocage haut Download PDF

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EP3886179A1
EP3886179A1 EP21000071.7A EP21000071A EP3886179A1 EP 3886179 A1 EP3886179 A1 EP 3886179A1 EP 21000071 A EP21000071 A EP 21000071A EP 3886179 A1 EP3886179 A1 EP 3886179A1
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Prior art keywords
semiconductor
layer
iii
power diode
contact region
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English (en)
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Thorsten Wierzkowski
Daniel Fuhrmann
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Azur Space Solar Power GmbH
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Azur Space Solar Power GmbH
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/8613—Mesa PN junction diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
    • H01L29/6609—Diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/201—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys
    • H01L29/205—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys in different semiconductor regions, e.g. heterojunctions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/36—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the concentration or distribution of impurities in the bulk material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
    • H01L29/66196—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices with an active layer made of a group 13/15 material
    • H01L29/66204—Diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/8611—Planar PN junction diodes

Definitions

  • the invention relates to a stacked high-blocking InGaAs power semiconductor diode.
  • GaAs Power Devices by German Ashkinazi, ISBN 965-7094-19-4, pages 8 and 9 a high-voltage-resistant PIN semiconductor diode made of GaAs is known.
  • Stacked high blocking InGaAs semiconductor power diodes and corresponding manufacturing processes are from the publications DE 10 2016 013 540 A1 , DE 10 2016 013 541 A1 , DE 10 2016 015 056 A1 , DE 10 2017 002 935 A1 and DE 10 2017 002 936 A1 known.
  • Generic diodes have breakdown voltages above 200V and should have a low forward voltage and a low series resistance in order to reduce the power loss. Furthermore, the diodes should have the lowest possible leakage currents of less than 1 ⁇ A in the reverse direction.
  • the semiconductor components are usually protected at the wafer level by passivation and / or protective layers.
  • III-V semiconductor components are, for example, from “ Passivation of GaAs in alcohol solutions of ammonium sulfide”, VN Bessolov et al., Semiconductors, Vol. 31, No. 11, pp. 1350-1356, ISSN 1063-7826, 1997 or from “ Ammonium sulfide passivation for AlGaAs / GaAs buried heterostructure laser fabrication process ", T. Tamanukl et al., Japanese Journal of Applied Physics, Part 1, Vol. 30, No. 3, pp.
  • trenches are typically etched in a first mesa process and then the area below the trenches is cut through by sawing.
  • the trenches are typically passivated further on.
  • Nanoimprint and selective-area MOVPE for growth of GaAs / InAs core / shell nanowires
  • F. Haas et al Nanotechnology, Vol. 24, No. 8, 085603, 2013
  • III / V nano ridge structures for optical applications on patterned 300 mm silicon substrate
  • B. Kunert et al. Appl. Phys. Lett. 109, 091101, 2016 described.
  • the object of the invention is to provide a device that develops the state of the art.
  • a stacked high-blocking III-V semiconductor power diode having a first highly doped semiconductor contact region of a first conductivity type with a dopant concentration of at least 1 • 10 18 cm -3 and with a first lattice constant.
  • the semiconductor drift area below the first semiconductor contact area there is a lightly doped semiconductor drift area of the first conductivity type or a second conductivity type with a dopant concentration of 8 • 10 11 - 1 • 10 15 cm -3 , the semiconductor drift area having the first lattice constant and a layer thickness between 10 ⁇ m - 200 ⁇ m .
  • a highly doped second semiconductor contact region of the second conductivity type with a dopant concentration of at least 5 ⁇ 10 17 cm -3 is arranged below the semiconductor drift region, the second semiconductor contact region having the first lattice constant or a second lattice constant.
  • a first metallic connection contact layer is formed at least in regions on an upper side of the first semiconductor contact region and is connected to the upper side of the first semiconductor contact region in a materially bonded manner.
  • a second metallic connection contact layer is formed at least in some areas below an underside of the second semiconductor contact area and is, for example, materially connected to the underside of the second semiconductor contact area or to a semiconductor layer, e.g. a substrate layer or a buffer layer, arranged between the second semiconductor contact area and the second metallic connection contact layer.
  • At least the first semiconductor contact region forms a core stack.
  • the core stack has a top and a bottom and a side surface extending from the top to the bottom.
  • the III-V semiconductor power diode has a dielectric frame region which surrounds the core stack along the side face and has a top side and a bottom side.
  • the top side of the core stack ends with the top side of the dielectric frame area or forms a first step with respect to the top side of the dielectric frame area.
  • the underside of the core stack ends with the underside of the dielectric frame area or forms a second step with respect to the underside of the dielectric frame area.
  • Semiconductor regions of the III-V semiconductor power diode arranged below the first semiconductor contact region are each either encompassed by the core stack or form a carrier region, the carrier region being arranged below the core stack and the frame region and having a common underside formed from the underside of the dielectric frame region and the Underside of the core stack, is firmly connected.
  • the III-V semiconductor power diode always has a core stack surrounded by the frame area, and a carrier area arranged therebelow is optional.
  • both the drift region and the second semiconductor contact region also form the core stack, so that the III-V semiconductor power diode either does not have a carrier region or has a carrier region formed from a further semiconductor layer, for example a substrate.
  • the drift region is formed as part of the core stack and the III-V semiconductor power diode has a carrier region formed at least from the second semiconductor contact region.
  • the core stack comprises only the first semiconductor contact region or possibly a further semiconductor intermediate layer, both the drift region and the second semiconductor contact region being formed in the carrier region.
  • the metallic connection contact layers are each very electrically conductive.
  • the metallic connection contact layers preferably consist of one or more metal layers, the metal layers preferably comprising Ge and / or Au and / or Pd and / or Ag.
  • the metallic connection contact layers produce an electrically low-resistance contact to the highly doped semiconductor contact areas.
  • a coverage of at least 70% or of at least 80% of the underside of the second semiconductor contact region is referred to as a full-area formation.
  • the second metallic connection contact layer is designed as points or limited surface sections or also in the shape of a finger.
  • the III-V semiconductor power diode has no carrier area and the second metallic connection contact layer is formed over the entire area on the underside of the III-V semiconductor power diode, ie the second metallic connection contact layer covers a common underside, formed from the underside of the core stack and the bottom of the frame area.
  • the metallic connection contact layers are preferably interconnected by means of bonding wires with contact fingers, the so-called pins, in that the semiconductor power diodes are arranged on a carrier, for example in the form of a leadframe.
  • semiconductor layer or “semiconductor contact layer” is preferably used synonymously with the expression “semiconductor region” or “semiconductor contact region” or “semiconductor contact” or “semiconductor contact region”.
  • all semiconductor regions of the power diode are preferably in the form of layers, in particular as planar layers, that is to say have a planar or essentially planar top and bottom.
  • first and / or the second semiconductor contact region are formed in a trough-shaped manner in an alternative embodiment. It is further understood that the trough-shaped regions preferably extend from an upper side of another planar semiconductor layer into this planar semiconductor layer.
  • a trough-shaped semiconductor contact region is preferably produced within a region of a layer-shaped drift region by introducing dopants into this region, the region preferably extending trough-shaped into the drift region.
  • a layered semiconductor contact region is produced in a drift region by implantation of dopants, e.g. a layer of a desired depth adjoining the top side of the drift region is converted into the semiconductor contact region by implantation.
  • All semiconductor layers of the power diode are preferably produced epitaxially, e.g. by means of MOVPE or by means of LPE or by means of CVD, or by implantation or diffusion.
  • one or more layers of the carrier area are connected to one another by means of a wafer bond.
  • III-V materials e.g. GaAs, In-GaP, InGaAs, AlGaAs or InP.
  • the high blocking III-V semiconductor diode additionally comprises semiconductor layers made of other semiconductor materials or additional layers made of other non-semiconductor materials.
  • III-V semiconductors in particular GaAs or InGaAs, provide particularly high charge carrier mobility.
  • a semiconductor region or a semiconductor layer consisting of a III-V material only has to consist essentially of III-V material or in addition to a III-V material, that is to say a material which has one or more elements the III. and / or V. main group, may optionally also contain impurities and / or dopants.
  • a layer comprising GaAs can thus be, for example, a GaAsP layer or AlGaAs layer.
  • the high-blocking III-V semiconductor diode can be designed with an n-on-p or a p-on-n structure.
  • the first conductivity type is n and the second conductivity type is p or vice versa.
  • the dielectric frame area consists of a dielectric material or a material having dielectric properties.
  • the dielectric frame area preferably consists of Si x O y , for example SiO 2 , or of Si x N y , for example SiN, or of Al x O y or of Ta x O y or of Ti x O y or of Hf x O y .
  • the frame area has Si x O y or Si x N y or Al x O y or Ta x O y or Ti x O y or Hf x O y .
  • the dielectric frame area is formed as an oxide, for example made of Comprising Al 2 O 3 or Ta 2 O 5 or TiO 2 or HfO 2 or a rare earth.
  • the dielectric frame area is preferably designed in a layered manner with a through opening receiving the core stack.
  • the common layer produced in this way has, for example, a flat common top side and / or a flat common bottom side.
  • the core stack protrudes beyond the top and / or the bottom of the dielectric frame area, so that a rising step is formed at the transition from the dielectric frame area to the core stack.
  • the top of the core stack does not extend to the top of the dielectric frame area, so that a descending step is formed at the transition from the top of the dielectric frame area to the top of the core stack.
  • the resulting common layer of frame area and core stack can also be arranged on a carrier area, so that a common underside (the underside of the common layer) formed by the underside of the frame and the underside of the core stack is materially connected to the upper side of the carrier area.
  • the outer side surface of the frame area preferably ends with the side surfaces of the carrier area, i.e. the diameter of the carrier area corresponds to the sum of the diameter of the core stack and twice the wall thickness of the frame area.
  • the frame area represents adequate protection or adequate passivation of the side surfaces or the pn junction, so that further passivation layers can be dispensed with. Leakage currents are reliably suppressed and a high breakdown voltage and efficiency are achieved.
  • One advantage is that the epitaxial deposition of the III-V semiconductor layers within the dielectric frame area prevents the formation of surface states that normally form on the semiconductor surface due to the oxygen in air and lead to reduced breakdown voltages and reduced device efficiency.
  • the pn junction remains protected in the frame area, so that penetration of moisture is prevented very reliably. Moisture in particular leads to higher leakage currents or low breakdown voltages, so that moisture penetration must be prevented, particularly in the case of high-barrier components.
  • the frame area enables the separate production of individual power diodes through selective growth. This enables the III-V semiconductor power diodes according to the invention to be singulated in a particularly simple manner simply by sawing.
  • III-V semiconductor power diodes With the III-V semiconductor power diodes, higher temperatures at the p / n junctions can be achieved compared to Si without the III-V semiconductor diodes being destroyed. III-V semiconductor diodes can be used at temperatures of up to 300 ° C, i.e. even in hot environments.
  • the III-V semiconductor power diode has an intermediate semiconductor layer of the first conductivity type with a dopant concentration of 8 ⁇ 10 12 -1 ⁇ 10 16 cm -3 between the first semiconductor contact region and the semiconductor drift region. It goes without saying that the intermediate semiconductor layer is formed as part of the core stack and / or as part of the carrier region.
  • the III-V semiconductor power diode alternatively or additionally, a semiconductor intermediate layer of the second conductivity type with a dopant concentration of 8 ⁇ 10 12 -1 ⁇ 10 16 cm -3 between the second semiconductor contact region and the semiconductor drift region. It goes without saying that the intermediate semiconductor layer is formed as part of the core stack and / or as part of the carrier region.
  • the III-V semiconductor power diode has a highly doped metamorphic buffer layer sequence, the metamorphic buffer layer sequence being arranged between the semiconductor drift region and the second semiconductor contact region, a dopant concentration greater than 5 ⁇ 10 17 cm -3 and a layer thickness above 0.5 ⁇ m and is smaller than 20 ⁇ m, is of the first conductivity type or the second conductivity type and has the first lattice constant on an upper side facing the semiconductor drift region and the second lattice constant on an underside facing the second semiconductor contact region and the second semiconductor contact region has the second lattice constant.
  • the buffer layer sequence is, for example, part of the core stack and / or part of the carrier area.
  • the buffer layer sequence or part of the buffer layer sequence is designed as a second semiconductor contact layer. That is, the buffer layer sequence fulfills both the function of lattice constant compensation between layers arranged above and below and the function of the second semiconductor contact layer or the corresponding layer which has both the features of the buffer layer sequence and the features of the second semiconductor contact layer.
  • the metamorphic buffer layer sequence has a sequence of at least three layers and, for example, a maximum of twenty layers.
  • the metamorphic buffer is preferably highly n-doped or highly p-doped.
  • the buffer layer sequence is formed from InGaAs, for example.
  • the metamorphic buffer layer sequence preferably has a dopant concentration greater than 5 ⁇ 10 17 cm -3 and a layer thickness above 0.5 ⁇ m and less than 20 ⁇ m.
  • the metamorphic buffer layer sequence consists of several In x Ga 1-x As layers with x that differs from layer to layer and / or remains the same.
  • the lattice constant changes at least once within the buffer.
  • the lattice constant increases, for example, from a lowermost layer of the sequence with the second lattice constant to the uppermost layer of the sequence with the first lattice constant from layer to layer.
  • the lattice constant first increases and then decreases from layer to layer or also decreases first and then increases.
  • the increase or decrease in the lattice constants over the entire sequence is either stepped or linear or in any other form.
  • the III-V semiconductor power diode has a substrate layer, the substrate layer being formed as part of the carrier region.
  • the substrate layer has either the first lattice constant or a second lattice constant.
  • the substrate layer is designed as a GaAs or Ge substrate, for example. In one development, the substrate forms the second semiconductor contact layer.
  • the semiconductor drift region and / or the first semiconductor contact region and / or the second semiconductor contact region consists of GaAs or InGaAs or the semiconductor drift region and / or the first Semiconductor contact region and / or the second semiconductor contact region comprise GaAs or InGaAs.
  • the first conductivity type is preferably p and the second conductivity type is n or the first conductivity type is n and the second conductivity type is p.
  • first semiconductor contact region and / or the second semiconductor contact region are embodied in the form of a trough.
  • the frame area is materially connected to the side surface of the core stack.
  • Another object of the invention is a production method for a stacked high-blocking III-V semiconductor power diode, a semiconductor carrier layer being provided.
  • a dielectric layer is deposited on a top side of the semiconductor carrier layer.
  • a mask layer with at least one through opening is then produced on an upper side of the dielectric layer.
  • the dielectric layer is removed in an etching step in the region of the at least one through opening of the mask layer, specifically up to the semiconductor carrier layer, so that the dielectric layer forms a dielectric frame region.
  • the mask layer is then removed.
  • one or more III-V semiconductor layers are deposited one after the other on the exposed top side of the semiconductor carrier layer and, in the metallization step, an at least regionally formed first metallic connection contact layer on a top side of a topmost deposited III-V semiconductor layer and a second metallic layer Connection contact layer applied below a lowermost deposited III-V semiconductor layer.
  • the production method is preferably carried out at the wafer level, that is to say a multiplicity of III-V semiconductor power diodes are produced next to one another in the manner of a matrix.
  • the components are then separated by sawing in the area of the dielectric frame area and, after the separation, have a side wall passivation.
  • the etching step e.g. a dry etching step or a wet chemical etching step, can be carried out with a high selectivity, which means that there is little or no selectivity
  • the semiconductor carrier layer that is to say the carrier region, is removed.
  • the recess in the dielectric layer is then at least partially or completely filled with one or more semiconductor layers, as a result of which a core stack of semiconductor layers enclosed by the frame region is formed on the semiconductor carrier layer.
  • the core stack comprises all semiconductor layers of the III-V semiconductor power diode, the III-V semiconductor power diode being more or less exposed by removing the entire semiconductor carrier layer.
  • the core stack comprises only part of the semiconductor layers of the III-V semiconductor power diode, in particular the first highly doped semiconductor contact region and possibly also the drift region, further layers, for example the second semiconductor contact region, being comprised by the semiconductor carrier layer.
  • a deposited III-V semiconductor layer is a semiconductor drift region with a first or a second conductivity type and a dopant concentration of 8 ⁇ 10 u ⁇ 1 ⁇ 10 15 cm ⁇ 3 .
  • a first highly doped semiconductor contact region of the first conductivity type with a dopant concentration of at least 1 • 10 18 cm -3 is preferably produced either as one of the III-V semiconductor layers by deposition after the deposition of the semiconductor drift region or by introducing dopants into an upper part of the semiconductor drift region .
  • the semiconductor carrier layer has a substrate layer, the substrate layer not being or partially or completely removed before the metallization step.
  • a second highly doped semiconductor contact area of the second conductivity type with a dopant concentration of at least 1 • 10 18 cm -3 is preferably made by deposition on the substrate layer or by introducing foreign atoms into part of the substrate layer or by introducing foreign atoms into the entire substrate layer or by providing a substrate layer provided with a dopant concentration of at least 5 • 10 17 cm -3 as part of the semiconductor carrier layer.
  • a second highly doped semiconductor contact region of the second conductivity type with a dopant concentration of at least 1 ⁇ 10 18 cm -3 is produced after removing the semiconductor carrier layer by introducing dopants into a lower portion of the semiconductor drift region.
  • a second highly doped semiconductor contact area of a second conductivity type with a dopant concentration of at least 1 • 10 18 cm -3 is used after the etching step to open the dielectric layer, i.e. the creation of the through opening and before the deposition of the semiconductor drift area as III-V- Semiconductor layer produced by deposition.
  • the second metallic connection contact layer is applied to an underside of the second semiconductor contact layer in the metallization step.
  • the semiconductor carrier layer provided preferably has a GaAs substrate or a Ge substrate or a Si substrate.
  • the dielectric layer has Si x O y , for example SiO 2 , or Si x Ni y or Al x O y or Ta x O y or Ti x O y or Hf x O y or consists of Si x O y or from Si x Ni y or from Al x O y or from Ta x O y or from Ti x O y or from Hf x O y .
  • the deposition is preferably carried out by means of MOVPE or by means of LPE or by means of CVD.
  • the first semiconductor contact region is produced by means of implantation or by means of diffusion. So foreign atoms are introduced into another semiconductor layer, e.g. the drift region, by implantation or diffusion and the corresponding area of the drift region then forms the first half-parent contact region or becomes the first semiconductor contact region.
  • the layer stack has a top side and a bottom side.
  • III-V semiconductor power diodes HLD shown in the sectional view have either a square or a rectangular or a round circumference or also a rectangular circumference with rounded corners in a plan view.
  • the illustration of the Figure 1 shows a stacked high-blocking III-V semiconductor power diode HLD.
  • the semiconductor power diode HLD has a first highly doped semiconductor contact region HK1 of the first conductivity type, a drift region HD1 of the first conductivity type or a second conductivity type and a second highly doped semiconductor contact region HK2 of the second conductivity type.
  • the first highly doped semiconductor contact region HK1 and the drift region together form a core stack with a top side, a bottom side, a side surface extending from the top side to the bottom side, a diameter d1 and a height h1.
  • the first semiconductor contact region HK1 and the drift region are each formed as a layer of the core stack.
  • the top of the core stack is formed by the first highly doped semiconductor contact region and a first metallic connection contact layer M1 is materially connected to the top.
  • the side surface of the core stack is enclosed by a dielectric frame area DR, a top side of the dielectric frame area DR flushing with the top side of the core stack, that is to say forming a flat common surface.
  • An underside of the dielectric frame area DR and the underside of the core stack likewise close off with one another or likewise form a flat common lower surface.
  • the dielectric frame area DR accordingly also has the height h1.
  • the dielectric frame area DR has a width b1, that is to say a wall thickness surrounding the core stack.
  • the second semiconductor contact region HK2 is embodied in layer form with a diameter or an edge length of d1 + 2 ⁇ b1 and is materially connected to the common underside of the core stack and the frame region DR.
  • a second metallic connection contact layer M2 covers an underside of the second semiconductor contact region HK2.
  • the semiconductor power diode HLD can be designed both as an n over p structure, that is to say with n as the first conductivity type and p as a second conductivity type, as well as a p over n structure, i.e. with p as the first conductivity type and n as the second conductivity type.
  • the semiconductor drift region HD1 has either the first or the second conductivity, that is to say is either weakly n-doped or weakly p-doped.
  • the p-n junction of the semiconductor power diode is correspondingly formed either between the second semiconductor contact region and the drift region or between the first semiconductor contact region and the drift region.
  • the core stack that is to say the drift region HD1 and the first semiconductor contact region HK1, on the other hand, have a round circumference.
  • the first metallic connection contact layer also has a round circumference, the diameter of the first metallic connection contact layer M1 being smaller than the diameter of the first semiconductor contact region.
  • the round circumference of the core stack can be produced easily and is particularly advantageous with regard to the electrical properties.
  • a square or rectangular circumference of the entire component can be produced particularly easily.
  • the first metallic connection contact layer also preferably has other circumferential shapes, for example polygonal ones.
  • the III-V semiconductor power diode HLD has a first intermediate layer ZW1, which is arranged as part of the core stack between the first semiconductor contact region HK1 and the semiconductor drift region HD1.
  • the III-V semiconductor power diode HLD has a second intermediate layer ZW2, which is arranged between the second semiconductor contact region HK2 and the semiconductor drift region HD1 and is materially connected to the common underside of the core stack and the dielectric frame region DR.
  • the second intermediate layer ZW2 is designed as part of the core stack, in particular as the lowermost layer of the core stack.
  • the second semiconductor contact region is also formed as part of the core stack, namely as the lowermost layer of the core stack.
  • the second metallic connection contact layer M2 is materially connected to the common underside formed from the underside of the core stack and the underside of the dielectric edge region.
  • III-V semiconductor power diodes HLD are connected by a common dielectric frame area DR.
  • the semiconductor power diodes HLD are also connected by a common second semiconductor contact region HK2 and a common second metallic connection contact layer.
  • the further embodiments can also be produced jointly on a wafer and have corresponding common structures.
  • the III-V semiconductor power diode HLD has a buffer layer sequence P, the buffer layer sequence P being below the dielectric frame area DR and the core stack and is arranged above the second semiconductor contact region HK2.
  • the core stack forms a first step S1 that rises towards the dielectric frame area DR and a descending second step S2 towards the underside of the dielectric frame area DR.
  • the steps are each created, for example, as a result of an etching process during manufacture.
  • the second metallic connection contact layer M2 is finger-shaped, that is to say has several finger-shaped and, for example, parallel sections, which are preferably connected to one another by a further transverse section.
  • the buffer layer sequence P is designed as part of the core stack.
  • the buffer layer sequence has, for example, three layers each with different lattice constants (shown in dashed lines).
  • the core stack has a first step that slopes down towards the top of the dielectric frame area, while the undersides of the dielectric frame area and of the core stack end with one another in this illustrated embodiment.
  • the second metallic connection contact layer is flat.
  • the first semiconductor contact region HK1 is trough-shaped and extends from the top of the core stack into the core stack, here into the semiconductor drift layer HD1.
  • the second semiconductor contact region HK2 is trough-shaped and extends from the underside of the core stack into the core stack.
  • the two semiconductor contact regions HK1 and HK2 are designed to protrude into the core stack in the shape of a trough.
  • the core stack of the high-blocking III-V semiconductor power diode HLD has the first semiconductor contact region HK1 and the first semiconductor intermediate layer ZW1.
  • the drift region HD1 forms the carrier region together with the second semiconductor contact region HK2 and the second metallic connection contact layer M2.
  • a highly doped second semiconductor contact layer HK2 is deposited on a substrate layer SUB, for example by means of MOVPE or LPE or CVD, the substrate layer SUB together with the second semiconductor contact layer HK2 serving as a semiconductor carrier layer TR.
  • a dielectric layer DS for example an SiO 2 layer, is deposited on a top side of the semiconductor carrier layer TR.
  • a mask layer MA with at least one through opening OE is then applied to an upper side of the dielectric layer DS.
  • the dielectric layer DS is removed in the region of the at least one through opening OE of the mask layer MA at least as far as the semiconductor carrier layer TR. It goes without saying that part of the semiconductor carrier layer TR, in this case the second semiconductor contact layer HK2, may also be etched away by the etching process. The part of the dielectric layer DS remaining after the etching step forms a dielectric frame area DR.
  • the mask layer MA is removed again.
  • a semiconductor drift layer HD1 is deposited on the exposed top side of the semiconductor carrier layer TR, in this case the second semiconductor contact layer HK2, whereby an increased layer thickness of the semiconductor drift layer HD1 is either smaller than the height of the dielectric frame area (left path of the Figure 13 ) or the same (right path of the Figure 13 ) or larger (not shown).
  • a first highly doped semiconductor contact layer HK1 is then deposited either on an upper side of the semiconductor drift layer HD1 (left path of the Figure 13 ) or by introducing dopants into a region of the semiconductor drift layer HD1 adjoining an upper side of the semiconductor drift layer HD1 (right path of the Figure 13 ).
  • the substrate layer SUB is then removed.
  • a first metallic connection contact layer M1 which is at least regionally formed, is placed on an upper side of the first semiconductor contact layer HK1, and a second metallic connection contact layer M2 applied to the underside of the second semiconductor contact layer HK2.
  • the substrate layer provided is converted into a highly doped semiconductor contact layer HK2 by introducing dopants and serves as a semiconductor carrier layer TR.
  • the method step of removing the substrate is omitted, the substrate layer being thinned in a further development.
  • the substrate layer SUB serves as a carrier layer TR.
  • the second semiconductor contact layer HK2, the drift region HD1 and the first semiconductor contact layer HK1 are grown one after the other on the exposed surface area of the carrier layer TR, that is to say the substrate SUB.
  • the carrier layer TR that is to say the substrate layer SUB, is then removed and the first and second metallic connection contact layers are applied (left path of the Figure 15 ).
  • the substrate layer SUB is not or only partially removed (thinned) and the second metallic connection contact layer M2 is applied to an underside of the substrate layer SUB (right path of the Figure 15 ).

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  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Electrodes Of Semiconductors (AREA)
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