EP3821458A1 - Procédé de fabrication de boîtiers de composant électronique et boîtier de composant électronique obtenu par ce procédé - Google Patents
Procédé de fabrication de boîtiers de composant électronique et boîtier de composant électronique obtenu par ce procédéInfo
- Publication number
- EP3821458A1 EP3821458A1 EP19749397.6A EP19749397A EP3821458A1 EP 3821458 A1 EP3821458 A1 EP 3821458A1 EP 19749397 A EP19749397 A EP 19749397A EP 3821458 A1 EP3821458 A1 EP 3821458A1
- Authority
- EP
- European Patent Office
- Prior art keywords
- connection
- electronic component
- encapsulation
- connection pads
- face
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 12
- 239000000463 material Substances 0.000 claims abstract description 34
- 239000003989 dielectric material Substances 0.000 claims abstract description 28
- 238000005538 encapsulation Methods 0.000 claims abstract description 26
- 239000004020 conductor Substances 0.000 claims abstract description 22
- 239000000853 adhesive Substances 0.000 claims description 16
- 230000001070 adhesive effect Effects 0.000 claims description 16
- 239000010410 layer Substances 0.000 description 12
- 229920005989 resin Polymers 0.000 description 7
- 239000011347 resin Substances 0.000 description 7
- 239000011248 coating agent Substances 0.000 description 5
- 238000000576 coating method Methods 0.000 description 5
- 238000004080 punching Methods 0.000 description 5
- 238000005520 cutting process Methods 0.000 description 3
- 238000009434 installation Methods 0.000 description 3
- 238000001465 metallisation Methods 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 238000003475 lamination Methods 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 239000004033 plastic Substances 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 210000000329 smooth muscle myocyte Anatomy 0.000 description 2
- 239000004743 Polypropylene Substances 0.000 description 1
- 239000012790 adhesive layer Substances 0.000 description 1
- 238000003486 chemical etching Methods 0.000 description 1
- 210000001520 comb Anatomy 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
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- 229920001155 polypropylene Polymers 0.000 description 1
- 229920001296 polysiloxane Polymers 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 229920001187 thermosetting polymer Polymers 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49537—Plurality of lead frames mounted in one device
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/561—Batch processing
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48153—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate
- H01L2224/48175—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being metallic
- H01L2224/48177—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being metallic connecting the wire to a bond pad of the item
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/81001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus
- H01L2224/81005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
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- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/85001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector involving a temporary auxiliary member not forming part of the bonding apparatus, e.g. removable or sacrificial coating, film or substrate
- H01L2224/85005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector involving a temporary auxiliary member not forming part of the bonding apparatus, e.g. removable or sacrificial coating, film or substrate being a temporary or sacrificial substrate
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
- H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
- H01L2924/18165—Exposing the passive side of the semiconductor or solid-state body of a wire bonded chip
Definitions
- the invention relates to the field of manufacturing processes for electronic component packages, such as for example integrated circuit packages of the "QFN" type (for "Quad Flat No-Lead” in English).
- document EP2846355A1 describes a process in which
- a dielectric material in the form of a strip; this strip extending in a longitudinal direction and having two main faces, one of which is at least partially covered with a sheet of electrically conductive material,
- connection units are produced in the sheet of electrically conductive material, these connection units being distributed along the longitudinal direction with a determined pitch, each connection unit comprising a connection face with connection pads, these connection pads being intended for the electrical connection of the integrated circuit box, for example on a printed circuit,
- an electronic component is placed on the strip at each connection unit and it is connected to at least some of the connection pads of the connection unit at which it is placed, and
- the electronic component is wrapped in an encapsulation material, at each connection unit.
- the electronic component is placed in a cavity in a housing molded by injection on the strip and in a mold, at each connection unit. Then, the electronic component is coated in a resin deposited in this cavity.
- the invention provides another method of manufacturing integrated circuit packages.
- the electronic component is also placed in a cavity before its encapsulation (or coating; in this text the terms coating and encapsulation are used as synonyms, just as coated or encapsulated), but on the one hand this cavity is produced differently, and on the other hand the encapsulation is carried out by dispensation, that is to say by depositing the encapsulation material in the cavity, without using a mold.
- the cavity is blind. Its bottom is formed by a layer of flexible and removable material which is removed after encapsulation of the electronic component.
- the electronic component can be encapsulated by coating, in a plastic, a resin, etc. after having been deposited on a support, without it being necessary, beforehand, to form a housing by injecting a plastic material into a mold, or to use an independent mold to inject the coating material.
- the method according to the invention makes it possible to use at least one material (dielectric material, electrically conductive material, etc.), or some of the materials, moreover necessary for the production of the connection tracks, to form at least one part of a blind cavity which will then be used to receive the encapsulation material.
- the method according to the invention makes it possible in particular to produce integrated circuit packages of the "QFN" type in which an electronic component (in this case an electronic chip) is encapsulated to form miniaturized components for surface mounting (“ SMCs ”). It can also be used to make SIM cards (“Subscriber Identification Module”, or “Subscriber Identity Module” in English) with flush contacts for electrical connection with the device in which this SIM card is inserted.
- SIM cards Subscriber Identification Module
- SIM Identity Module Subscriber Identity Module
- the method according to the invention optionally includes one or other of the characteristics mentioned in claims 2 to 7, considered in isolation or in combination with one or more others.
- the invention is an electronic component box intended for surface mounting on an electrical circuit, this box being manufactured according to a process such as that mentioned above.
- the characteristics of this box correspond to those mentioned in claim 8.
- the electronic component housing according to the invention optionally includes one or the other of the characteristics mentioned in claims 9 to 11, considered in isolation or in combination with one or more others.
- Figure 2 shows a top view of an example of an electrical circuit strip at different stages of a method according to the invention
- Figure 2A shows an enlarged part of Figure 2;
- FIG. 3 shows an electrical circuit connection unit for the implementation of a method according to the invention, before installation of an electronic component at this connection unit;
- FIG. 4 shows the electrical circuit connection unit of Figure 3, after installation and overmolding of an electronic component at this connection unit;
- FIG. 5 shows, schematically seen from below an example of an integrated circuit package obtained according to a method according to the invention
- FIG. 6 shows, schematically in perspective the integrated circuit package of Figure 5.
- FIG. 1 A first example of implementation of the method according to the invention is shown in Figure 1. It is described below in connection with the manufacture of an integrated circuit box of the "QFN" type. This implementation example includes the following steps:
- the strip 10 extends in a longitudinal direction L in which it is unwound; this strip 10 has two main faces 10A, 10B; the strip 10 has a thickness of, for example, 75 ⁇ m or 110 ⁇ m;
- the strip 10 is coated with dielectric material, at least partially, on one (in this case the main face 10A) of its main faces 10A, 10B with an adhesive 20 which can be reactivated when hot (of epoxy resin type) modified) (Fig. lb);
- - Perforations 30 are made in the strip 10 of dielectric material coated with the adhesive 20 to form drive notches on the edges of the strip 10 of dielectric material as well as cavities; these perforations 30 are produced, for example by punching; the cavities are distributed with a pitch defined by the desired distance between the integrated circuit boxes (Fig. le);
- a sheet 40 of electrically conductive metallic material is laminated on the face
- this sheet 40 of electrically conductive material is for example a sheet of copper - or one of its alloys - 70mpi thick;
- the sheet 40 of electrically conductive material is etched for example by photo lithography to define and produce patterns 50 (alternatively the patterns 50 are completely, or only partially, cut out mechanically before lamination of the sheet 40 of electrically conductive material, on the face of the strip 10 of dielectric material comprising the adhesive 20); these patterns 50, and the connection units which they comprise are distributed along the longitudinal direction L with a fixed pitch; the patterns 50 include in particular connection units connected by conductive tracks (Fig. le and Fig.
- connection units a blind or non-opening cavity 60 on one face of the strip 10 of the dielectric material; one and / or the other of the two faces of the sheet 40 of electrically conductive material are optionally metallized; this metallization (for example Ni / Au or Ag) is, for example, suitable for "QFN" type component transfer methods on an electrical circuit and / or for methods of connection to connection pads to electronic component 90 (see below) in relation to Fig. li);
- connection pads 45 make it possible, on the one hand, to connect the “QFN” type component to an electrical circuit and, on the other hand, to connect an electronic component 90 (FIG. 1f and FIG. li );
- this layer 80 of removable material is for example made up of a strip with a non-permanent adhesive or has a face coated with a non-permanent adhesive; it may for example be a polypropylene film coated with a layer of rubber-based adhesive, or a polyimide film coated with a layer of silicone-based adhesive; optionally the adhesive layer is protected by a non-stick protective film; it can be the reference 1285 from the company SCAPA, or the reference SMX-P30S from the company SEEMEX Inc.
- this layer 80 of removable material constitutes a bottom for the openings 70 cut in the previous step; a blind or non-opening cavity 60 is thus formed; the cavity 60 is therefore closed by a bottom consisting of the removable layer 80 and on its periphery by the edge cut from the strip
- the removable layer 80 is in contact with the connection pads 45 and thus protects one of their faces during the subsequent encapsulation step;
- an electronic component 90 (for example an electronic chip) is deposited in the cavity 60, for example on an adhesive face of the removable layer 80 deposited in the previous step (Fig. 1h);
- the electronic component 90 is connected for example by wire connection (wire bonding) or flip chip to the connection pads 45 (for the example illustrated in this document, it is a wire connection between the connection pads 45 and the connection pads of the electronic component 90 - see Fig. li);
- connection pads 45 are isolated from each other by punching in order to allow an individual electrical test of the components of the “QFN” type (FIG. 1j); in FIG. 1j and in FIGS. 3 and 4, the dotted lines schematically represent the short circuit 48 present in the electrically conductive sheet 40, before this step making it possible to electrically isolate the connection pads 45 from each other; thus after this step, although the electronic component housings 110 are not yet individualized (see below),
- connection pads 45 it is possible to mount an electronic component 90, and to connect it to the connection pads 45, then to test it; this step is optional, especially if the electronic components 90 are only tested after individualization of their respective housing 110 (see FIGS. 5 and 6); - The electronic component 90, the connection pads 45 and a portion of the strip
- FIG. 2 schematically shows a strip 10 of dielectric material with patterns 50 etched in the sheet 40 of electrically conductive material.
- the patterns 50 include conductive tracks 52 and connection units 54.
- the conductive tracks 52 are used in particular to bring electric current during an electrolytic deposition implemented for the metallization of the connection pads 45.
- units 54 are shown after cutting the connection pads 45 (see also Figure 3).
- areas of cutouts 56 also produced by punching are shown to isolate the connection pads 45 from one another (see also FIG. 4).
- connection pads 45 have not already been isolated from one another during a step such as that shown in Figure lj), they can be concomitantly in the final step of individualization of the housings 110 of electronic component (Fig. lm).
- the strip 10 extends in a longitudinal direction L in which it is unwound; this strip 10 has two main faces 10A, 10B; the strip 10 has a thickness of, for example, 75 ⁇ m or 110 ⁇ m;
- the strip 10 is coated with dielectric material, at least partially, on one (in this case the main face 10A) of its main faces 10A, 10B with an adhesive 20 (Fig. 7b) suitable for sticking temporarily the dielectric material 10 with an electrically conductive material 40 (Fig. 7d); the complex thus produced with the strip 10 covered with the adhesive forms a layer of flexible and removable material 80 ’;
- Perforations 30 are made in the strip 10 of dielectric material coated with the adhesive 20; in particular cavities are made, for example by punching, to form drive notches on the edges of the strip 10 of dielectric material (Fig. 7c); - A sheet 40 of electrically conductive metal material is laminated on the face
- this sheet 40 of electrically conductive material is for example a sheet of copper - or one of its alloys - 105mhi of minimum thickness;
- connection units 7e and 7f these patterns, and the connection units which they comprise are distributed along the longitudinal direction L with a fixed pitch; the patterns include in particular connection units connected by conductive tracks; at this stage, the connection units therefore comprise a blind or non-opening cavity 60 on one face of the dielectric material; one and / or the other of the two faces of the sheet 40 of electrically conductive material are optionally metallized; this metallization (for example Ni / Au or Ag) is for example suitable for methods of transferring a component of the “QFN” type onto an electrical circuit and / or of connection to connection pads 45 to the electronic component 90 (see also below in relation to Fig. 7g);
- the electronic component 90 is connected for example by wire connection (wire-bonding) or flip chip to the connection pads 45 (for the example illustrated in this document, it is a wire connection between the connection pads 45 and the connection pads of the electronic component 90 - see Fig. 7g);
- the electronic component 90, the connection pads 45 and a portion of the dielectric material are encapsulated for example in a resin 100 (to form what is called a glob-top), filling the cavities 60 by dispensing from place to place, to form the “QFN” type components at the desired pitch (Fig. 7h);
- the resin 100 is flattened or flattened (Fig. 7h ’);
- the strip 10 of dielectric material is removed (peeled) (Fig. 7i) (with the adhesive 20); the strip 10 of dielectric material therefore played the role of a layer of flexible and removable material, the electronic components 90 or modules of the “QFN” type are then electrically tested and individualized for a transfer step (“pick and place” in English) later on an electrical circuit; this stage can be concomitant or consecutive of a step of short-circuiting the connection pads 45; this step can be concomitant or consecutive with a step of cutting the edges of the cavity 60 made of the conductive material (Fig. 7j).
- the electronic components 90 obtained by this second embodiment of the method according to the invention are similar or similar to those which are, or could have been, obtained using the first example and illustrated by Figures 2 to 6.
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
Description
Claims
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR1856526A FR3083920A1 (fr) | 2018-07-13 | 2018-07-13 | Procede de fabrication de boitiers de composant electronique et boitier de composant electronique obtenu par ce procede |
PCT/FR2019/051729 WO2020012120A1 (fr) | 2018-07-13 | 2019-07-10 | Procédé de fabrication de boîtiers de composant électronique et boîtier de composant électronique obtenu par ce procédé |
Publications (1)
Publication Number | Publication Date |
---|---|
EP3821458A1 true EP3821458A1 (fr) | 2021-05-19 |
Family
ID=65200907
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP19749397.6A Pending EP3821458A1 (fr) | 2018-07-13 | 2019-07-10 | Procédé de fabrication de boîtiers de composant électronique et boîtier de composant électronique obtenu par ce procédé |
Country Status (5)
Country | Link |
---|---|
EP (1) | EP3821458A1 (fr) |
CN (1) | CN112470261A (fr) |
FR (1) | FR3083920A1 (fr) |
SG (1) | SG11202100314PA (fr) |
WO (1) | WO2020012120A1 (fr) |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20040058478A1 (en) * | 2002-09-25 | 2004-03-25 | Shafidul Islam | Taped lead frames and methods of making and using the same in semiconductor packaging |
US7453157B2 (en) * | 2004-06-25 | 2008-11-18 | Tessera, Inc. | Microelectronic packages and methods therefor |
SG132533A1 (en) * | 2005-11-21 | 2007-06-28 | St Microelectronics Asia | Ultra-thin quad flat no-lead (qfn) package and method of fabricating the same |
US8030138B1 (en) * | 2006-07-10 | 2011-10-04 | National Semiconductor Corporation | Methods and systems of packaging integrated circuits |
US8643165B2 (en) * | 2011-02-23 | 2014-02-04 | Texas Instruments Incorporated | Semiconductor device having agglomerate terminals |
JP5924110B2 (ja) * | 2012-05-11 | 2016-05-25 | 株式会社ソシオネクスト | 半導体装置、半導体装置モジュールおよび半導体装置の製造方法 |
US8835228B2 (en) * | 2012-05-22 | 2014-09-16 | Invensas Corporation | Substrate-less stackable package with wire-bond interconnect |
US9969891B2 (en) * | 2013-05-10 | 2018-05-15 | Oxifree Global Limited | Coating composition for the protection of complex metal structures and components |
BR102013022262A2 (pt) * | 2013-05-10 | 2016-04-26 | Oxifree Holdings Corp | sistema de revestimento para proteção de estruturas de metal complexas em ambientes submersos |
EP2846355A1 (fr) | 2013-07-26 | 2015-03-11 | Linxens Holding | Substrat électrique et procédé de fabrication de celui-ci |
US9379087B2 (en) * | 2014-11-07 | 2016-06-28 | Texas Instruments Incorporated | Method of making a QFN package |
-
2018
- 2018-07-13 FR FR1856526A patent/FR3083920A1/fr active Pending
-
2019
- 2019-07-10 EP EP19749397.6A patent/EP3821458A1/fr active Pending
- 2019-07-10 WO PCT/FR2019/051729 patent/WO2020012120A1/fr unknown
- 2019-07-10 CN CN201980046879.4A patent/CN112470261A/zh active Pending
- 2019-07-10 SG SG11202100314PA patent/SG11202100314PA/en unknown
Also Published As
Publication number | Publication date |
---|---|
FR3083920A1 (fr) | 2020-01-17 |
SG11202100314PA (en) | 2021-02-25 |
CN112470261A (zh) | 2021-03-09 |
WO2020012120A1 (fr) | 2020-01-16 |
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