EP3818563A1 - Dispositif electronique et son procede de realisation - Google Patents
Dispositif electronique et son procede de realisationInfo
- Publication number
- EP3818563A1 EP3818563A1 EP19745566.0A EP19745566A EP3818563A1 EP 3818563 A1 EP3818563 A1 EP 3818563A1 EP 19745566 A EP19745566 A EP 19745566A EP 3818563 A1 EP3818563 A1 EP 3818563A1
- Authority
- EP
- European Patent Office
- Prior art keywords
- substrate
- spacer
- stud
- metal
- wire element
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/073—Connecting or disconnecting of die-attach connectors
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01L—MEASURING FORCE, STRESS, TORQUE, WORK, MECHANICAL POWER, MECHANICAL EFFICIENCY, OR FLUID PRESSURE
- G01L9/00—Measuring steady of quasi-steady pressure of fluid or fluent solid material by electric or magnetic pressure-sensitive elements; Transmitting or indicating the displacement of mechanical pressure-sensitive elements, used to measure the steady or quasi-steady pressure of a fluid or fluent solid material, by electric or magnetic means
- G01L9/0041—Transmitting or indicating the displacement of flexible diaphragms
- G01L9/0072—Transmitting or indicating the displacement of flexible diaphragms using variations in capacitance
- G01L9/0073—Transmitting or indicating the displacement of flexible diaphragms using variations in capacitance using a semiconductive diaphragm
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/01—Manufacture or treatment
- H10W72/019—Manufacture or treatment of bond pads
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/30—Die-attach connectors
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/851—Dispositions of multiple connectors or interconnections
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W99/00—Subject matter not provided for in other groups of this subclass
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W46/00—Marks applied to devices, e.g. for alignment or identification
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/01—Manufacture or treatment
- H10W72/019—Manufacture or treatment of bond pads
- H10W72/01951—Changing the shapes of bond pads
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- H—ELECTRICITY
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- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/073—Connecting or disconnecting of die-attach connectors
- H10W72/07302—Connecting or disconnecting of die-attach connectors using an auxiliary member
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- H—ELECTRICITY
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- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/073—Connecting or disconnecting of die-attach connectors
- H10W72/07321—Aligning
- H10W72/07323—Active alignment, e.g. using optical alignment using marks or sensors
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/073—Connecting or disconnecting of die-attach connectors
- H10W72/07331—Connecting techniques
- H10W72/07337—Connecting techniques using a polymer adhesive, e.g. an adhesive based on silicone or epoxy
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/073—Connecting or disconnecting of die-attach connectors
- H10W72/07351—Connecting or disconnecting of die-attach connectors characterised by changes in properties of the die-attach connectors during connecting
- H10W72/07355—Connecting or disconnecting of die-attach connectors characterised by changes in properties of the die-attach connectors during connecting changes in materials
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/075—Connecting or disconnecting of bond wires
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/075—Connecting or disconnecting of bond wires
- H10W72/07531—Techniques
- H10W72/07537—Techniques using a polymer adhesive, e.g. an adhesive based on silicone or epoxy
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- H—ELECTRICITY
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- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/30—Die-attach connectors
- H10W72/351—Materials of die-attach connectors
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/30—Die-attach connectors
- H10W72/381—Auxiliary members
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/851—Dispositions of multiple connectors or interconnections
- H10W72/853—On the same surface
- H10W72/865—Die-attach connectors and bond wires
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
- H10W72/931—Shapes of bond pads
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W80/00—Direct bonding of chips, wafers or substrates
- H10W80/011—Manufacture or treatment of pads or other interconnections to be direct bonded
- H10W80/031—Changing or setting shapes of the pads
- H10W80/035—Changing or setting shapes of the pads by heating, e.g. melting or causing diffusion
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/20—Configurations of stacked chips
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/20—Configurations of stacked chips
- H10W90/231—Configurations of stacked chips the stacked chips being on both top and bottom sides of an auxiliary carrier having no electrical connection structure
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
- H10W90/732—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between stacked chips
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL
Definitions
- the invention relates to a method for manufacturing an electronic device and for example an integrated circuit chip
- US patent 8723312 describes different chip architectures. These chips include a first substrate separated from a second substrate by a spacer. The spacer, the first substrate and the second substrate define one or two lateral grooves which are used to embed an electrically conductive wire.
- WO2008 / 025889 describes a microelectronic chip comprising two parallel main faces and opposite side faces. At least one of the side faces has a groove, provided with an electrical connection element forming a housing for a wire element having an axis parallel to the longitudinal axis of the groove.
- US Patent 8723312 also describes a method of inserting a wire element inside the groove. The integrated circuit which is present in the first substrate is brought into electrical contact with an external element by means of the electrically conductive wire which is inserted in the groove.
- the invention proposes to provide a process for manufacturing a device which is easy to implement and which makes it possible to produce a more efficient device because the positions of the elements are better defined.
- the process for manufacturing a device is remarkable in that it comprises the following successive steps:
- the at least one metal stud fixing the first substrate with the second substrate, the at least one metal stud forming a locking means configured to come into contact with the second substrate when the second substrate reaches a threshold position relative to the first substrate;
- the first substrate is fixed to the second substrate by means of a spacer and during the fixing of the first substrate with the second substrate, the at least one metal stud is arranged to block the movement of the first substrate relative to the second substrate to a predefined air gap in a direction perpendicular to a face of the first substrate facing a face of the second substrate.
- a portion of the second substrate is movable relative to the first substrate.
- the metal pad is formed on a first electrode and the annealing transforms the at least one metal pad into an additional electrode electrically connected to the first electrode.
- the method comprises a step of compressing the spacer during the fixing of the first substrate with the second substrate so as to have the second substrate in contact with the at least one metal stud.
- the at least one metal stud is arranged to block the movement of the first substrate relative to the second substrate in a direction parallel to a face of the first substrate supporting the second substrate, the second substrate having planar side walls.
- the metal stud is formed on an electrical contact, the annealing transforming the metallic stud into an additional electrical contact and in which an electronic component is fixed to the first substrate and is electrically connected to the first substrate by means of the additional electrical contact.
- the first substrate is fixed to the second substrate by means of a spacer, the first substrate, the spacer and the second substrate defining at least one lateral groove and in which during the fixing of the first substrate with the second substrate.
- the at least one metal stud is arranged to block the movement of the first substrate relative to the second substrate in a direction parallel to a face of the first substrate supporting the second substrate.
- the at least one metal stud preventing the introduction of a wire element into the lateral groove, the annealing transforming the metal stud before the introduction of a wire element into the lateral groove.
- the metal pad is formed on an electrical track, the annealing transforming the metal pad into an electrical contact.
- the wired element is electrically conductive and is electrically connected to the electrical track by means of the electrical contact.
- a wire element is installed on the first substrate between two metal pads so that the two metal pads block a movement of the wire element in a direction parallel to a face of the first substrate supporting the wire element.
- the molten material partially covers the wire element by capillary action.
- a fixing layer is deposited on the wire element and the metallic material after the annealing step to fix the wire element with the first substrate.
- the wire element is installed on a support and that the first substrate blocks the wire element against the support, the wire element being blocked during the annealing step.
- the first substrate is fixed to the second substrate by means of a spacer.
- the at least metal pad is constrained between the first and second substrates, the spacer, the first substrate and the second substrate defining a channel closed by the at least metal stud.
- the annealing step passes the at least one metal pad in the molten state to open the channel.
- FIG. 1 to 5 show, schematically, in section, a first embodiment of a method of manufacturing an integrated circuit chip
- FIG. 6 shows, schematically, in section, an alternative embodiment of a method of manufacturing an integrated circuit chip
- FIGS. 7 to 10 schematically represent, in section, a second embodiment of a method for manufacturing an integrated circuit chip
- FIGS. 11 to 15 schematically represent, in section, a third embodiment of a method for manufacturing an electronic device
- FIGS. 16 to 19 schematically represent, in section, a fourth embodiment of a method for manufacturing an electronic device
- FIG. 20a to 23a and 20b to 23b show schematically, respectively in section and in top view, a fifth embodiment of a method of manufacturing a device.
- blocking means it is particularly advantageous when producing a electronic and / or microfluidic device, to use blocking means in order to more easily produce the device or to improve its performance.
- locking means When attaching a first substrate to a second substrate, it is advantageous to use locking means in order to define a position or a range of positions accessible for the second substrate relative to the first substrate.
- the locking means can also be used to define the position of other elements of the electronic device, for example wire elements fixed to the first substrate and / or to the second substrate.
- blocking means which are sacrificial so that after having fixed the desired alignment / positioning, the blocking means are removed to allow the use of the free space for another function. It is particularly interesting that the removal of the blocking means is a transformation of the blocking means into another function, for example an electrode, an electrical contact or a fixing means.
- the blocking means by at least one metal stud which can be annealed in order to melt.
- the metal stud is initially shaped to define the locking means and the annealing step makes it possible to change the shape of the locking means.
- the stud is no longer able to perform the blocking function but it provides another advantage for example by covering a wire element which improves the electrical contact and / or the mechanical strength.
- the chip is defined by means of a first substrate 1 surmounted by at least one metal pad 2.
- the first substrate 1 is intended to be fixed to a second substrate 3.
- the pad 2 intervenes to define the position of the second substrate 3 relative to the first substrate 1 in one or more directions which are parallel to the two faces of the substrates 1 and 3 which are opposite.
- the stud 2 intervenes to define the distance which separates the two substrates 1 and 3, that is to say that the stud 2 fixes the spacing or gap of the second substrate 3 by relative to the first substrate 1 in a direction perpendicular to the two faces of the substrates 1 and 3 which are opposite.
- the studs 2 are of certain interest for aligning the two substrates 1 and 3 or defining an air gap between the two substrates, but they occupy a non-negligible volume at the surface of the substrates 1 and 3 which limits their use or requires working with larger substrates.
- the removal step can have a significant influence on the various elements which are already present on the surface of the first and second substrates 1 and 3.
- the use of a particular etching atmosphere makes it necessary to protect from areas of substrates 1 and 3 which are reactive to this atmosphere or this requires the use of a greater thickness of material in order to anticipate a more or less significant withdrawal of material when the pad 2 is removed.
- Etching by plasma or by the chemical route can also damage any components placed in the cavity.
- the interior of the cavity is inaccessible, which may be the case for a pressure sensor whose membrane is thinned at the end of the process.
- the step of transforming the pad 2 to be a step of thermal transformation by increasing the temperature of the pad 2 beyond its melting temperature. For example, the heating is done by the Joule effect by circulating a current in the metal pad 2.
- a step of eliminating the pad 2 for example by chemical or physical means but on the contrary a step of transforming the pad 2 so that the material which formed the pad 2 can subsequently interact with a other element of the electronic device and perform another function.
- a pad 2 made of electrically conductive material Initially, the pad 2 mechanically ensures the positioning of the first substrate 1 relative to the second substrate 3. After the transformation of the pad, the position of the second substrate 3 is defined relative to the first substrate 1 and the electrically conductive material is used to electrically connect the first substrate 1 with an external element which is preferably introduced after the fixing of the two substrates 1 and 3.
- the volume occupied by the first pad 2 is released, which allows the introduction of an additional element. Furthermore, it is particularly advantageous to provide that the additional element is fixed to the first substrate 1 while the material forming the pad 2 is still in the liquid state following the transformation step. Thus the additional element can be inserted without the conductive material interfering with the installation on the first substrate 3.
- the stud 2 prohibits the installation of the additional element which facilitates monitoring of the manufacturing process by avoiding an inversion of the stages.
- the material forming the pad 2 is transformed then solidifies and the additional element is installed.
- a new annealing step can be applied so that the material forming the pad 2 returns to the molten state to react with the additional element.
- the additional element is for example an electrically conductive wired element 6 or an electronic component 9.
- the manufacturing method includes the supply of a first substrate 1 surmounted by one or more pads 2 in projection as illustrated in Figure 1.
- the first substrate 1 is intended to come into contact with a spacer A surmounting a second substrate 3.
- the assembly formed by the spacer A and the second substrate 3 is brought into contact with the first substrate 1.
- a first alignment is made in the directions X and / or Y so as to place judiciously the spacer A with respect to the first substrate 1 and thus define one or more lateral grooves 5 and make sure that the first substrate 1 is indeed opposite with the second substrate 3.
- This placement of the spacer A relative to the first substrate 1 is called the assembly step.
- the first substrate 1 is disposed on the second substrate 3 with a first alignment.
- This first alignment can be defined in a first direction X and possibly a second direction Y perpendicular to the first direction X.
- the first and second directions are taken along a plane parallel to the surface of the first substrate 1.
- a fixing step is carried out so as to fix the first substrate 1 with the spacer A and fix the first substrate 1 with the second substrate 3.
- a pressure constraint is applied to the first substrate 1 and to the second substrate 3, which results in a possible displacement of the first substrate 1 relative to the second substrate 3 by sliding.
- the first alignment is degraded or even lost.
- This movement is linked, for example to a layer of adhesive 4 which is located between the first substrate 1 and the spacer A.
- the layer of adhesive 4 ensures the fixing of the first substrate 1 with the second substrate 3.
- the layer 4 transforms and generally liquefies which promotes sliding between the spacer A and the first substrate 1.
- the sliding results in a modification of the dimensions of the lateral grooves.
- the second substrate 3 is fixed to the first substrate 1 by a layer of polymeric material 4.
- the at least one metal stud 2 is formed in a material having a melting temperature below the degradation temperature of the layer of polymeric material 4.
- blocking means are placed on the first substrate 1.
- the blocking means are formed by at least one first stud 2 projecting from on the surface of the first substrate 1 so as to come into contact with the spacer A and block its movement at least in the first direction X and advantageously in the second direction Y.
- the stop which exists to limit the movement in the direction X and / or Y direction ensures a minimum connection surface between the spacer A and the first substrate
- the shape of the first pad 2 can be arbitrary. It is advantageous to use a plurality of separate pads 2 in order to form a plurality of stops which limit the movement of the spacer A in the directions X and / or Y.
- the pad 2 can go around the area of mechanical contact between the spacer A and the first substrate 1.
- the pad 2 can have the shape of a C or an L in order to limit the displacement of the spacer A in the directions X and Y and in one or two opposite directions of each direction.
- the stud (s) 2 are arranged to block the movement of the spacer only in the direction X or only in the direction Y.
- the adhesive layer 4 is advantageously deposited on the first substrate 1 so as to fix the spacer A with the first substrate 1.
- the adhesive layer 4 can be placed on the first substrate 1 and / or on the spacer A. According to the embodiments, the adhesive layer 4 can be deposited before or after the formation of the pads 2.
- the layer of adhesive 4 has a reaction temperature allowing the fixation of the substrates 1 and 3 which is lower than the transformation temperature of the pad 2.
- the spacer A, the first substrate 1 and the second substrate 3 define at least one lateral groove 5.
- the pad 2 may have a significant thickness to define the height of the groove and avoid overly crushing the layer of adhesive 4 by the spacer A.
- a wire element 6 After fixing the two substrates together, in order to functionalize the lateral groove 5 by installing, for example, a wire element 6, it is particularly advantageous to remove the studs 2 which partially fill the groove 5 and which prevent easy access to the groove 5. As illustrated in FIG. 3, an annealing step is used in order to transform the stud 2 and thus release part of the volume of the lateral groove 5. The stud 2 is transformed into an electrical contact 2b of reduced thickness compared to at the initial plot 2.
- the height of the stud 2 is reduced by means of the annealing step, which facilitates the insertion of a wire element 6.
- the pad 2 is formed in an electrically conductive material, for example in a metallic material.
- the pad 2 is arranged on an electrical track of the first substrate 1 so that after its transformation, the electrically conductive material forms an electrical contact between the wire element 6 and the electrical track of the first substrate 1.
- the molten pads participate in the fixing of the wire elements which are electrically conductive wires 6 with the first substrate 1 and in improving the electrical connection between the electrically conductive wire 6 and the electrical track.
- Plots 2 are formed in an electrically conductive material which provides electrical contact between the electrically conductive wire 6 and the integrated circuit of the first substrate 1.
- the pad 2 comprises or consists of a solder material which is configured to melt and cover the electrically conductive wire 6 by capillary action in order to increase the adhesion between the chip and the electrically conductive wire 6.
- the pad 2 is made by means of several electrically conductive materials.
- the stud 2 projects beyond the first electrical contact zone formed by the electrical track located in the groove 5.
- the metallic material When the electrically conductive wires 6 are hot inserted into the lateral grooves 5 of the chip, the metallic material is in the liquid state and it wets the electrically conductive wire 6 by capillary action, which makes it possible to increase the surface of electrical contact between the first substrate 1 and the electrically conductive wire 6.
- the wire 6 is introduced into the groove 5 then the pad 2 is melted.
- brazing material which has a melting temperature higher than the temperature used during the step of fixing the spacer A with the first substrate 1.
- the wire element 6 is installed in the lateral groove 5, it is advantageous to deposit an encapsulation material 7.
- an encapsulation material 7 for example an adhesive which will reinforce the adhesion between the first substrate 1 and the second substrate 3 as well as with the spacer A and the wire element.
- the encapsulation material 7 is configured to fill the empty areas and strengthen the solidity of the chip.
- the encapsulation material 7 is an adhesive and advantageously a structural adhesive which can be an E505 adhesive sold by the company EPO-TEK. It is also possible to use Parylene also called poly (p-xylylene) or a fusible glass.
- the encapsulation material 7 may be a barrier material which is configured to block the passage of pollutants, for example water.
- the encapsulation material 7 is an adhesive and advantageously a protective adhesive which can be an adhesive TC420 sold by the company POLYTEC. It is still possible to use an encapsulation material 7 which has two functions: adhesive and barrier.
- the length of the spacer A in the direction X is of the order of a few hundred microns, for example between 100 microns and 1 millimeter.
- the width of the spacer A in the direction Y is advantageously of the order of a few tens of microns, for example between 10 microns and 100 microns.
- the pads 2 formed on the first substrate 1 are produced by electrolytic growth or by screen printing. Other techniques are also available but less practical from an industrial point of view. It is possible to provide that part of the pads is formed by electrolytic growth and another part of the pads is formed by another technique, for example by screen printing.
- the studs 2 project from the surface of the first substrate 1 by a height of between a few microns and a few hundred microns.
- the height of the pads 2 is between 2 microns and 500 microns.
- the width of the pads 2 is advantageously of the order of a few tens of microns, for example between 10 microns and 100 microns.
- the first substrate 1 comprises one or more electronic circuits, for example one or more field effect transistors and / or bipolar transistors.
- the substrate 1 can also include one or more resistors and / or one or more capacitors.
- the first substrate 1 can also be formed from semiconductor materials, for example from orientation silicon (100) (110) or (111), from III-V type material or from III-VI type material.
- the first substrate advantageously includes a support made of semiconductor material surmounted by several layers of electrically insulating material inside which flow multiple electrically conductive tracks in three dimensions.
- the second substrate and / or the spacer are fixed on an electrically insulating layer which has one or more accessible electrical tracks.
- the material forming the pads 2 is partially removed after the fixing of the second substrate 3. It is advantageous to anneal the pads 2 in order to transform the material in the liquid or molten state and to absorb the material having formed the studs 2.
- the lateral groove 5 being released, it is possible to introduce therein a wire element 6 for example by embedding.
- the chip has two opposite main external faces.
- the first external main face is formed by a first face of the first substrate 1.
- the second external main face is formed by a first face of the second substrate 3.
- the two opposite external main faces are parallel.
- the chip has two main faces connected to each other by lateral faces.
- At least one groove 5 is present in one of the side faces. In the embodiment illustrated in FIGS. 2 to 5, two grooves 5 are formed and are separated by the spacer A.
- the general shape of the chip is parallelepiped, the two main external faces can then be of substantially equal dimensions, and are connected by four lateral faces.
- a first substrate 1 and / or a second substrate 3 having a domed external main face.
- a lateral face can be an extension of a main face, without precise delimitation edges between them.
- the spacer A has been secured to the second substrate 3, for example by bonding.
- the spacer A is formed by etching the second substrate 3. It is also possible to combine these two embodiments.
- the spacer A has a height of between 100 microns and 200 microns. The height of the spacer A corresponds to the height of the projecting part relative to the rest of the second substrate 3. The height of the spacer A is defined as a function of the diameter of the electrically conductive wires 6.
- the spacer A is formed inside the second substrate 3 by ion etching and preferably by an ion etching of the Reactive Ion Etching type and more preferably by Deep Reactive Ion Etching.
- the placement of the second substrate 3 on the first substrate 1 with the desired level of alignment can be obtained industrially by means of bonding and alignment equipment sold by the companies Suss MicroTec and EVG.
- the fixing step is carried out by gluing, melting a fusible material, molecular sealing or anodic sealing of the spacer A with the first substrate 1.
- the fixing is carried out by means of an annealing, the maximum temperature of which is between the glass transition temperature and the polymerization temperature of the adhesive material 4 used to bond the spacer A with the first substrate 1 .
- the adhesive material is an adhesive sold under the name HT1010 by the company Brewer Science Inc.
- the wire elements 6 are inserted longitudinally in the grooves 5.
- the wire elements 6 are preferably pinched mechanically in the grooves 5.
- the first substrate 1 comprises at least one functional block configured to perform at least one logical and / or analog and possibly mechanical function (cf. support for electrical wires, etc.).
- the first substrate 1 also comprises at least a first electrical contact zone.
- the first substrate 1 has a second electrical contact area.
- the first substrate 1 comprises a silicon substrate or is constituted by a silicon substrate.
- the first substrate 1 is configured to perform a radio-identification type function also called "radio frequency identification" or RFID.
- the functional block is an integrated circuit configured to perform at least one logic and / or analog function.
- the first substrate 1 and the second substrate 3 are configured to produce a plurality of chips.
- the first substrate 1 comprises a plurality of identical or different integrated circuits which advantageously repeat according to a first repetition step in the first direction X and which are advantageously repeated according to a second repetition step in the second direction Y.
- the second substrate 3 is placed on the first substrate 1 so as to form the plurality of chips which have lateral grooves.
- a cutting step can be carried out so as to cut the first substrate 1, the second substrate 3 and possibly the spacer A and thus define a plurality of chips and side grooves.
- the chips can then be dissociated from each other.
- the first substrate 1 comprises predefined weakening lines in order to define the dimensions of the different chips and to facilitate future cutting. It is the same for the second substrate 3. It is then particularly advantageous to properly align the first substrate 1 with the assembly formed by the spacer A and the second substrate 3 in order to align the predefined weakening lines and facilitate the cutting chips.
- the first substrate 1 and / or the second substrate 3 are devoid of predefined weakening lines.
- the chips are cut by any suitable technique, for example using a saw or laser radiation.
- the first substrate 1 and the second substrate 3 have identical dimensions in the first direction and in the second direction.
- the second substrate 3 is an active element, that is to say that it comprises an electronic component, for example a battery.
- the second substrate 3 can be configured to supply the first substrate 1.
- the second substrate 3 has no electronic component.
- Each lateral groove has two opposite faces formed respectively by the first substrate 1 and the second substrate 3 and a bottom formed by the spacer A.
- Each groove 5 is open at its two ends.
- Each lateral groove 5 has, on its first lateral face, an electrical track.
- the insertion of the wire element is done by the side face perpendicular to the longitudinal axis of the groove
- Each wire element 6 has a longitudinal axis which is parallel or substantially parallel to the longitudinal axis of the groove 5, c 'is to say parallel to the axis Y.
- Each wire element 6 is secured to the first substrate 1 by welding with addition of material, by bonding, and / or by embedding.
- the embedding in the groove 5 requires to correctly dimension the wire element 6 and the groove 5.
- the mechanical resistance by embedding may be insufficient and generally requires a strengthening phase by the addition of glue and / or metal by means adhesive 4.
- the cross section of the electrically conductive wires 6 can be arbitrary.
- the first and second electrically conductive wires 6 are single-strand or multi-strand conductive wires. It is therefore possible to have a chip comprising two single-stranded conductive wires or two multi-stranded conductive wires or a mixture of these two technologies.
- a multi-stranded conductive wire comprises several conductive wires which are electrically dissociated and which make it possible to pass different signals.
- the multi-stranded conductive wire comprises several conductive wires which are connected together electrically and which circulate the same electrical signal.
- a multi-strand conductive wire can for example be in the form of a strand of several electrically conductive wires.
- the chip is an RFID type chip
- the first and / or the second electrically conductive wires 6 are advantageously configured to form communication antennas.
- the height of the spacer A and the section of the electrically conductive wires 6 are advantageously configured to ensure the compression of the electrically conductive wires between the two substrates.
- the first substrate 3 is surmounted by at least two studs 2 spaced from one another so as to allow the insertion of a wire element 6.
- annealing is carried out so as to melt the studs which will become impregnated on and / or in the wire element to cover it at least partially and fix the latter on the first substrate.
- the fixing can be improved by subsequently adding an adhesion element 7 which fixes the wire element to the first substrate 1.
- the wire element 6 is installed on the first substrate and the two studs 2 are arranged on the second substrate 3 at a distance from the wire element 6.
- the second substrate 3 is moved in direction of the first substrate 1 to wedge the wire element 6 by means of the two studs 2.
- Annealing is then carried out so that the molten material forming the studs is impregnated on the wire element 6 to achieve the fixing and possibly improve an electrical connection.
- the method for producing an electronic device also includes the use of a sacrificial pad 2.
- the method differs from the previous one in that the second substrate does not make it possible to define lateral grooves 5 or grooves which can cooperate with wire elements 6.
- the first substrate 1 is associated with one or more electrical contacts 8, for example metallic contacts, which are arranged projecting or on the surface of the first substrate 1.
- One or more pads 2 are disposed on the surface of the first substrate 1. It is also advantageous to use an adhesive layer 4 which can be deposited before or after the pads 2. It should be noted that protruding electrical contacts 8 could also be used in the previous embodiment.
- a second substrate 3 is installed on the first substrate 1.
- the second substrate 3 is intended to be fixed on the first substrate 1 for example by means of the layer of adhesive 4.
- the stud (s) 2 intervene during the fixing step in order to limit the misalignment between the two substrates 1 and 3.
- the second substrate 3 has flat side walls and perpendicular or substantially perpendicular to the surface of the first substrate 1. It is always advantageous to eliminate at least partially the pads 2 in order to take advantage of an additional surface accessible on the face of the first substrate 1 and to integrate additional functionalities into it.
- an annealing step is applied in order to melt the pad 2 and make accessible the electrical contact (s) 8 which are located on the surface of the first substrate 1. These contacts were initially partially or completely covered the pads 2 which made them difficult to use. Once the stud 2 has been transformed, it is possible to fix, on the electrical contact 8, an electronic device 9 or an electrical connector which will ensure the transmission of signals to an electronic device 9.
- the position of the electronic device 9 can be partially fixed using the second substrate as a stop during a step of fixing the electronic device 9 to the first substrate 1.
- the use of pads having a large thickness facilitates the alignment of the first substrate 1 relative to the second substrate 3.
- the pad 2 prevents optimal placement of the electronic device 9.
- the melting step makes it possible to release a volume initially occupied by the pad which facilitates or authorizes the installation of the device 9 as close as possible to the substrate 3 or at a desired height defined by the thickness of the stud after fusion.
- a first electronic component 9 and a second electronic component 9 are fixed on either side of the second substrate 3 on respectively a first electrical contact 8 and a second electrical contact 8 which are in projection of the first substrate 1.
- the second substrate 3 and / or the electronic component and / or the first substrate 1 can also include functionalities of the electronic type or a battery.
- the reverse configuration can be achieved by installing the pad 2 in place of the substrate 3 in FIG. 7 and by associating a second substrate 3 which goes around the pad 2 so as to block any movement in the direction X and / or in the direction Y.
- the pad 2 is made of an electrically conductive material. During its passage to the liquid state, the material forming the pad 2 covers the electrical contact and makes the electrical connection between the electronic components 9 added and the first substrate 1.
- FIGS. 9 and 10 Such an embodiment and illustrated in FIGS. 9 and 10.
- an electrical contact 8 made of copper or a copper alloy and gold or coated with gold or an alloy of copper and gold.
- the material forming the pad 2 is chosen so as to interdiffuse with the material forming the electrical contact 8.
- the electrical contact 8 is made of copper and the pad 2 is made of gold.
- the electrical contact 8 has a greater extent than necessary and the first substrate defines a plurality of locations for a plurality of second substrates. The electrical contacts are cut when sawing the substrate to differentiate the multiple chips from each other.
- the volume used to form the pad 2 is greater than necessary to define the electrical contact. Part of the electrical contact formed by the molten pad can be removed by sawing or any other technique after installation of the wire element or electronic component 9.
- the surface of the substrate has zones having different surface coatings which are configured to modify the wettability of the material forming the pad in the molten state.
- the pattern formed by the differences in surface coating makes it possible to at least partially define the pattern of the contact on the surface of the first substrate as well as the thickness of the molten material and therefore the thickness of the electrical contact which results therefrom.
- the difference in coating can be obtained by applying a plasma treatment and / or by using different materials. The difference in treatment makes it possible to facilitate the lateral extension of the molten material to reduce the thickness or, on the contrary, to limit the lateral extension to increase the thickness and facilitate significant covering of the element. Wired.
- the surface can be formed by a first coating which preferentially attracts the material in the molten state and by a second material which attracts less the material in the molten state or even repels it in order to define the shape of the pattern after fusion and its thickness. It is also possible to displace the pattern during fusion by using a suitable surface finish or even by applying a gas flow.
- At least one sacrificial stud 2 is used in order to define the position of the second substrate 3 relative to the first substrate 1.
- the first substrate 1 is surmounted by at least one stud 2 which is advantageously located on an electrical contact 8 for example in the form of an electrode.
- one or more spacers A are formed on the surface of the substrate 1.
- a second substrate 3 is fixed to the first substrate 1 on the multiple spacer (s) A.
- the second substrate 3 comes into contact with the pad 2 which makes it possible to define the separation distance between the two faces facing the substrates 1 and 3.
- the first substrate 1, the second substrate 3 and the support A define a sealed cavity.
- the spacer A is in the form of a ring, for example of polymer material.
- the second substrate 3 can undergo a technological step of thinning and / or flattening of the external face. It is particularly advantageous to use the second stud 2 which limits or prevents the bending of the second substrate 3 and which facilitates the processing of the second substrate 3. The risks of rupture and / or deformation of the second substrate 3 are greatly reduced. It is also possible to provide that the substrate undergoes a thickening or deposition step of another material for example to form another electrode. Any technological step carried out on the second substrate or in the presence of the second substrate can cause the second substrate to rupture, for example during the pressure peak.
- the resonance frequency of the second substrate 3 can then be defined by adapting the thickness of the second substrate 3.
- the planarization and / or thinning and / or thickening of the second substrate 3 makes it possible to precisely define the mechanical characteristics of the resonator . It is advantageous to produce the resonant element more easily by depositing a thicker material which is therefore less fragile and by adapting the final thickness to the desired frequencies.
- a pad 2 of electrically conductive material which after having gone into the molten state will at least partially cover the electrode 8 and participate in the actuation of the second substrate 3.
- the electrode 8 d actuation is therefore partly formed by the electrically conductive material which served to define the air gap which separates the first substrate 1 and the second substrate 3.
- the second substrate 3 can be formed by any suitable material, for example glass or silicon insofar as the material forming the second substrate 3 withstands the transformation temperature of the pad 2.
- a stud 2 made of polymer material which will degas during its transformation and thus increase the pressure inside the cavity. It is particularly advantageous to use a stud 2 of metallic material which does not interfere with the magnetic or electrostatic actuation of the vibrating element formed by the second substrate 3.
- the second substrate 3 is not necessarily a resonant element. It is possible to follow the deformation of the second substrate 3 to follow the pressure difference between the two faces of the second substrate. It is also possible to follow the atmosphere in the cavity by following the value of electrical capacity which exists between the electrode 8 and the second substrate 3. In all these applications, it is particularly advantageous to have a good control of the air gap between the second substrate 3 and the electrode 8 to reduce the calibration operations and take advantage of greater measurement dynamics.
- the stud also makes it possible to define the air gap between the two substrates and therefore between the electrode 8 and the second substrate 3.
- the first substrate 1 is surmounted by a stud 2 which is advantageously disposed at least partially on an electrical contact 8.
- the electrical contact 8 may project from the first substrate 1.
- the spacer (s) A have a height greater than the assembly formed by the electrode 8 and the pad 2.
- the second substrate 3 is deposited at a distance from the first substrate 1 bearing on the multiple spacer (s) A.
- the second substrate 3 is at a distance from the pad 2.
- the thickness of the pad 2 makes it possible to define the air gap which separates the first substrate 1 and the second substrate 3.
- the solidification treatment is for example a heat treatment which will cause the polymerization of a spacer A made of polymer material. It is also possible to provide that the solidification treatment uses polymerization by optical means, or by electronic means or by elimination of a solvent present in the spacer A. After the solidification treatment, the second substrate 3 is in contact from stud 2.
- the spacer A is metallic.
- the pad 2 can undergo a thermal annealing which transforms the pad 2 and which releases the second substrate 3.
- the transformation of the pad 2 allows a possible displacement of the second substrate 3 relative to the first substrate 1. It is then possible to initiate a vibration of the second substrate 3.
- the stud 2 makes it possible to define the air gap between the second substrate 3 and the electrode 8 and then to actuate the second substrate 3 or to follow a physical quantity between the electrode and the second substrate.
- the height of the pad 2 is identical to the height of the spacer A so that the substrate 3 is in equilibrium before the step of transforming the pad 2.
- a stud 2 is formed on the surface of the first substrate 1, for example on a covering layer 11.
- Two spacers A defining two side walls are then formed so as to define the two opposite side walls d 'a canal.
- the two side walls A are spaced from each other and come into contact with the stud 2.
- the two side walls A are separated from each other by the stud 2 and they are spaced d 'a distance equal to the width of the stud 2.
- the two side walls A can be formed before or after the formation of the pad 2. However, it is preferable to form the pad 2 before forming the side walls A.
- the thickness or height of the stud 2 is greater than the thickness or height of the side walls A.
- the second substrate 3 is deposited and it deforms the top of the pad 2 which protrudes from the side walls A.
- the stress applied by the second substrate 3 causes a lateral deformation of the pad 2 which presses against the side walls A to improve the seal.
- the stud 2 ensures better sealing of the channel on all the contact surfaces.
- the channel is closed by means of the stud 2.
- the application of an annealing configured to pass the stud 2 in the molten liquid state makes it possible to make the channel pass through. For example, it is possible to melt the stud 2 by crossing it with a current so that the latter reaches its melting temperature by Joule effect.
- the pad 2 is made of an electrically conductive material.
- the pad 2 is in the form of a bowl in order to facilitate the deformation of the upper ends of the pad 2 and thus ensure better sealing.
- This configuration also makes it possible to limit the amount of material used to form the pad 2 and also to heat to release the channel.
- the dimensions of the pad 2 and the section of the channel are configured so that the opening of the channel is obtained only when the pressure difference in the channel between the two sides of the pad 2 reaches a threshold value. Below this threshold value, the wettability forces which exist in the molten metal forming the pad 2 are not sufficient to open the valve formed by the pad 2.
- the opening of the channel can be obtained by means of a rod passing through the molten material.
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Abstract
Description
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Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| FR1856171A FR3083643B1 (fr) | 2018-07-04 | 2018-07-04 | Procede de realisation d'un dispositif electronique |
| PCT/EP2019/067944 WO2020007960A1 (fr) | 2018-07-04 | 2019-07-04 | Dispositif electronique et son procede de realisation |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| EP3818563A1 true EP3818563A1 (fr) | 2021-05-12 |
Family
ID=66530066
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| EP19745566.0A Withdrawn EP3818563A1 (fr) | 2018-07-04 | 2019-07-04 | Dispositif electronique et son procede de realisation |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US20210125957A1 (fr) |
| EP (1) | EP3818563A1 (fr) |
| FR (1) | FR3083643B1 (fr) |
| WO (1) | WO2020007960A1 (fr) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114898671B (zh) * | 2022-05-05 | 2024-09-24 | 昆山国显光电有限公司 | 邦定结构及显示装置 |
Family Cites Families (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3271631B2 (ja) * | 1993-02-18 | 2002-04-02 | 太平洋セメント株式会社 | 半導体装置実装用基板 |
| US7332819B2 (en) * | 2002-01-09 | 2008-02-19 | Micron Technology, Inc. | Stacked die in die BGA package |
| US20030111720A1 (en) * | 2001-12-18 | 2003-06-19 | Tan Lan Chu | Stacked die semiconductor device |
| JP4669270B2 (ja) * | 2004-12-02 | 2011-04-13 | 富士通株式会社 | Rfidタグおよびその製造方法 |
| FR2905518B1 (fr) | 2006-08-29 | 2008-12-26 | Commissariat Energie Atomique | Puce microelectronique a faces laterales munies de rainures et procede de fabrication |
| FR2928491A1 (fr) | 2008-03-06 | 2009-09-11 | Commissariat Energie Atomique | Procede et dispositif de fabrication d'un assemblage d'au moins deux puces microelectroniques |
| FR2954588B1 (fr) * | 2009-12-23 | 2014-07-25 | Commissariat Energie Atomique | Procede d'assemblage d'au moins une puce avec un element filaire, puce electronique a element de liaison deformable, procede de fabrication d'une pluralite de puces, et assemblage d'au moins une puce avec un element filaire |
| FR2971081B1 (fr) * | 2011-02-02 | 2013-01-25 | Commissariat Energie Atomique | Procédé de fabrication de deux substrats relies par au moins une connexion mécanique et électriquement conductrice obtenue |
| FR3034566A1 (fr) * | 2015-03-31 | 2016-10-07 | Commissariat Energie Atomique | Procede d'assemblage de substrats |
-
2018
- 2018-07-04 FR FR1856171A patent/FR3083643B1/fr not_active Expired - Fee Related
-
2019
- 2019-07-04 WO PCT/EP2019/067944 patent/WO2020007960A1/fr not_active Ceased
- 2019-07-04 EP EP19745566.0A patent/EP3818563A1/fr not_active Withdrawn
- 2019-07-04 US US17/257,651 patent/US20210125957A1/en not_active Abandoned
Also Published As
| Publication number | Publication date |
|---|---|
| WO2020007960A1 (fr) | 2020-01-09 |
| US20210125957A1 (en) | 2021-04-29 |
| FR3083643A1 (fr) | 2020-01-10 |
| FR3083643B1 (fr) | 2023-01-13 |
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