EP3791408B1 - Procédé de fabrication d'un piège à atomes ainsi que piège à atomes - Google Patents

Procédé de fabrication d'un piège à atomes ainsi que piège à atomes Download PDF

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Publication number
EP3791408B1
EP3791408B1 EP19710350.0A EP19710350A EP3791408B1 EP 3791408 B1 EP3791408 B1 EP 3791408B1 EP 19710350 A EP19710350 A EP 19710350A EP 3791408 B1 EP3791408 B1 EP 3791408B1
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EP
European Patent Office
Prior art keywords
electric conductor
contacting
layer
conductor element
substrate
Prior art date
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EP19710350.0A
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German (de)
English (en)
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EP3791408A1 (fr
Inventor
Amado Bautista-Salvador
Christian Ospelkaus
Martina Wahnschaffe
Jonathan Morgner
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Bundesministerium fuer Wirtschaft und Energie
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Bundesministerium fuer Wirtschaft und Energie
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J49/00—Particle spectrometers or separator tubes
    • H01J49/0013—Miniaturised spectrometers, e.g. having smaller than usual scale, integrated conventional components
    • H01J49/0018—Microminiaturised spectrometers, e.g. chip-integrated devices, MicroElectro-Mechanical Systems [MEMS]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J49/00—Particle spectrometers or separator tubes
    • H01J49/26—Mass spectrometers or separator tubes
    • H01J49/34—Dynamic spectrometers
    • H01J49/42—Stability-of-path spectrometers, e.g. monopole, quadrupole, multipole, farvitrons
    • H01J49/4205—Device types
    • H01J49/422—Two-dimensional RF ion traps
    • H01J49/4225—Multipole linear ion traps, e.g. quadrupoles, hexapoles
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J3/00—Details of electron-optical or ion-optical arrangements or of ion traps common to two or more basic types of discharge tubes or lamps

Definitions

  • the invention relates to a method for producing an atomic trap and an atomic trap produced using it.
  • Atom traps are devices for storing neutral atoms and/or ions. In the case of ions, these are usually trapped by means of an electric field and, in the case of neutral atoms, by means of a magnetic field and cooling of the ions or neutral atoms to be trapped in the atom trap. For example, the method of laser cooling can be used for cooling.
  • Storage means in particular that the neutral atoms or ions do not leave the atomic trap or the respective field for a period of at least one second, preferably at least one minute, more preferably at least 10 minutes.
  • an atom trap is understood to be a device for generating such an electrical and/or magnetic field, by means of which atoms or ions can be stored.
  • any necessary cooling devices are not part of the claimed invention.
  • Inhomogeneous magnetic fields or inhomogeneous electric fields are preferably used to capture or store the neutral atoms or ions. It is possible, for example by means of photoionization, to first convert neutral atoms into ions and then store them in electric fields.
  • the ions can in particular be monoatomic, but also polyatomic ions, ie molecular ions.
  • Atomic traps are used, among other things, in quantum information processing, for example as quantum sensors or for quantum sensors. They can be formed from microtechnical structures. Here it is possible, for example and particularly advantageous to form multilayer atom traps. These have a plurality of superimposed layers, which in turn each have electrical conductor structures. It is necessary here for the individual layers to be reproducible and to be manufacturable with small deviations, since irregularities propagate and add up when the layers are applied one on top of the other. In the prior art, this often leads to manufacturing difficulties.
  • the different conductor structures in the individual layers should be conductively connected to one another, which is difficult to achieve in the prior art, especially in a process with the necessary reproducibility and freedom from irregularities and the required layer thicknesses and material combinations.
  • nuclear traps are very susceptible to electrical interference fields in particular.
  • Atomic traps require an electrical and/or magnetic field that is as well-defined as possible in terms of time, in particular that is constant, in order to store atoms and/or ions.
  • interference fields can be minimized, for example, by realizing large aspect ratios, so that charges accumulated on exposed dielectrics below the conductor layer generate the smallest possible electric fields at the location above the structure where the atoms are stored.
  • Aspect ratio is to be understood in particular as the height of the electrical conductor structures in comparison to the gaps between the same conductor elements.
  • the object of the present invention is to improve the production of nuclear traps.
  • the invention solves the problem by a method with the following steps: (a) application of an electrically conductive starting layer to a substrate, (b) application of at least one electrical conductor element to the starting layer by means of electrochemical deposition and/or in the lift-off method, (c ) Application of at least one contacting element by means of electrochemical deposition and/or in the lift-off process, so that the at least one contacting element is electrically conductively connected to the at least one electrical conductor element, (d) removing the starting layer in areas in which no electrical conductor element was applied , (e) applying an insulating layer which at least partially covers the at least one electrical conductor element and the at least one contacting element, (f) planarizing the insulating layer and exposing the at least one contacting element and (g) applying at least one further electrical conductor element by means of electro chemical deposition and/or in the lift-off process, so that the at least one further electrical conductor element is electrically conductively connected to the at least one contacting element.
  • the invention also achieves the object by means of an atom trap which is produced using the method according to the invention and which has at least one electrical conductor element applied by electrochemical deposition and/or in the lift-off method and at least one electrical conductor element applied by electrochemical deposition and/or in the lift-off method.
  • Method applied contacting element wherein the at least one electrical conductor element and the at least one contacting element have a layer thickness of at least 1 micron and an aspect ratio of at least 1.
  • the substrate is, for example, a wafer made of silicon dioxide or corundum.
  • the substrate can also be formed from a body made of electrically conductive material, for example silicon, which has an insulating, ie electrically non-conductive, coating, for example made of silicon dioxide or silicon nitride.
  • an electrically conductive starting layer is applied to this substrate, preferably made of an alloy or a metal, such as, for example copper, silver or nickel.
  • the starting layer is preferably formed from gold or an alloy containing gold.
  • Gold is little used in semiconductor technology because it has several disadvantageous properties. For example, it can contaminate laboratories designed as clean rooms, so that CMOS semiconductors can no longer be produced in laboratories that work with gold, for example. In addition, gold is very soft, difficult to polish, in particular mechanically, and is also expensive.
  • gold is preferably used because, for example, it is not very reactive and has only a low tendency for adsorbates to adhere.
  • At least one electrical conductor element is applied to the starting layer by means of electrochemical deposition and/or in the lift-off process.
  • the electrically conductive starting layer functions in particular as a counter-electrode for the electrochemical deposition, which is also referred to as galvanic deposition.
  • a structure is preferably first applied to the starting layer by means of photolithography.
  • the photoresist can be a positive or negative resist, for example, with the at least one electrical conductor element being applied by means of electrochemical deposition in the areas in which the starting layer is not covered by photoresist.
  • a further layer of photoresist is applied by means of photolithography, the photoresist applied in the previous step preferably having been removed beforehand.
  • photoresist which can be positive or negative resist. These are formed by electrochemical deposition in the areas where there is no photoresist.
  • These areas are located in particular above the conductor elements applied to the starting layer, so that the contacting elements are electrically conductively connected to them.
  • the starting layer is then removed in areas where no electrical conductor element was applied. Before this, in particular the previously applied photoresist is removed and the starting layer is removed, for example by wet or dry etching.
  • the substrate is preferably uncovered in all areas in which there is no electrical conductor element. Alternatively, only narrow areas of the starting layer are removed, so that the electrical conductor elements that are spaced apart from one another are no longer electrically conductively connected to one another via the starting layer, and areas in which the starting layer has not been removed remain.
  • the starting layer can also be removed before the at least one contacting element is applied.
  • the insulating layer preferably consists of a dielectric or a mixture of different dielectrics, such as a polyimide, a silicone or a polymer made from or with benzocyclobutene (BCB).
  • a dielectric or a mixture of different dielectrics such as a polyimide, a silicone or a polymer made from or with benzocyclobutene (BCB).
  • the insulating layer can be applied, for example, by means of spin coating. This is particularly preferred when the dielectric constituting the insulating layer is a polyimide or a polymer made from or with BCB.
  • the insulating layer is applied in such a way that it at least partially, preferably completely, covers the at least one conductor element and the at least one contacting element.
  • the insulating layer encloses the at least one conductor element and the at least one contacting element, preferably completely above the substrate and/or the starting layer.
  • the invention also solves the problem by a method with the steps: (a) applying an electrically conductive starting layer to a substrate, (b) applying at least one electrical conductor element to the starting layer by means of electrochemical deposition and/or in the lift-off method, ( c) removing the starting layer in areas where no electrical conductor element is applied, (d) applying an insulating layer which at least partially, in particular completely covers, the at least one conductor element, (e) removing the insulating layer in predetermined areas above the at least one electrical conductor element , so that the at least one conductor element is partially uncovered, (f) application of via elements by means of electrochemical deposition and/or in the lift-off process in the areas in which the at least one electrical conductor element is uncovered, and (g) application of at least one additional one electrical conductor element mi by means of electrochemical deposition and/or in the lift-off process, so that the at least one further electrical conductor element is electrically conductively connected to the at least one contacting element.
  • step (e) is carried out, namely the removal of the insulating layer in a predetermined area above the at least one electrical conductor element so that the at least one conductor element is exposed
  • the insulating layer is planarized, in particular by chemical-mechanical polishing.
  • a starting layer can be applied, which is covered with a photoresist, in particular at the points where no contact elements are provided. All statements made on the subject matter of the main claim also apply accordingly to this embodiment of the method according to the invention.
  • the insulating layer does not have a flat surface, but rather an uneven surface structure. This corresponds in particular to the underlying structures, so that the insulating layer has a greater height above the substrate in the areas in which electrical conductor elements and/or contacting elements are located than in those areas in which the insulating layer merely covers the substrate.
  • the insulating layer has a structure that corresponds to the underlying structure of the substrate, the remaining starting layer, the electrical conductor elements and the contacting elements.
  • the insulating layer is planarized and the at least one contacting element is exposed.
  • Planarization means in particular that the surface of the insulating layer is smoothed, so that it is in particular as flat as possible and preferably runs parallel to the surface of the substrate.
  • the insulating layer is preferably planarized by chemical-mechanical polishing.
  • the at least one contacting element is exposed in particular in one of the two alternative methods presented below.
  • the layer thickness of the material of the insulating layer covering the at least one contacting element is as small as possible. This layer thickness is preferably less than 500 nm, particularly preferably less than 250 nm.
  • photoresist is preferably first applied to the planarized insulating layer.
  • This photoresist can in turn be a positive or negative resist.
  • the photoresist is preferably applied to the insulating layer in such a way that it is not located in the areas below which the at least one contacting element is located. Particularly preferably, only areas below which the at least one contacting element is located remain free of photoresist.
  • the dielectric, ie the insulating layer, above the at least one contacting element can then be removed, for example by means of wet or dry etching, and this can thus be uncovered.
  • the resulting height difference between the insulating layer and the at least one contacting element compared to the substrate is preferably at most 500 nm, particularly preferably at most 250 nm.
  • the previously applied photoresist is preferably removed.
  • a further electrically conductive starting layer is particularly preferably applied, which is in particular located both on the insulating layer and on the previously exposed contacting elements.
  • each additional electrical conductor element is therefore electrically conductively connected to at least one underlying contacting element.
  • connection is preferably made via the applied further starting layer, so that the at least one further electrical conductor element and the at least one contacting element are not directly connected to one another, but are electrically conductively connected to one another via the further starting layer.
  • the electrical conductor elements and/or the contacting elements are preferably made of gold or copper or an alloy containing gold and/or copper.
  • Gold has a high electrical conductivity.
  • it is not very reactive and has a low tendency for adsorbates to stick. These can lead to the emergence of interference fields, which make it difficult or even impossible to capture the atoms and/or ions.
  • the at least one contacting element is preferably exposed by planarizing the insulating layer in step (f).
  • the insulating layer is planarized until it no longer covers the at least one contacting element.
  • material of the at least one contacting element it is possible in particular for material of the at least one contacting element to be removed by planarization in addition to the material of the insulating layer.
  • this method can, in the case of contacting elements made of soft material, such as pure gold, lead to smearing of the contacting element as soon as it is reached by the polishing wheel.
  • This method is therefore preferably used with sufficiently hard materials for the contacting element, such as copper or nickel or alloys, in particular gold alloys, with sufficient hardness.
  • the method preferably has a step (h) which, in particular, follows step (g) of the main claim, namely the application of at least one further electrical conductor element by means of electrochemical deposition and/or in the lift-off process, so that the at least one further electrical conductor element is electrically is conductively connected to the at least one contacting element is carried out.
  • Step (h) comprises removing the insulating layer in areas where no further electrical conductor element has been applied, so that gaps are formed.
  • a further electrically conductive starter layer has been applied to the insulating layer and the via elements, this is first removed in the areas in which no further electrical conductor element has been applied. This can also be done in the same step in which the insulating layer is removed in these areas. In other words, this exposes underlying layers. The insulating layer is removed, for example, until it reaches an underlying electrical conductor element or until it reaches the substrate.
  • a gap is to be understood here in particular as a material-free space which is delimited laterally in at least two spatial directions parallel to the substrate by applied structures.
  • it can be a material-free space that is completely surrounded, that is to say laterally in all four spatial directions parallel to the substrate.
  • it can also be a channel that is only delimited on two sides and runs through the atom trap from one side of the substrate to another side of the substrate parallel to the substrate.
  • such a gap forms a channel that does not completely run through the atomic trap.
  • this channel is surrounded by structures on three sides.
  • the gaps preferably have an aspect ratio of at least 1.
  • Aspect ratio is the height or depth of an object in relation to its smallest lateral extent.
  • the aspect ratio consequently relates to the ratio of the spatial depth of a gap to its smallest width, in particular parallel to the substrate.
  • the depth of a gap is to be understood in particular as a distance perpendicular to the substrate, from the lowest edge of a structural element laterally delimiting the gap to the bottom of the gap, which runs in particular parallel to this edge and is formed, for example, by an electrical conductor element or the substrate.
  • the gaps are as narrow as possible. They therefore preferably have an aspect ratio of at least 3, more preferably at least 4, even more preferably at least 5.
  • the method comprises the step of repeating steps (c) to (g) or (c) to (h) so that a multilayer atom trap is obtained.
  • the manufacturing method according to this embodiment is after the atomic trap Performance of steps (a) to (g) or (a) to (h) not completed. Rather, some of the steps are repeated at least once.
  • Further contacting elements are therefore preferably applied by means of electrochemical deposition and/or in the lift-off process, which are electrically conductively connected to the electrical conductor elements applied in step (g).
  • step (d) in particular does not have to be carried out.
  • Steps (c) to (g) or (c) to (h) are preferably carried out at least once, more preferably at least five times, more preferably at least ten times and more preferably at least twenty times.
  • a multi-layer structure of conductor elements is created, which are connected to one another via via elements in a direction perpendicular to the substrate.
  • the aspect ratio is preferably at least 1, more preferably at least 3, more preferably at least 4 and most preferably at least 5 means in particular the aspect ratio of the resulting gaps, i.e. in the finished, preferably multilayer atom trap.
  • An aspect ratio that is as large as possible is advantageous since it is less likely that interfering substances or adsorbates can penetrate these gaps and settle there. Such interfering substances or adsorbates, for example, allow the formation of electrical interference fields that make it difficult or even prevent the capture of neutral atoms or ions in the atom trap.
  • An aspect ratio that is as large as possible is also advantageous because dielectrics can carry surface charges in the lower region of the gap. These surface charges, when buried so deep in the interstices, create only small electric fields at the location of the stored atoms and thus disturb them less.
  • the electrical conductor elements are preferably applied with a layer thickness of at least 1 ⁇ m and/or the insulating layer and/or the at least one contacting element are applied with a layer thickness of at least 1 ⁇ m.
  • the contacting elements preferably also have a layer thickness of at least 1 ⁇ m.
  • Such a layer thickness of at least 1 ⁇ m can be realized, for example, with the method of electrochemical deposition, which is otherwise disadvantageous in microtechnology. This usually has the disadvantage that the elements produced are too thick and too irregular for many microtechnical applications.
  • the insulating layer preferably also has a layer thickness of at least 1 ⁇ m.
  • the thickness of the insulating layer preferably corresponds to the layer thickness of the contacting elements. It is preferably the same size or larger.
  • the layer thickness of the electrical conductor elements and/or the contacting elements and/or the insulating layer is preferably more than 3 ⁇ m, more preferably more than 5 ⁇ m and particularly preferably more than 10 ⁇ m.
  • the conductor elements and/or the contacting elements preferably have an aspect ratio of at least 1.
  • the spatial extent in the direction perpendicular to the substrate is at least equal to the smallest lateral extent, which in particular runs parallel to the substrate.
  • the conductor elements and/or the contacting elements particularly preferably have an aspect ratio of at least 3, more preferably at least 4, more preferably at least 5.
  • the substrate preferably has a recess for passing an atomic beam through, or such a recess is made in the substrate.
  • a recess can be, for example, a channel that runs through the substrate completely from a bottom to a top and is thus surrounded by the substrate in all four spatial directions parallel to the substrate.
  • the recess it is also possible for the recess to be surrounded by the substrate in only three spatial directions.
  • An atom beam can be directed through such a recess, from which atoms or ions are captured by the atom trap.
  • the atomic beam can also be an ion beam.
  • Such a beam can be generated, for example, by selectively heating a metal wire, such as a beryllium wire. It is also possible to generate ions from an atomic beam by means of photoionization and then capture and store them.
  • the substrate preferably has at least one substrate via element or this is introduced into the substrate.
  • the substrate has an upper side and an underside, with the method according to the invention being carried out in particular on the upper side of the substrate.
  • the at least one electrically conductive substrate via element preferably extends from the top to the bottom of the substrate.
  • the electrical conductor elements are preferably applied to the upper side of the substrate in such a way that they are electrically conductively connected to this at least one substrate via element.
  • the power source required for energizing the electrical conductor elements can be connected to the rear of the substrate.
  • the electrical current can then be introduced into the at least one electrical conductor element via the substrate via element. It is also possible that only a potential, in particular static voltages, is present at the electrical conductor elements. In other words, energizing the at least one electrical conductor element is possible, but not necessary.
  • An atom trap according to the invention is characterized in that it has conductor elements and contacting elements whose layer thickness is at least 1 ⁇ m. In particular, this only becomes possible as a result of the electrochemical deposition during production. Other manufacturing methods, such as sputtering, lead in particular to significantly lower layer thicknesses and are therefore technically not useful.
  • a high layer thickness is advantageous because, in particular, traps for neutral atoms must be able to carry high currents in order to provide field configurations with a stable and very large spatial inhomogeneity for storing the atoms.
  • the conductor elements and the contacting elements have an aspect ratio of at least 1, so that narrow structures are formed in particular.
  • Any gaps that may be formed preferably also have aspect ratios of at least 1. This ensures in particular that charges accumulated on dielectric layers in the wall region of the gaps below conductor elements cause interference fields that are as small as possible at the location of the atoms.
  • the atomic trap according to the invention is also characterized in particular by the fact that its structure can be scaled particularly easily. In other words, in particular almost any number of layers, in particular at least 10 layers, can be formed without irregularities propagating in such a way that a functional structure is no longer provided.
  • the metallic starting layer 2 here is in 1 already applied to the substrate 1, in particular over the entire surface and by means of gas phase deposition.
  • Photoresist 3 is then applied to this, in particular by means of spin coating or spray coating.
  • the photoresist is preferably either negative resist or positive resist.
  • positive resist a mask is used which is translucent at the points at which the subsequent electrical conductor elements 4 (4.1, 4.2) are to be arranged. Exposure causes the positive resist to become liquid or soluble in the exposed areas, so that it can be removed in these areas. As a result, the photoresist 3 is only arranged in the areas in which no electrical conductor elements 4 are to be applied. In this respect, it serves as a form or template for applying the at least one electrical conductor element 4.
  • the areas of the mask in which the subsequent electrical conductor elements 4 are not to be applied are translucent. In these areas, the photoresist 3 hardens under exposure. In the non-exposed areas, it can be removed accordingly and a mold or template is created for applying the at least one electrical conductor element 4.
  • the starting layer 2 acts as a counter-electrode during the galvanic deposition of the electrical conductor elements 4.1 and 4.2.
  • photoresist 3 which serves as a mold or template for the contacting elements 6 .
  • the previously applied photoresist can first be removed.
  • the contacting elements 6, in this case the three contacting elements 6.1 to 6.3, are applied by means of electrolytic deposition in the areas in which no photoresist 3 is present.
  • the photoresist 3 is then in particular completely removed. This can be done using a suitable solvent such as acetone.
  • the starting layer 2 is removed in the areas in which no conductor elements 4 are applied to it. It is preferably possible to remove the starting layer 2 and the photoresist 3 in a single work step.
  • the starting layer 2 can already be removed before the contacting elements 6 are applied.
  • An insulating layer 7 is then applied.
  • this consists of a polyimide and is applied by means of spin coating.
  • the insulating layer preferably completely covers the previously applied structures. Due to the different heights of the individual structures compared to the substrate 1, the insulating layer has a structure that corresponds in particular to the underlying structures.
  • the height of the insulating layer ie the distance between the surface and the underlying structure, is preferably almost constant. this is in 1 indicated as h1.
  • the absolute height of the insulating layer above the substrate varies and leads to the corresponding structure mentioned.
  • the insulating layer 7 is then planarized. It is preferably planarized by means of chemical-mechanical polishing, so that it then preferably has a constant height h2 above the substrate 1. Consequently, material of the insulating layer is removed.
  • the insulating layer 7 is planarized only to the extent, that is to say only so much material is removed, that the contacting elements 6.1 to 6.3 are still covered by the insulating layer 7.
  • the height of these the contacting elements 6.1. to 6.3 covering layer is in particular as small as possible. It is preferably less than 250 nm.
  • Photoresist 3 is then applied again, leaving out the areas below which the contacting elements 6.1. to 6.3. In these recessed areas, the insulating layer is removed, for example, by etching or a suitable solvent. Preferably, a removal method is used that does not attack the contacting elements 6 .
  • the height is still the, in particular constant, height h2.
  • a further electrically conductive starting layer 12 is then applied to the insulating layer 7 and the exposed contacting elements 6.1 to 6.3.
  • Photoresist 3 is again applied to this, which serves as a mold or template for the further electrical conductor elements 14.1 and 14.2. These are applied to the further starting layer 12 by means of electrochemical deposition.
  • the photoresist is then removed.
  • the further starting layer 12 is also removed in the areas in which no further electrical conductor element 14 is applied. This is done in two separate steps or preferably in one step.
  • the insulating layer 7 is now uncovered. This is then also removed, for example by etching, so that gaps 8 form. These gaps are delimited at the bottom by the electrical conductor elements 4 and/or the substrate. In the present case, the gap 8.1 is delimited by the electrical conductor element 4.1. The gap indicated at the edge 8.2. is, however, limited by the substrate 1.
  • Further contacting elements 16 can then be applied to the conductor elements 14 in order to obtain a multilayer atom trap.
  • the process steps outlined above can be repeated several times for this purpose.
  • figure 3 shows an atomic trap 20 according to the invention.
  • a plurality of multi-layer conductor structures 21 to 23 spatially separated from one another are shown schematically in this. These were made according to the in figure 1 and 2 applied to the substrate 1 outlined method.
  • the conductor structures 21 to 23 are preferably not conductively connected to one another and each have their own electrical connection 29 for energizing.
  • the conductor structures 21 to 23 serve to bring about an, in particular inhomogeneous, electric field above the atom trap.
  • ions 24.1 to 24.3 are captured and stored. These ions were previously identified using photoionization generated from neutral atoms.
  • a laser beam 25 is used for photoionization.
  • the conductor structures 22.1 and 22.2 are connected to AC voltage and the conductor structures 23.1 and 23.2 to ground.
  • the conductor structures 23 it is also possible for the conductor structures 23 to be connected to a non-zero DC voltage.
  • FIG 4 a further embodiment of an atomic trap 20 according to the invention is shown schematically.
  • This atom trap in turn has multilayer conductor structures 21 to 23, with a recess 26 in the form of a channel also being introduced into the substrate 1.
  • An atomic beam 27 is guided through this recess.
  • the atomic beam 27 can be generated by heating a metal wire, for example by heating a beryllium wire at a point to over 1000 K.
  • atoms of the atomic beam are converted into ions 24.1 to 24.3 by means of photoionization, which are stored in the electrical field that is caused by the multilayer conductor structures 21 to 23.
  • the substrate also has substrate through-plating elements 28, via which the multi-layer conductor structures 21 to 23 are energized. At least one substrate via element 28 is preferably assigned to each multilayer conductor structure 21 to 23 . By means of the substrate via elements 28, the current can be supplied in a particularly simple manner from the rear side of the substrate 1.
  • figure 5 shows an exemplary sectional view of a multi-layer atomic trap.
  • the sectional view corresponds to the atomic trap in the figures 1 and 2 illustrated manufacturing process.
  • Further contacting elements 16.1 and 16.2 were applied to the last applied conductor elements 14.1 and 14.2 by means of electrochemical deposition. These are preferably dimensioned identically as the contacting elements 6.1 to 6.3.
  • a further insulating layer 17 was applied by means of spin coating.
  • the contacting elements are exposed and a further starting layer (not shown) follows, which is superimposed on the further contacting elements 16.1 and 16.2 and the further insulating layer 17.
  • figure 5 It can be seen that the aspect ratio, that is to say the ratio of the width to the height of the gaps 8.1 and 8.2, increases as a result of the application of further layers. Gaps 8.1 and 8.2 in figure 5 a greater height than in figure 2 , resulting in a larger aspect ratio with the same width.

Claims (11)

  1. Procédé de fabrication d'un piège à atomes (20), comprenant les étapes consistant à :
    (a) appliquer une couche de départ électriquement conductrice (2) sur un substrat (1),
    (b) appliquer au moins un élément conducteur électrique (4) sur la couche de départ (2) par dépôt électrochimique et/ou par un procédé de lift-off,
    (c) appliquer au moins un élément de mise en contact (6) par dépôt électrochimique et/ou par le procédé de lift-off, de sorte qu'au moins un élément de mise en contact (6) est relié de manière électriquement conductrice audit au moins un élément conducteur électrique (4),
    (d) éliminer la couche de départ (2) dans les zones où aucun élément conducteur électrique (4) n'a été appliqué,
    (e) appliquer une couche isolante (7) qui recouvre au moins partiellement ledit au moins un élément conducteur électrique (4) et ledit au moins un élément de mise en contact (6),
    (f) aplanir la couche isolante (7) et mettre à découvert ledit au moins un élément de mise en contact (6), et
    (g) appliquer au moins un autre élément conducteur électrique (14) par dépôt électrochimique et/ou par un procédé de lift-off, de sorte que ledit au moins un autre élément conducteur électrique (14) est relié de manière électriquement conductrice audit au moins un élément de mise en contact (6).
  2. Procédé de fabrication d'un piège à atomes (20), comprenant les étapes consistant à :
    (a) appliquer une couche de départ électriquement conductrice (2) sur un substrat (1),
    (b) appliquer au moins un élément conducteur électrique (4) sur la couche de départ (2) par dépôt électrochimique et/ou par un procédé de lift-off,
    (c) éliminer la couche de départ (2) dans les zones où aucun élément conducteur électrique (4) n'a été appliqué,
    (d) appliquer une couche isolante (7) qui recouvre au moins partiellement, en particulier complètement ledit au moins un élément conducteur électrique (4),
    (e) éliminer la couche isolante (7) dans des zones prédéterminées au-dessus dudit au moins un élément conducteur électrique (4), de telle sorte que ledit au moins un élément conducteur électrique (4) est partiellement mis à découvert,
    (f) appliquer des éléments de mise en contact (6) par dépôt électrochimique et/ou par un procédé de lift-off dans les zones où ledit au moins un élément conducteur électrique (4) est mis à découvert, et
    (g) appliquer au moins un autre élément conducteur électrique (14) par dépôt électrochimique et/ou par un procédé de lift-off, de sorte que ledit au moins un autre élément conducteur électrique (14) est relié de manière électriquement conductrice audit au moins un élément de mise en contact (6).
  3. Procédé selon l'une des revendications 1 et 2, caractérisé en ce que les éléments conducteurs électriques (4) et/ou les éléments de mise en contact (6) sont en or ou en cuivre, ou en un alliage contenant de l'or et/ou du cuivre.
  4. Procédé selon la revendication 1, caractérisé par l'étape consistant à :
    mettre à découvert ledit au moins un élément de mise en contact (6) par l'aplanissement de la couche isolante (7) à l'étape (f).
  5. Procédé selon l'une des revendications précédentes, caractérisé par l'étape consistant à :
    (h) éliminer la couche isolante (7) dans des zones où aucun autre élément conducteur électrique (14) n'a été appliqué, de manière à former des interstices (8).
  6. Procédé selon la revendication 4, caractérisé en ce que les interstices (8) présentent un rapport d'aspect d'au moins 1.
  7. Procédé selon l'une des revendications précédentes, caractérisé par l'étape consistant à :
    répéter les étapes (c) à (g) ou (c) à (h) de manière à obtenir un piège à atomes multicouche (20).
  8. Procédé selon l'une des revendications précédentes, caractérisé en ce que les éléments conducteurs électriques (4, 14) sont appliqués avec une épaisseur de couche d'au moins 1 µm, et/ou la couche isolante (7) et/ou ledit au moins un élément de mise en contact (6) est appliqué(e) avec une épaisseur de couche d'au moins 1 µm.
  9. Procédé selon l'une des revendications précédentes, caractérisé en ce que les éléments conducteurs (4, 14) et/ou les éléments de mise en contact (6, 16) sont appliqués avec un rapport d'aspect d'au moins 1.
  10. Procédé selon l'une des revendications précédentes, caractérisé en ce que le substrat (1) présente un évidement (26) pour le passage d'un faisceau d'atomes (27), ou un tel évidement (26) est réalisé dans le substrat (1).
  11. Piège à atomes (20) fabriqué par un procédé selon à l'une des revendications 1 à 9, dans lequel ledit au moins un élément conducteur électrique et ledit au moins un élément de mise en contact présentent une épaisseur de couche d'au moins 1 µm et un rapport d'aspect d'au moins 1.
EP19710350.0A 2018-05-09 2019-03-04 Procédé de fabrication d'un piège à atomes ainsi que piège à atomes Active EP3791408B1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE102018111220.3A DE102018111220B3 (de) 2018-05-09 2018-05-09 Verfahren zum Herstellen einer Atomfalle sowie Atomfalle
PCT/EP2019/055314 WO2019214863A1 (fr) 2018-05-09 2019-03-04 Procédé de fabrication d'un piège à atomes ainsi que piège à atomes

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EP3791408A1 EP3791408A1 (fr) 2021-03-17
EP3791408B1 true EP3791408B1 (fr) 2022-05-11

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EP (1) EP3791408B1 (fr)
DE (1) DE102018111220B3 (fr)
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DE102022129825B3 (de) 2022-11-11 2023-12-21 Dr. Ing. H.C. F. Porsche Aktiengesellschaft Batterie und Verfahren zu deren Überwachung

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WO2007052273A2 (fr) * 2005-11-02 2007-05-10 Ben Gurion University Of The Negev Research And Development Authority Nouveau materiau et procede pour puce a ions integree
US7928375B1 (en) * 2007-10-24 2011-04-19 Sandia Corporation Microfabricated linear Paul-Straubel ion trap
KR101725788B1 (ko) * 2014-10-31 2017-04-12 에스케이 텔레콤주식회사 절연층 노출을 방지한 이온 트랩 장치 및 그 제작 방법
US10141177B2 (en) * 2017-02-16 2018-11-27 Bruker Daltonics, Inc. Mass spectrometer using gastight radio frequency ion guide

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DE102018111220B3 (de) 2019-05-23
WO2019214863A1 (fr) 2019-11-14
EP3791408A1 (fr) 2021-03-17
US11264220B2 (en) 2022-03-01

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