EP3765866B1 - Light receiving device and distance measuring device - Google Patents

Light receiving device and distance measuring device Download PDF

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Publication number
EP3765866B1
EP3765866B1 EP19713590.8A EP19713590A EP3765866B1 EP 3765866 B1 EP3765866 B1 EP 3765866B1 EP 19713590 A EP19713590 A EP 19713590A EP 3765866 B1 EP3765866 B1 EP 3765866B1
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EP
European Patent Office
Prior art keywords
light receiving
field effect
circuit
unit
receiving device
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Application number
EP19713590.8A
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German (de)
English (en)
French (fr)
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EP3765866A1 (en
Inventor
Yasuhiro Shinozuka
Hayato Kamizuru
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Sony Semiconductor Solutions Corp
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Sony Semiconductor Solutions Corp
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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
    • G01S17/00—Systems using the reflection or reradiation of electromagnetic waves other than radio waves, e.g. lidar systems
    • G01S17/02—Systems using the reflection of electromagnetic waves other than radio waves
    • G01S17/06—Systems determining position data of a target
    • G01S17/08—Systems determining position data of a target for measuring distance only
    • G01S17/10—Systems determining position data of a target for measuring distance only using transmission of interrupted, pulse-modulated waves
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
    • G01S17/00—Systems using the reflection or reradiation of electromagnetic waves other than radio waves, e.g. lidar systems
    • G01S17/02—Systems using the reflection of electromagnetic waves other than radio waves
    • G01S17/06—Systems determining position data of a target
    • G01S17/08—Systems determining position data of a target for measuring distance only
    • G01S17/32—Systems determining position data of a target for measuring distance only using transmission of continuous waves, whether amplitude-, frequency-, or phase-modulated, or unmodulated
    • G01S17/36—Systems determining position data of a target for measuring distance only using transmission of continuous waves, whether amplitude-, frequency-, or phase-modulated, or unmodulated with phase comparison between the received signal and the contemporaneously transmitted signal
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
    • G01S17/00—Systems using the reflection or reradiation of electromagnetic waves other than radio waves, e.g. lidar systems
    • G01S17/88—Lidar systems specially adapted for specific applications
    • G01S17/89—Lidar systems specially adapted for specific applications for mapping or imaging
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
    • G01S17/00—Systems using the reflection or reradiation of electromagnetic waves other than radio waves, e.g. lidar systems
    • G01S17/88—Lidar systems specially adapted for specific applications
    • G01S17/93—Lidar systems specially adapted for specific applications for anti-collision purposes
    • G01S17/931—Lidar systems specially adapted for specific applications for anti-collision purposes of land vehicles
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
    • G01S7/00—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00
    • G01S7/48—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S17/00
    • G01S7/483—Details of pulse systems
    • G01S7/486—Receivers
    • G01S7/4861—Circuits for detection, sampling, integration or read-out
    • G01S7/4863—Detector arrays, e.g. charge-transfer gates
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
    • G01S7/00—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00
    • G01S7/48—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S17/00
    • G01S7/483—Details of pulse systems
    • G01S7/486—Receivers
    • G01S7/4865—Time delay measurement, e.g. time-of-flight measurement, time of arrival measurement or determining the exact position of a peak
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/02016—Circuit arrangements of general character for the devices
    • H01L31/02019—Circuit arrangements of general character for the devices for devices characterised by at least one potential jump barrier or surface barrier
    • H01L31/02027—Circuit arrangements of general character for the devices for devices characterised by at least one potential jump barrier or surface barrier for devices working in avalanche mode

Definitions

  • the present disclosure relates to a light receiving device and a distance measuring device.
  • a circuit element such as a transistor forming a pixel is shared among a plurality of pixels to reduce the number of circuit elements per pixel (see, for example, PTL 1).
  • US 2016/0044296 A1 is related to a precharged latched pixel cell for a time of flight 3D image sensor.
  • a pixel cell includes a latch having an input terminal and an output terminal. The latch is coupled to provide a latched output signal at the output terminal responsive to the input terminal.
  • a first precharge circuit is coupled to precharge the input terminal of the latch to a first level during a reset of the pixel cell.
  • a single photon avalanche photodiode (SPAD) is coupled to provide a SPAD signal to the input terminal of the latch in response to a detection of a photon incident on the SPAD.
  • SPAD single photon avalanche photodiode
  • a plurality of pixels in a solid-state imaging device each include: a light receiving circuit that includes a light receiving element performing photoelectric conversion, sets, by an exposure signal, a photoelectric time for performing the photoelectric conversion, and outputs a light reception signal depending on whether or not incident light has reached the pixel within the photoelectric time; a counter circuit that counts, as a count value, the number of times the incident light has reached the pixel, based on the light reception signal; a comparison circuit that sets a value corresponding to the count value as a threshold, and sets a comparison signal to an on state in the case where the count value is greater than the threshold; and a storage circuit that stores, as a distance signal, a time signal when the comparison signal is in the on state.
  • EP 3 287 813 discloses an apparatus for detecting illumination levels.
  • This apparatus comprises at least one single photon avalanche diode pixel configured to operate in a first mode to output a digital single photon detection event, the pixel comprising: a single photon avalanche diode; and at least one output transistor configured to provide an analogue output current from the single photon avalanche diode, such that the at least one single photon avalanche diode pixel is further configured to operate in a second mode to output the analogue output current indicating a level of illumination of the pixel.
  • US 20110057736 A1 is concerned with a linear, voltage-controlled ring oscillator with current-mode, digital frequency and gain control.
  • a voltage-controlled ring oscillator one or more controllable current sources generate a bias current in response to a tuning voltage.
  • the ring oscillator circuit transistors can be sized relative to one another to skew the rise and fall times of the ring oscillator output signal with respect to one another.
  • a peak limiter can limit the oscillation amplitude in response to the bias current.
  • a controllable bias current source can include a voltage-to-current converter and one or more groups of digitally controlled current source transistors.
  • a light receiving device including:
  • a distance measuring device including:
  • a light receiving device including:
  • the circuit area per pixel can be reduced, the pixel aperture ratio can be improved while miniaturizing pixels.
  • the recharge control unit is configured to, in a case where photons are incident on one or more light receiving units among light receiving units of a plurality of pixels that share a recharge control unit, perform recharging for all of the light receiving units of the plurality of pixels.
  • the recharge control unit can have an OR circuit that takes the OR of logic signals whose logic is inverted at the time when photons are incident on one or more light receiving units, and can be configured to perform recharging according to an OR signal of the OR circuit.
  • the light receiving device and the distance measuring device of the present disclosure including the preferable configuration described above can have a configuration in which the light receiving unit includes a single photon avalanche diode. At this time, a configuration can be adopted in which a signal is retrieved from a cathode electrode side of the single photon avalanche diode, or a configuration can be adopted in which a signal is retrieved from an anode electrode side.
  • the light receiving device and the distance measuring device of the present disclosure including the preferable configuration described above can have a level conversion unit that converts the level of the OR signal of the OR circuit, and can be configured to output a conversion result of the level conversion unit as information for detecting the photon incidence timing.
  • the light receiving device and the distance measuring device can have an exclusive OR circuit that retrieves the exclusive OR of logic signals whose logic is inverted at the time when photons are incident on one or more light receiving units, and a level conversion unit that converts the level of the exclusive OR signal of the exclusive OR circuit, and can be configured to output the conversion result of the level conversion unit as information for detecting the photon incidence timing.
  • the light receiving device and the distance measuring device of the present disclosure including the preferable configuration described above can have an adder that adds the number of photons incident on a plurality of pixels sharing the recharge control unit, and can be configured to output an addition result of the adder as information for detecting the number of incident photons.
  • each of the input signals of the OR circuit can have a waveform shaping unit that performs processing for increasing the pulse width and outputs the result.
  • the light receiving device and the distance measuring device of the present disclosure including the preferable configuration described above can have a quenching circuit that lowers the applied voltage with respect to the single photon avalanche diode to the breakdown voltage.
  • the quenching circuit can have a second switch unit connected in parallel to a first switch unit, and can be configured to operate according to the output of the light receiving unit.
  • the recharge control unit can have a recharge signal generation circuit that generates a recharge signal for driving the first switch unit. Then, the recharge signal generation circuit can use a ring oscillator. Furthermore, the ring oscillator can be configured by using an asymmetric delay element having different rising delay time and falling delay time.
  • the asymmetric delay element can include a CMOS inverter, and have a P-channel field effect transistor and an N-channel field effect transistor having different sizes. Furthermore, a configuration can be adopted in which the delay time of the asymmetric delay element can be varied.
  • a configuration can be adopted in which, the number of series connections of the transistor having higher on-resistance among the P-channel field effect transistor and the N-channel field effect transistor is variable, and the delay time is set according to the number of series connections.
  • a configuration may be adopted in which the number of parallel connections of the transistor having higher on-resistance is variable, and the delay time can be set according to the number of parallel connections.
  • the light receiving device and the distance measuring device can have a stacked structure in which a first semiconductor substrate on which the light receiving unit is arranged and a second semiconductor substrate on which the recharge control unit is arranged are stacked.
  • Fig. 1 is a schematic configuration diagram showing a distance measuring device according to an embodiment of the present disclosure.
  • a distance measuring device 1 as a measuring method for measuring the distance to a subject 10 which is a measuring object, the time of flight (TOF) method is adopted which measures the time until light (for example, laser light) emitted toward the subject 10 is reflected by the subject 10 and returns.
  • the distance measuring device 1 includes a light source 20 and a light receiving device 30. Then, as the light receiving device 30, a light receiving device according to an embodiment of the present disclosure which will be described later is used.
  • the light source 20 has, for example, a laser driver 21, a laser light source 22, and a diffusing lens 23, and irradiates the subject 10 with laser light.
  • the laser driver 21 drives the laser light source 22 under the control of a control unit 40.
  • the laser light source 22 includes, for example, a semiconductor laser, and emits laser light when driven by the laser driver 21.
  • the diffusing lens 23 diffuses the laser light emitted from the laser light source 22 and irradiates the subject 10.
  • the light receiving device 30 has a light receiving lens 31, a light sensor 32, and a logic circuit 33, and receives reflected laser light that is the irradiated laser light emitted by the laser irradiation unit 20 being reflected by the subject 10 and returning.
  • the light receiving lens 31 condenses the reflected laser light from the subject 10 onto a light receiving surface of the light sensor 32.
  • the light sensor 32 receives the reflected laser light from the subject 10 that has passed through the light receiving lens 31 in units of pixels and performs photoelectric conversion.
  • the control unit 40 is constituted by, for example, a central processing unit (CPU) or the like, and controls the light source 20 and the light receiving device 30, and measures time t until the laser light emitted from the light source 20 toward the subject 10 is reflected by the subject 10 and returns. On the basis of this time t, distance L to the subject 10 can be obtained.
  • a time measurement method a timer is started at the timing of emitting pulse light from the light source 20, the timer is stopped at the timing when the light receiving device 30 receives the pulse light, and the time t is measured.
  • pulse light is emitted from the light source 20 at a predetermined cycle, a cycle when the light receiving device 30 receives the pulse light is detected, and the time t may be measured from the phase difference between the light emission cycle and the light reception cycle.
  • a two-dimensional array sensor (so-called area sensor) in which pixels including a light receiving unit are arranged in a two-dimensional array
  • a one-dimensional array sensor (so-called line sensor) in which pixels including a light receiving unit are linearly arranged can also be used.
  • the light receiving unit of the pixel includes an element that generates a signal in response to the reception of photons, for example, a single photon avalanche diode (SPAD) element. That is, in the light receiving device 30 according to the present embodiment, the light receiving unit of the pixel includes the SPAD sensor. Note that, the light receiving unit is not limited to the SPAD element, and may be various elements such as an avalanche photo diode (APD).
  • APD avalanche photo diode
  • Fig. 3 shows a basic configuration of the light receiving device 30 using a SPAD sensor. Here, the basic configuration for one pixel is shown.
  • a pixel 50 uses the SPAD sensor 51 as a light receiving unit.
  • the SPAD sensor 51 has a cathode electrode connected to a terminal 52 and an anode electrode connected to a low potential-V bd (for example, -10V) side power supply, and generates a signal, specifically, a pulse signal in response to the reception of a photon hv.
  • the SPAD sensor 51 is a high-performance light sensor capable of detecting incidence of single photon with photon detection efficiency (PDE).
  • the pixels 50 including the SPAD sensor 51 are arranged in a two-dimensional array of M rows and N columns on the first semiconductor substrate to constitute a pixel array unit.
  • the first semiconductor substrate in which the pixels 50 are arranged constitutes a sensor chip 71.
  • This sensor chip 71 corresponds to the light sensor 32 in Fig. 2A .
  • a circuit unit 60 is provided for each pixel 50.
  • the circuit unit 60 includes a first switch unit 61, a second switch unit 62, a comparator 63, a recharge control unit 64, and a level conversion unit 65.
  • the first switch unit 61, the second switch unit 62, and the comparator 63 constitute the pixel 50 together with the SPAD sensor 51.
  • the first switch unit 61 is constituted by, for example, a P-channel type field effect transistor, is connected between a high-potential V e side power supply and the terminal 52, and is a recharge switch that operates according to a recharge signal RCHG provided from the recharge control unit 64.
  • the first switch unit 61 recharges the SPAD sensor 51 in response to the recharge signal RCHG.
  • the second switch unit 62 is connected in parallel to the first switch unit 61 and constitutes a quenching circuit that performs quenching operation according to the output of the SPAD sensor 51, more specifically, the output of the comparator 63.
  • the second switch unit 62 as a quench switch stops the avalanche phenomenon by lowering the voltage applied to the SPAD sensor 51 to the breakdown voltage by the quenching operation.
  • the comparator 63 converts the cathode potential of the SPAD sensor 51 to a logic level.
  • a logic signal output from the comparator 63 is supplied to the second switch unit 62 as a quench signal QNCH and is also supplied to the recharge control unit 64 and the level conversion unit 65.
  • the recharge control unit 64 generates the recharge signal RCHG on the basis of the logic signal output from comparator 63. Then, the recharge control unit 64 performs on/off control of the first switch unit 61 on the basis of the recharge signal RCHG.
  • the level conversion unit 65 is a level-down circuit that levels down the potential V e of the logic level output from the comparator 63 to the power supply potential V DD (for example, about 1.1V) of the logic circuit 33 (see Fig. 2B ) in the subsequent stage.
  • V DD power supply potential
  • the potential level-downed by the level conversion unit 65 is derived as a pixel output.
  • processing such as edge detection of the pixel output from the level conversion unit 65 is performed.
  • Fig. 4B shows timing relationships among the cathode potential of the SPAD sensor 51, the quench signal QNCH, and the recharge signal RCHG.
  • the cathode potential of the SPAD sensor 51 is lowered to around 0V by the quenching operation by the second switch unit 62, the avalanche amplification stops. Then, as the logic of the recharge signal RCHG changes from 1 to 0 to 1, the first switch unit 61 is turned on to recharge the SPAD sensor 51. As a result, the cathode potential of the SPAD sensor 51 rises to V e , and the SPAD sensor 51 returns to the initial state.
  • a series of operation described above that is, a series of operation of current flowing in the SPAD sensor 51, potential decreasing of the cathode potential of the SPAD sensor 51, quenching, and recharging of the SPAD sensor 51 is repeated each time a photon enters the SPAD sensor 51.
  • the circuit unit 60 having the above-described configuration is arranged in a two-dimensional array of M rows and N columns on the second semiconductor substrate.
  • the second semiconductor substrate in which the circuit unit 60 is arranged constitutes a circuit chip 72.
  • the circuit chip 72 is stacked on the sensor chip 71. Thereby, in the stacked structure of the sensor chip 71 and the circuit chip 72, the circuit unit 60 is provided for each one pixel 50. In other words, the occupied area of one pixel 50 and the occupied area of one circuit unit 60 are substantially equal.
  • miniaturization of the pixel 50 has been advanced for the purpose of downsizing the chip size.
  • the occupied areas of the pixel 50 and the circuit unit 60 are about the same and the relationship between the pixel 50 and the circuit unit 60 is in a one-to-one relationship, even if the pixel 50 is miniaturized, the occupied area (circuit area) of the circuit unit 60 does not decrease, so that the aperture ratio of the pixel 50 decreases. In other words, the circuit area of the circuit unit 60 becomes a bottleneck for miniaturization of the pixel 50.
  • the recharge control unit 64 is shared among the plurality of pixels 50.
  • the recharge control unit 64 is shared among the plurality of pixels 50 in this way, so that, since the circuit area of the circuit unit 60 per pixel can be reduced, the aperture ratio can be increased while miniaturizing the pixel 50. Furthermore, in a case of a stacked structure (see Fig. 4A ) in which the sensor chip 71 and the circuit chip 72 are stacked, since the circuit area of the circuit unit 60 per pixel can be reduced, the pixel 50 is miniaturized, and further, the size of the chip size can be reduced or the number of pixels can be increased.
  • the technology of the present disclosure is not limited to application to the stacked structure.
  • the technology of the present disclosure is also applicable to a so-called flat structure in which the circuit unit 60 is arranged on the same semiconductor substrate as the pixel array unit in which the pixels 50 are arranged. Details of the chip structure of the stacked structure and the flat structure will be described later.
  • a first embodiment is an example of retrieving a signal from a cathode electrode side of the SPAD sensor 51.
  • Fig. 5 is a circuit configuration of the light receiving device 30 according to the first embodiment.
  • the recharge control unit 64 is shared among four pixels 50 1 to 50 4 .
  • the four pixels 50 1 to 50 4 are four pixels of two columns ⁇ two rows adjacent to each other in the column direction and the row direction in a matrix pixel array.
  • the number of pixels sharing the recharge control unit 64 is not limited to four pixels. This point is similar in each of the embodiments described later.
  • the second switch unit 62 as a quench switch provided for each SPAD sensor 51 is not shown for the sake of simplicity of the drawing. This is similar in each of the embodiments described later.
  • the SPAD sensor 51 1 has a cathode electrode connected to a terminal 52 1 and an anode electrode connected to a low potential (-V bd ) side power supply, respectively. Then, the signal of the SPAD sensor 51 1 is retrieved through the terminal 52 1 from the cathode electrode side. This is similar in the other SPAD sensors 51 2 to 51 4 .
  • a first switch unit 61 1 serving as a recharge switch is constituted by, for example, a P-channel type field effect transistor, is connected between a high-potential (V e ) side power supply and the terminal 52, and operates according to a recharge signal RCHG provided from the recharge control unit 64. This is similar in the other first switch units 61 2 to 61 4 .
  • each cathode electrode of the SPAD sensors 51 1 to 51 4 through the terminals 52 1 to 52 4 are converted to the logical level by comparators 63 1 to 63 4 and then supplied to an input end of the recharge control unit 64.
  • each cathode electrode of the SPAD sensors 51 1 to 51 4 and the input end of the recharge control unit 64 are electrically connected via the terminals 52 1 to 52 4 and the comparators 63 1 to 63 4 , so that the recharge control unit 64 is shared among the four pixels 50 1 to 50 4 .
  • the recharge control unit 64 includes a four-input OR circuit 641 and a recharge signal generation circuit 642.
  • the OR circuit 641 obtains the OR of the logic signals retrieved from each cathode electrode of the SPAD sensors 51 1 to 51 4 supplied through the comparators 63 1 to 63 4 .
  • the OR output of the OR circuit 641 is supplied to the recharge signal generation circuit 642.
  • the recharge signal generation circuit 642 generates the recharge signal RCHG by delaying the OR output of the OR circuit 641 by a predetermined delay time, and supplies the recharge signal RCHG to the first switch units 61 1 to 61 4 .
  • the recharge control unit 64 performs the recharge control in response to the OR signal of the logic signal whose logic is inverted at the time when photons are incident on one or more of the SPAD sensors 51 1 to 51 4 .
  • Fig. 6 shows timing relationships of comparison outputs COMP_1 to COMP_4 of the comparators 63 1 to 63 4 for each of the SPAD sensors 51 1 to 51 4 and the OR output OR out of the OR circuit 641. Quenching based on the quench signal QNCH and recharging based on the recharge signal RCHG are as described in Fig. 4B .
  • the delay time is the delay time of the recharge signal generation circuit 642.
  • the recharge control unit 64 is shared among the four pixels 50 1 to 50 4 , when photons are incident on one or more SPAD sensors among the SPAD sensors 51 1 to 51 4 of the four pixels 50 1 to 50 4 that share the recharge control unit 64, recharge control is performed for all of the SPAD sensors 51 1 to 51 4 . In other words, the recharge control is (collectively) performed for the four pixels 50 1 to 50 4 . In this case, the SPAD sensor on which the photon is not incident may also be recharged.
  • each cathode electrode of the SPAD sensors 51 1 to 51 4 and the input end of the recharge control unit 64 are electrically connected via the terminals 52 1 to 52 4 and the comparators 63 1 to 63 4 , so that the recharge control unit 64 is shared among four pixels 50 1 to 50 4 .
  • the recharge control unit 64 is shared among four pixels 50 1 to 50 4 .
  • a second embodiment is an example of retrieving a signal from an anode electrode side of the SPAD sensor 51.
  • Fig. 7 shows a circuit configuration of the light receiving device 30 according to the second embodiment.
  • the SPAD sensor 51 1 has a cathode electrode connected to a high potential side power supply and an anode electrode connected to the terminal 52 1 , respectively.
  • the power supply potential of the high potential side power supply is set to V bd +V e .
  • the signal of the SPAD sensor 51 1 is retrieved through the terminal 52 1 from the anode electrode side. This is similar in the other SPAD sensors 51 2 to 51 4 .
  • a first switch unit 61 1 serving as a recharge switch is constituted by, for example, an N-channel type field effect transistor, is connected between the terminal 52 1 and a low-potential (V ss ) side power supply, and operates according to the recharge signal RCHG provided from the recharge control unit 64. This is similar in the other first switch units 61 2 to 61 4 .
  • the anode electrodes of the SPAD sensors 51 1 to 51 4 and the input end of the recharge control unit 64 are electrically connected to each other through the terminals 52 1 to 52 4 and the comparators 63 1 to 63 4 . Due to this connection relationship, the recharge control unit 64 is shared among the four pixels 50 1 to 50 4 . Note that, the logic of the comparators 63 1 to 63 4 is inverted from that in the case of the first embodiment.
  • the recharge control unit 64 includes the four-input OR circuit 641, the recharge signal generation circuit 642, and an inverter 643.
  • the OR circuit 641 obtains the OR of the logic signals retrieved from each cathode electrode of the SPAD sensors 51 1 to 51 4 supplied through the comparators 63 1 to 63 4 .
  • the OR output of the OR circuit 641 is supplied to the recharge signal generation circuit 642.
  • the recharge signal generation circuit 642 generates the recharge signal RCHG by delaying the OR output of the OR circuit 641 by a predetermined delay time.
  • the inverter 643 inverts the logic of the recharge signal RCHG generated by the recharge signal generation circuit 642 and supplies the logic to the first switch units 61 1 to 61 4 .
  • the light receiving device 30 according to the second embodiment having the above configuration differs from the light receiving device 30 according to the first embodiment in that the logic of the comparators 63 1 to 634 and the recharge signal RCHG is inverted, the basic circuit operation is the same.
  • a third embodiment is a modification of the first embodiment, and is an example using another circuit configuration as the four-input OR circuit 641.
  • Fig. 8 shows a circuit configuration of the light receiving device 30 according to the third embodiment.
  • the light receiving device 30 has a circuit configuration using two two-input NOR circuits 644, 645 and a two-input NAND circuit 646 instead of the four-input OR circuit 641 of the recharge control unit 64.
  • the NOR circuits 644, 645 and the NAND circuit 646 have the same logic as that of the four-input OR circuit 641, and obtain the OR of the logic signals of the SPAD sensors 51 1 to 51 4 supplied through the comparators 63 1 to 63 4 .
  • circuit configuration including the two NOR circuits 644, 645 and the NAND circuit 646 has been described as an example of the other circuit configuration of the four-input OR circuit 641, the circuit configuration is not limited to this circuit configuration, and other gate circuit configurations can be adopted as long as the logics are equivalent.
  • a fourth embodiment is a modification of the first embodiment, which is a first example of a method of retrieving pixel outputs.
  • Fig. 9 shows a circuit configuration of the light receiving device 30 according to the fourth embodiment.
  • the pixel output is basically the output of each of the four pixels 50 1 to 50 4 .
  • the OR output OR out of the four-input OR circuit 641 is retrieved as a pixel output through the level conversion unit 65.
  • the level conversion unit 65 converts the level of the OR output OR out of the four-input OR circuit 641 to the power supply level of the logic circuit 33 at the subsequent stage, and outputs the information as information for detecting the photon incidence timing (pixel output).
  • the light receiving device 30 according to the fourth embodiment having the above configuration has a circuit configuration in which the level conversion unit 65 and circuits thereafter are also shared among the four pixels 50 1 to 50 4 .
  • the circuit area of the circuit unit 60 per pixel can be reduced as compared with the case where the outputs of the four pixels 50 1 to 50 4 are derived. From the pixel output, the photon incidence timing to the SPAD sensors 51 1 to 51 4 can be detected.
  • a fifth embodiment is a modification of the first embodiment, which is a second example of a method of retrieving pixel outputs.
  • Fig. 10 shows a circuit configuration of the light receiving device 30 according to the fifth embodiment.
  • a four-input EX-OR circuit (exclusive-OR circuit) 66 that obtains the exclusive OR of logic signals whose logic is inverted at the time when photons are incident on one or more of the SPAD sensors 51 1 to 51 4 is used.
  • the EX-OR circuit 66 obtains the exclusive OR of the logic signals of the SPAD sensors 51 1 to 51 4 supplied through the comparators 63 1 to 63 4 .
  • the exclusive logical output EXOR out is retrieved as a pixel output through the level conversion unit 65.
  • the level conversion unit 65 converts the level of the exclusive OR output OR out of the four-input EX-OR circuit 66, and outputs the information as information for detecting the photon incidence timing (pixel output).
  • Fig. 11 shows timing relationships among comparison outputs COMP_1 to COMP_4 of the comparators 63 1 to 63 4 , the OR output OR out of the OR circuit 641, and the exclusive OR output EXOR out of the EX-OR circuit 66.
  • the exclusive OR output EXOR out is used as the pixel output, so that, even if the second SPAD sensor fires before the recharge, the photon incidence timing can be detected.
  • a sixth embodiment is a modification of the fourth embodiment, and is an example of detecting the number of incident photons.
  • Fig. 12 shows the circuit configuration of the light receiving device 30 according to the sixth embodiment.
  • the light receiving device 30 in addition to retrieving information for detecting the incident timing as a pixel output, information for detecting the number of incident photons to the SPAD sensors 51 1 to 51 4 is retrieved as a pixel output.
  • the light receiving device 30 inputs each of the comparison outputs COMP_1 to COMP_4 of the comparators 63 1 to 63 4 to the adder 67 through the level conversion units 65 1 to 65 4 , the number of incident photons is counted by the adder 67, and the addition output ADD out is retrieved as a pixel output (information about the number of incidence).
  • Fig. 13 shows timing relationships among comparison outputs COMP_1 to COMP_4 of the comparators 63 1 to 63 4 , the OR output OR out of the OR circuit 641, and the addition output ADD out of the adder 67.
  • a seventh embodiment is a modification of the first embodiment, and is an example in which the pixel output is retrieved for each pixel.
  • Fig. 14 shows the circuit configuration of the light receiving device 30 according to the seventh embodiment.
  • the comparison outputs COMP_1 to COMP_4 of the comparators 63 1 to 63 4 are retrieved as pixel outputs for each pixel through waveform shaping units 68 1 to 68 4 , respectively.
  • the light receiving device 30 has the waveform shaping units 68 1 to 68 4 that performs processing of increasing the pulse width for each of the comparison outputs COMP_1 to COMP_4 (each input signal of the OR circuit 641) of the comparators 63 1 to 63 4 , and outputs the result.
  • the waveform shaping unit 68 4 includes a D-type flip-flop 69 4 in addition to the level conversion unit 65 4 that level-converts the comparison output COMP_4 of the comparator 63 4 to the power supply potential V DD . This is similar in the other waveform shaping units 68 1 to 68 3 .
  • the D-type flip-flop 69 4 performs toggle operation in which the logic of the output is inverted each time an input is applied. As a result of this toggle operation, the D-type flip-flop 69 4 shapes the waveform of the comparison output COMP_4 into a pulse signal having a pulse width wider than the comparison output COMP_4 and makes the result a pixel output. This is similar in the other D type flip-flops 69 1 to 69 3 .
  • Fig. 15 shows the timing relationship of the comparison outputs COMP_1 to COMP_4 of the comparators 63 1 to 63 4 . Each of the comparison outputs COMP_1 to COMP_4 becomes a pixel output through the waveform shaping units 68 1 to 68 4 .
  • An eighth embodiment is an example of the chip structure of the light receiving device 30.
  • the chip structure of the light receiving device 30 a stacked structure and a flat structure can be exemplified.
  • Fig. 16 shows an exploded perspective view of a stacked structure of the light receiving device 30 according to the eighth embodiment.
  • the number of pixels sharing the recharge control unit 64 is four, in other words, the SPAD sensors 51 1 to 51 4 having four pixels of two columns ⁇ two rows, and the circuit unit 60 including the shared recharge control unit 64 are shown.
  • the SPAD sensors 51 1 to 51 4 are arranged in a two-dimensional array on the sensor chip 71 including the first semiconductor substrate.
  • the circuit unit 60 corresponding to the SPAD sensors 51 1 to 51 4 is formed on the circuit chip 72 including the second semiconductor substrate stacked on the sensor chip 71.
  • the circuit unit 60 includes the first switch unit 61 (61 1 to 61 4 ) as a recharge switch, the second switch unit 62 as a quench switch, and the comparator 63 (63 1 to 63 4 ) that are provided for each SPAD sensor 51 1 to 51 4 , the recharge control unit 64 shared among the four pixels, and the like.
  • the recharge control unit 64 is shared among a plurality of pixels, so that the circuit area of the circuit unit 60 per pixel can be reduced, and thereby, the pixel 50 can be miniaturized, and further, the size of the chip size can be reduced.
  • the two-layer structure of the first-layer sensor chip 71 and the second-layer circuit chip 72 is described as an example of the stacked structure.
  • the technology of the present disclosure is not limited to the two-layer structure, and three or more layered structure may be adopted.
  • Fig. 17 shows a perspective view of a flat structure of the light receiving device 30 according to the eighth embodiment.
  • the circuit unit 60 including the first switch unit 61, the second switch unit 62, the comparator 63, the recharge control unit 64 shared by four pixels, and the like, the logic circuit 33, an I/O 73, and a peripheral circuit 74 are integrated.
  • the recharge control unit 64 is shared among the plurality of pixels, so that, since the circuit area of the circuit unit 60 per pixel can be reduced, the aperture ratio can be increased while miniaturizing the pixel 50.
  • a ninth embodiment is a first example in which the recharge signal generation circuit 642 of the recharge control unit 64 includes a ring oscillator.
  • Fig. 18 shows a circuit configuration of the recharge signal generation circuit 642 according to the ninth embodiment.
  • the recharge signal generation circuit 642 includes a ring oscillator that oscillates by the connection in a ring shape of a two-input NAND circuit 6421 and a plurality of asymmetric delay elements 6422 1 to 6422 i .
  • the asymmetric delay element is a delay element in which the rising delay time td _rise_ DLY and the falling delay time td _fall_DLY are different.
  • An example of an asymmetric delay element is an inverter.
  • the OR output OR out of the OR circuit 641 is used as one input and the output of the last stage asymmetric delay element 6422 i as the recharge signal RCHG is used as the other input.
  • Fig. 19 shows a timing waveform diagram of each unit in the light receiving device 30 having the recharge signal generation circuit 642 of the above configuration.
  • Fig. 19 shows the timing waveforms of the output of the OR circuit 641, the output of the NAND circuit 6421, the recharge signal RCHG, the cathode potential of the SPAD sensor 51 (51 1 to 51 4 ), and the output of the comparator 63 (63 1 to 63 4 ).
  • the recharge signal generation circuit 642 is preferable since a fine pulse width can be arbitrarily set for the recharge signal RCHG by adjusting the number of stages of the asymmetric delay elements 6422 1 to 6422 i .
  • the four-input OR circuit 641 may have a circuit configuration including a combination of a four-input NOR circuit 6411 and an inverter 6412.
  • a tenth embodiment is a second example in which the recharge signal generation circuit 642 of the recharge control unit 64 includes a ring oscillator.
  • Fig. 20 shows a circuit configuration of the recharge signal generation circuit 642 according to the tenth embodiment.
  • the recharge signal generation circuit 642 according to the ninth embodiment includes the two-input NAND circuit 6421 and the plurality of asymmetric delay elements 6422 1 to 6422 i .
  • the recharge signal generation circuit 642 according to the tenth embodiment uses a two-input NOR circuit 6423 instead of the two-input NAND circuit 6421.
  • the inverter 6424 is inserted in the path between the output end of the last stage asymmetric delay element 6422 i and the other input end of the NOR circuit 6423. Furthermore, the four-input NOR circuit 647 is used in place of the four-input OR circuit 641 that takes the OR of the comparison outputs COMP_1 to COMP_4 of the comparators 63 1 to 63 4 .
  • the recharge signal generation circuit 642 according to the tenth embodiment is a circuit having equivalent logic to the logic of the recharge signal generation circuit 642 according to the ninth embodiment.
  • An eleventh embodiment is an example of an asymmetric delay element constituting the ring oscillator.
  • Fig. 21 is a circuit configuration of an asymmetric delay element according to the eleventh embodiment.
  • the asymmetric delay element is exemplified as a four-stage configuration.
  • the configuration is not limited thereto. This is similar in a twelfth embodiment and a thirteenth embodiment to be described later.
  • the first stage has a CMOS inverter configuration including a P-channel field effect transistor Q p1 and an N-channel field effect transistor Q n1 connected in series between the high potential side power supply and the low potential side power supply. Specifically, gate electrodes of the P-channel field effect transistor Q p1 and the N-channel field effect transistor Q n1 are connected in common to serve as input ends, and the drain electrodes are connected in common to serve as output ends.
  • the transistor sizes of the P-channel field effect transistor Q p1 and the N-channel field effect transistor Q n1 are asymmetric. Specifically, if a channel width is W and a channel length is L, a transistor size W/L is set so that the P-channel field effect transistor Q p1 is smaller than the N-channel field effect transistor Q n1 . If the transistor size W/L is small, the on-resistance R on is large, and if the transistor size W/L is large, the on-resistance R on is small.
  • the second stage has a CMOS inverter configuration including a P-channel field effect transistor Q p2 and an N-channel field effect transistor Q n2 connected between the high potential side power supply and the low potential side power supply.
  • the transistor size W/L is set so that the P-channel field effect transistor Q p2 is larger than the N-channel field effect transistor Q n2 .
  • the third stage has a CMOS inverter configuration including a P-channel field effect transistor Q p3 and an N-channel field effect transistor Q n3 .
  • the setting is similar to that of the first stage CMOS inverter.
  • the fourth stage has a CMOS inverter configuration including a P-channel field effect transistor Q p4 and an N-channel field effect transistor Q n4 .
  • the setting is similar to that of the second stage CMOS inverter.
  • the transistor with the higher on-resistance R on drives the next stage, so that the delay time becomes long.
  • the transistor with the smaller on-resistance R on drives the next stage, so that the delay time becomes short. Accordingly, the rising delay time t d_rise_DLY and the falling delay time td _fall_DLY are different.
  • a twelfth embodiment is a modification of the eleventh embodiment, and is an example of switching the number of series (the number of series connections) of elements with high on-resistance constituting the CMOS inverter.
  • Fig. 22 is a circuit configuration of the asymmetric delay element according to the twelfth embodiment.
  • the first stage has a CMOS inverter configuration including, for example, three P-channel field effect transistors Q p11 , Q p12 , and Q p13 and an N-channel field effect transistor Q n11 connected in series between the high potential side power supply and the low potential side power supply.
  • gate electrodes of the P-channel field effect transistors Q p11 , Q p12 , and Q p13 and the N-channel field effect transistor Q n11 are connected in common to serve as input ends, and the drain electrodes of the field effect transistor Q p13 and the field effect transistor Q n11 are connected in common to serve as output ends.
  • the P-channel field effect transistors Q p11 , Q p12 , and Q p13 have higher on-resistance than the N-channel field effect transistor Q n11 . Furthermore, for example, the sizes W/L of the P-channel field effect transistors Q p11 , Q p12 , and Q p13 are set to be equal.
  • the P-channel field effect transistor Q p14 is connected between the common connection node of the field effect transistor Q p11 and the field effect transistor Q p12 and the high potential side power supply.
  • the P-channel field effect transistor Q p15 is connected between the common connection node of the field effect transistor Q p12 and the field effect transistor Q p13 and the high potential side power supply.
  • a control signal D 0 is applied to the gate electrode of the P-channel field effect transistor Q p14
  • a control signal D 1 is applied to the gate electrode of the P-channel field effect transistor Q p15 .
  • control signal D 0 is logic 0 and the control signal D 1 is logic 1
  • the field effect transistor Q p14 is rendered conductive, and the field effect transistor Q p15 is rendered non-conductive, so that the field effect transistors Q p12 , Q p13 are connected in series to the N-channel field effect transistor Q n11 .
  • the control signals D 0 , D 1 are both logic 1
  • both the field effect transistors Q p14 , Q p15 are rendered non-conductive, so that the field effect transistors Q p11 , Q p12 , and Q p13 are connected in series to the N-channel field effect transistor Q n11 .
  • the second stage has a CMOS inverter configuration including a P-channel field effect transistor Q p21 and, for example, three N-channel field effect transistors Q n21 , Q n22 , and Q n23 connected in series between the high potential side power supply and the low potential side power supply.
  • a CMOS inverter configuration including a P-channel field effect transistor Q p21 and, for example, three N-channel field effect transistors Q n21 , Q n22 , and Q n23 connected in series between the high potential side power supply and the low potential side power supply.
  • gate electrodes of the P-channel field effect transistor Q p21 and the N-channel field effect transistors Q n21 , Q n22 , and Q n23 are connected in common to serve as input ends
  • the drain electrodes of the field effect transistor Q p21 and the field effect transistor Q n21 are connected in common to serve as output ends.
  • the N-channel field effect transistors Q n21 , Q n22 , and Q n23 have higher on-resistance than the P-channel field effect transistor Q p21 . Furthermore, for example, the sizes W/L of the N-channel field effect transistors Q n21 , Q n22 , and Q n23 are set to be equal.
  • the P-channel field effect transistor Q p22 is connected between the common connection node of the field effect transistor Q n21 and the field effect transistor Q n22 , and the low potential side power supply.
  • the P-channel field effect transistor Q p23 is connected between the common connection node of the field effect transistor Q n22 and the field effect transistor Q n23 and the low potential side power supply.
  • An inverted signal xD 0 of the control signal D 0 is applied to the gate electrode of the P-channel field effect transistor Q p22
  • an inverted signal xD 1 of the control signal D 1 is applied to the gate electrode of the P-channel field effect transistor Q p23 .
  • the field effect transistor Q p22 is rendered non-conductive, and the field effect transistor Q p23 is rendered conductive, so that the field effect transistors Q n21 , Q n22 are connected in series to the P-channel field effect transistor Q p21 .
  • the control signals D 0 , D 1 are both logic 1
  • both the field effect transistors Q p22 , Q p23 are rendered non-conductive, so that the field effect transistors Q n21 , Q n22 , Q n23 are connected in series to the P-channel field effect transistor Q p21 .
  • the third stage has a CMOS inverter configuration including, for example, three P-channel field effect transistors Q p31 , Q p32 , and Q p33 and, the N-channel field effect transistor Q n31 connected in series between the high potential side power supply and the low potential side power supply.
  • gate electrodes of the P-channel field effect transistors Q p31 , Q p32 , and Q p33 and the N-channel field effect transistor Q n31 are connected in common to serve as input ends, and the drain electrodes of the field effect transistor Q p33 and the field effect transistor Q n31 are connected in common to serve as output ends.
  • the P-channel field effect transistors Q p31 , Q p32 , Q p33 have higher on-resistance than the N-channel field effect transistor Q n31 . Furthermore, for example, the sizes W/L of the P-channel field effect transistors Q p31 , Q p32 , and Q p33 are set to be equal.
  • the P-channel field effect transistor Q p34 is connected between the common connection node of the field effect transistor Q p31 and the field effect transistor Q p32 and the high potential side power supply.
  • the P-channel field effect transistor Q p15 is connected between the common connection node of the field effect transistor Q p32 and the field effect transistor Q p33 and the high potential side power supply.
  • a control signal D 0 is applied to the gate electrode of the P-channel field effect transistor Q p34
  • a control signal D 1 is applied to the gate electrode of the P-channel field effect transistor Q p15 .
  • the circuit operation according to the logic of the control signals D 0 , D 1 is the same as that in the case of the first stage CMOS inverter.
  • the fourth stage has a CMOS inverter configuration including a P-channel field effect transistor Q p41 and, for example, three N-channel field effect transistors Q n41 , Q n42 , and Q n43 connected in series between the high potential side power supply and the low potential side power supply. Specifically, gate electrodes of the P-channel field effect transistor Q p41 and the N-channel field effect transistors Q n41 , Q n42 , and Q n43 are connected in common to serve as input ends, and the drain electrodes of the field effect transistor Q p41 and the field effect transistor Q n41 are connected in common to serve as output ends.
  • the N-channel field effect transistors Q n41 , Q n42 , and Q n43 have higher on-resistance than the P-channel field effect transistor Q p41 . Furthermore, for example, the sizes W/L of the N-channel field effect transistors Q p41 , Q p42 , and Q p43 are set to be equal.
  • the P-channel field effect transistor Q p42 is connected between the common connection node of the field effect transistor Q n41 and the field effect transistor Q n42 and the low potential side power supply.
  • the P-channel field effect transistor Q p43 is connected between the common connection node of the field effect transistor Q n42 and the field effect transistor Q n43 and the low potential side power supply.
  • An inverted signal xD 0 of the control signal D 0 is applied to the gate electrode of the P-channel field effect transistor Q p42
  • an inverted signal xD 1 of the control signal D 1 is applied to the gate electrode of the P-channel field effect transistor Q p43 .
  • the circuit operation according to the logic of the control signals (inverted signals) xD 0 , xD 1 is the same as that in the case of the second stage CMOS inverter.
  • the number of series connections of the field effect transistors having high on-resistance constituting the CMOS inverter is changed according to the logic of the control signals D 0 , D 1 .
  • the number of series connections of the P-channel field effect transistors is changed, and in the CMOS inverters of the second and fourth stages, the number of series connections of the N-channel field effect transistors is changed.
  • Fig. 23A shows a truth table of the asymmetric delay element according to the twelfth embodiment.
  • the number of series connections of the field effect transistors having high on-resistance constituting the CMOS inverter is changed according to the logic of the control signals D 0 , D 1 , so that the delay time can be controlled.
  • the delay time when the control signals D 0 , D 1 are both logic 0 is td 0
  • the delay time when the control signal D 0 is logic 0 and the control signal D 1 is logic 1 is td 1
  • the delay time when the control signals D 0 , D 1 are both logic 1 is td 2
  • the magnitude relation td 0 ⁇ td 1 ⁇ td 2 is satisfied.
  • a thirteenth embodiment is a modification of the eleventh embodiment, and is an example of switching the number of parallel (the number of parallel connections) of elements with high on-resistance constituting the CMOS inverter.
  • Fig. 24 shows a circuit configuration of the asymmetric delay element according to the thirteenth embodiment.
  • the P-channel field effect transistor Q p51 in the first stage having a CMOS inverter including a P-channel field effect transistor Q p51 and an N-channel field effect transistor Q n51 connected in series between the high potential side power supply and the low potential side power supply, the P-channel field effect transistor Q p51 has higher on-resistance than that of the N-channel field effect transistor Q n51 . Then, for example, three P-channel field effect transistors having a high on-resistance, in other words, the field effect transistors Q p51 , Q p52 , and Q p53 are connected in parallel.
  • the P-channel field effect transistor Q p54 is connected between the P-channel field effect transistor Q p52 and the high potential side power supply
  • the P-channel field effect transistor Q p55 is connected between the P-channel field effect transistor Q p53 and the high potential side power supply.
  • a control signal D 0 is applied to the gate electrode of the P-channel field effect transistor Q p54
  • a control signal D 1 is applied to the gate electrode of the P-channel field effect transistor Q p55 .
  • control signal D 0 is logic 0 and the control signal D 1 is logic 1
  • the field effect transistor Q p54 is rendered conductive, and the field effect transistor Q p55 is rendered non-conductive, so that the field effect transistor Q p52 is connected in parallel to the field effect transistor Q p51 .
  • the control signals D 0 , D 1 are both logic 1
  • both the field effect transistors Q p54 , Q p55 are rendered non-conductive, so that the field effect transistor Q p51 is independently connected in series to the N-channel field effect transistor Q n51 .
  • the N-channel field effect transistor Q n61 has higher on-resistance than that of the P-channel field effect transistor Q p61 . Then, for example, three N-channel field effect transistors having a high on-resistance, in other words, the field effect transistors Q n61 , Q n62 , and Q n63 are connected in parallel.
  • the P-channel field effect transistor Q p64 is connected between the N-channel field effect transistor Q n62 and the low potential side power supply
  • the P-channel field effect transistor Q p65 is connected between the N-channel field effect transistor Q n63 and the low potential side power supply.
  • An inverted signal xD 0 of the control signal D 0 is applied to the gate electrode of the P-channel field effect transistor Q p64
  • an inverted signal xD 1 of the control signal D 1 is applied to the gate electrode of the P-channel field effect transistor Q p65 .
  • control signals xD 0 is logic 0 and the control signal xD 1 is logic 1
  • the field effect transistor Q p64 is rendered conductive, and the field effect transistor Q p65 is rendered non-conductive, so that the field effect transistor Q n62 is connected in parallel to the field effect transistor Q n61 .
  • the control signals xD 0 , xD 1 are both logic 1
  • both the field effect transistors Q p64 , Q p65 are rendered non-conductive, so that the field effect transistor Q n61 is independently connected in series to the P-channel field effect transistor Q p61 .
  • the P-channel field effect transistor Q p71 has higher on-resistance than that of the N-channel field effect transistor Q n71 .
  • three P-channel field effect transistors having a high on-resistance in other words, the field effect transistors Q p71 , Q p72 , and Q p73 are connected in parallel.
  • the P-channel field effect transistor Q p74 is connected between the P-channel field effect transistor Q p72 and the high potential side power supply
  • the P-channel field effect transistor Q p75 is connected between the P-channel field effect transistor Q p73 and the high potential side power supply.
  • a control signal D 0 is applied to the gate electrode of the P-channel field effect transistor Q p74
  • a control signal D 1 is applied to the gate electrode of the P-channel field effect transistor Q p75 .
  • the circuit operation according to the logic of the control signals D 0 , D 1 is the same as that in the case of the first stage CMOS inverter.
  • the N-channel field effect transistor Q n81 has higher on-resistance than that of the P-channel field effect transistor Q p81 . Then, for example, three N-channel field effect transistors having a high on-resistance, in other words, the field effect transistors Q n81 , Q n82 , and Q n83 are connected in parallel.
  • the P-channel field effect transistor Q p84 is connected between the N-channel field effect transistor Q n82 and the low potential side power supply
  • the P-channel field effect transistor Q pg5 is connected between the N-channel field effect transistor Q n83 and the low potential side power supply.
  • An inverted signal xD 0 of the control signal D 0 is applied to the gate electrode of the P-channel field effect transistor Q p84
  • an inverted signal xD 1 of the control signal D 1 is applied to the gate electrode of the P-channel field effect transistor Q p85 .
  • the circuit operation according to the logic of the control signals (inverted signals) xD 0 , xD 1 is the same as that in the case of the second stage CMOS inverter.
  • the number of parallel connections of the field effect transistors having high on-resistance constituting the CMOS inverter is changed according to the logic of the control signals D 0 , D 1 .
  • the number of parallel connections of the P-channel field effect transistors is changed, and in the CMOS inverters of the second and fourth stages, the number of parallel connections of the N-channel field effect transistors is changed.
  • Fig. 23B shows a truth table of the asymmetric delay element according to the thirteenth embodiment.
  • the number of parallel connections of the field effect transistors having high on-resistance constituting the CMOS inverter is changed according to the logic of the control signals D 0 , D 1 , so that the delay time can be controlled.
  • the delay time when the control signals D 0 , D 1 are both logic 0 is td 0
  • the delay time when the control signal D 0 is logic 0 and the control signal D 1 is logic 1 is td 1
  • the delay time when the control signals D 0 , D 1 are both logic 1 is td 2
  • the magnitude relation td 0 ⁇ td 1 ⁇ td 2 is satisfied.
  • the technology according to the present disclosure can be applied to various products. A more specific application example will be described below.
  • the technology according to the present disclosure may be realized as a distance measuring device mounted on any type of mobile body such as automobile, electric vehicle, hybrid electric vehicle, motorcycle, bicycle, personal mobility, airplane, drone, ship, robot, construction machine, agricultural machine (tractor).
  • Fig. 25 is a block diagram showing a schematic configuration example of a vehicle control system 7000 which is an example of a mobile body control system to which the technology according to the present disclosure can be applied.
  • the vehicle control system 7000 includes a plurality of electronic control units connected via a communication network 7010.
  • the vehicle control system 7000 includes a drive system control unit 7100, a body system control unit 7200, a battery control unit 7300, a vehicle exterior information detection unit 7400, a vehicle interior information detection unit 7500, and an integrated control unit 7600.
  • the communication network 7010 connecting the plurality of control units may be, for example, an in-vehicle communication network conforming to an arbitrary standard such as the controller area network (CAN), the local interconnect network (LIN), the local area network (LAN), or the FlexRay (registered trademark).
  • CAN controller area network
  • LIN local interconnect network
  • LAN local area network
  • FlexRay registered trademark
  • Each control unit includes a microcomputer that performs operation processing according to various programs, a storage unit that stores programs executed by the microcomputer, parameters used for various operation, or the like, and a drive circuit that drives devices subjected to various control.
  • Each control unit includes a network I/F for communicating with another control unit via the communication network 7010, and includes a communication I/F for communication by wired communication or wireless communication with vehicle interior or exterior device, a sensor, or the like.
  • each of the other control units includes a microcomputer, a communication I/F, a storage unit, and the like.
  • the drive system control unit 7100 controls the operation of the device related to the drive system of the vehicle according to various programs.
  • the drive system control unit 7100 functions as a control device of a driving force generation device for generating a drive force of a vehicle such as an internal combustion engine or a driving motor, a drive force transmission mechanism for transmitting a drive force to wheels, a steering mechanism that adjusts a wheeling angle of the vehicle, a braking device that generates a braking force of the vehicle, and the like.
  • the drive system control unit 7100 may have a function as a control device such as antilock brake system (ABS), or an electronic stability control (ESC ).
  • ABS antilock brake system
  • ESC electronic stability control
  • a vehicle state detection unit 7110 is connected to the drive system control unit 7100.
  • the vehicle state detection unit 7110 includes, for example, at least one of a gyro sensor that detects the angular velocity of the axis rotational motion of the vehicle body, an acceleration sensor that detects the acceleration of the vehicle, or a sensor for detecting an operation amount of an accelerator pedal, an operation amount of a brake pedal, steering of a steering wheel, an engine rotation speed, a wheel rotation speed, or the like.
  • the drive system control unit 7100 performs operation processing using the signal input from the vehicle state detection unit 7110 and controls the internal combustion engine, the driving motor, the electric power steering device, the brake device, or the like.
  • the body system control unit 7200 controls the operation of various devices mounted on the vehicle according to various programs.
  • the body system control unit 7200 functions as a keyless entry system, a smart key system, a power window device, or a control device for various lamps such as a head lamp, a back lamp, a brake lamp, a turn indicator, or a fog lamp.
  • radio waves transmitted from a portable device that substitutes keys or signals of various switches may be input to the body system control unit 7200.
  • the body system control unit 7200 receives input of these radio waves or signals and controls a door lock device, a power window device, a lamp, or the like of the vehicle.
  • the battery control unit 7300 controls a secondary battery 7310 that is a power supply source of the driving motor according to various programs. For example, information such as battery temperature, a battery output voltage or remaining capacity of the battery is input to the battery control unit 7300 from the battery device including the secondary battery 7310. The battery control unit 7300 performs arithmetic processing using these signals and controls the temperature adjustment of the secondary battery 7310, or the cooling device or the like included in the battery device.
  • the vehicle exterior information detection unit 7400 detects information outside the vehicle equipped with the vehicle control system 7000.
  • the imaging unit 7410 or the vehicle exterior information detector 7420 is connected to the vehicle exterior information detection unit 7400.
  • the imaging unit 7410 includes at least one of a time of flight (ToF) camera, a stereo camera, a monocular camera, an infrared camera, or other cameras.
  • the vehicle exterior information detector 7420 includes, for example, at least one of an environmental sensor for detecting the current weather or climate, or an ambient information detection sensor for detecting another vehicle, an obstacle, a pedestrian, or the like around the vehicle equipped with the vehicle control system 7000.
  • the environmental sensor may be, for example, at least one of a raindrop sensor that detects rain, a fog sensor that detects mist, a sunshine sensor that detects sunshine degree, or a snow sensor that detects snowfall.
  • the ambient information detection sensor may be at least one of an ultrasonic sensor, a radar device or a light detection and ranging, laser imaging detection and ranging (LIDAR) device.
  • the imaging unit 7410 and the vehicle exterior information detector 7420 may be provided as independent sensors or devices, respectively, or may be provided as a device in which a plurality of sensors or devices are integrated.
  • Fig. 26 shows an example of installation positions of the imaging unit 7410 and the vehicle exterior information detector 7420.
  • the imaging units 7910, 7912, 7914, 7916, 7918 are provided at, for example, at least one of a front nose, a side mirror, a rear bumper, or a back door, of the vehicle 7900 or an upper portion of a windshield in the vehicle compartment.
  • the imaging unit 7910 provided for the front nose and the imaging unit 7918 provided in the upper portion of the windshield in the vehicle compartment mainly acquire an image ahead of the vehicle 7900.
  • the imaging units 7912, 7914 provided in the side mirror mainly acquire an image of the side of the vehicle 7900.
  • the imaging unit 7916 provided in the rear bumper or the back door mainly acquires an image behind the vehicle 7900.
  • the imaging unit 7918 provided on the upper portion of the windshield in the vehicle compartment is mainly used for detecting a preceding vehicle, a pedestrian, an obstacle, a traffic signal, a traffic sign, a lane, or the like.
  • FIG. 26 shows an example of the imaging ranges of the imaging units 7910, 7912, 7914, 7916.
  • An imaging range a indicates the imaging range of the imaging unit 7910 provided in the front nose
  • the imaging ranges b, c indicate the imaging ranges of the imaging units 7912, 7914 provided in the side mirror
  • the imaging range d indicates the imaging range of the imaging unit 7916 provided in the rear bumper or the back door.
  • the vehicle exterior information detectors 7920, 7922, 7924, 7926, 7928, 7930 provided on the front, rear, side, or corner of the vehicle 7900 and the windshield in the upper portion of the vehicle compartment may be ultrasonic sensors or radar devices, for example.
  • the vehicle exterior information detectors 7920, 7926, 7930 provided at the front nose, the rear bumper, or the back door of the vehicle 7900, and the upper portion of the windshield of the vehicle compartment may be the LIDAR device, for example.
  • These vehicle exterior information detectors 7920 to 7930 are mainly used for detecting a preceding vehicle, a pedestrian, an obstacle, or the like.
  • the vehicle exterior information detection unit 7400 causes the imaging unit 7410 to image an image of the exterior of the vehicle and receives the imaged image data. Furthermore, the vehicle exterior information detection unit 7400 receives the detection information from the connected vehicle exterior information detector 7420. In a case where the vehicle exterior information detector 7420 is an ultrasonic sensor, a radar device or a LIDAR device, the exterior information detection unit 7400 transmits ultrasonic waves, electromagnetic waves, or the like, and receives information of the received reflected waves.
  • the vehicle exterior information detection unit 7400 may perform object detection processing or distance detection processing of a person, a car, an obstacle, a sign, a character on a road surface, or the like, on the basis of the received information.
  • the vehicle exterior information detection unit 7400 may perform environment recognition processing for recognizing rainfall, fog, road surface condition, or the like on the basis of the received information.
  • the vehicle exterior information detection unit 7400 may calculate the distance to the object outside the vehicle on the basis of the received information.
  • the vehicle exterior information detection unit 7400 may perform image recognition processing of recognizing a person, a car, an obstacle, a sign, a character on a road surface, or the like, on the basis of the received image data, or distance detection processing.
  • the vehicle exterior information detection unit 7400 performs processing such as distortion correction or positioning on the received image data and combines the image data imaged by different imaging units 7410 to generate an overhead view image or a panorama image.
  • the vehicle exterior information detection unit 7400 may perform viewpoint conversion processing using image data imaged by different imaging units 7410.
  • the vehicle interior information detection unit 7500 detects vehicle interior information.
  • a driver state detection unit 7510 that detects the state of the driver is connected to the vehicle interior information detection unit 7500.
  • the driver state detection unit 7510 may include a camera for imaging the driver, a biometric sensor for detecting the biological information of the driver, a microphone for collecting sound in the vehicle compartment, and the like.
  • the biometric sensor is provided on, for example, a seating surface, a steering wheel or the like, and detects biometric information of an occupant sitting on a seat or a driver holding a steering wheel.
  • the vehicle interior information detection unit 7500 may calculate the degree of fatigue or the degree of concentration of the driver on the basis of the detection information input from the driver state detection unit 7510, and may determine whether or not the driver is sleeping.
  • the vehicle interior information detection unit 7500 may perform processing such as noise canceling processing on the collected sound signal.
  • the integrated control unit 7600 controls the overall operation of the vehicle control system 7000 according to various programs.
  • An input unit 7800 is connected to the integrated control unit 7600.
  • the input unit 7800 is realized by a device such as a touch panel, a button, a microphone, a switch or a lever that can be input operated by an occupant, for example. Data obtained by performing speech recognition on the sound input by the microphone may be input to the integrated control unit 7600.
  • the input unit 7800 may be, for example, a remote control device using infrared rays or other radio waves, or an external connection device such as a mobile phone or a personal digital assistant (PDA) corresponding to the operation of the vehicle control system 7000.
  • PDA personal digital assistant
  • the input unit 7800 may be, for example, a camera, in which case the occupant can input information by gesture. Alternatively, data obtained by detecting the movement of the wearable device worn by the occupant may be input. Moreover, the input unit 7800 may include, for example, an input control circuit or the like that generates an input signal on the basis of information input by an occupant or the like using the input unit 7800 and outputs the input signal to the integrated control unit 7600. By operating the input unit 7800, an occupant or the like inputs various data or instructs processing operation to the vehicle control system 7000.
  • the storage unit 7690 may include a read only memory (ROM) that stores various programs to be executed by the microcomputer, and a random access memory (RAM) that stores various parameters, operation results, sensor values, or the like. Furthermore, the storage unit 7690 may be realized by a magnetic storage device such as a hard disc drive (HDD), a semiconductor storage device, an optical storage device, a magneto-optical storage device, or the like.
  • ROM read only memory
  • RAM random access memory
  • the storage unit 7690 may be realized by a magnetic storage device such as a hard disc drive (HDD), a semiconductor storage device, an optical storage device, a magneto-optical storage device, or the like.
  • the general-purpose communication I/F 7620 is a general-purpose communication I/ F that mediates communication with various devices existing in an external environment 7750.
  • a cellular communication protocol such as global system of mobile communications (GSM) (registered trademark), WiMAX, long term evolution (LTE), or LTE-advanced (LTE-A), or other wireless communication protocols such as a wireless LAN (Wi-Fi (registered trademark)), or Bluetooth (registered trademark), may be implemented in the general-purpose communication I/F 7620.
  • the general-purpose communication I/F 7620 may be connected to a device (for example, an application server or a control server) existing on an external network (for example, the Internet, a cloud network or a company specific network) via a base station or an access point, for example. Furthermore, the general-purpose communication I/F 7620 uses, for example, the peer to peer (P2P) technology to perform connection with a terminal existing in the vicinity of the vehicle (for example, a terminal of a driver, a pedestrian or a shop, or the machine type communication terminal (MTC).
  • P2P peer to peer
  • MTC machine type communication terminal
  • the dedicated communication I/F 7630 is a communication I/F supporting a communication protocol formulated for use in a vehicle.
  • a standard protocol such as the wireless access in vehicle environment (WAVE) that is combination of lower layer IEEE 802.1 lp and upper layer IEEE 1609, the dedicated short range communications (DSRC), or the cellular communication protocol may be implemented.
  • the dedicated communication I/F 7630 performs V2X communication that is concept including one or more of a vehicle to vehicle communication, a vehicle to infrastructure communication, a vehicle to home communication, and a vehicle to pedestrian communication.
  • the positioning unit 7640 receives a global navigation satellite system (GNSS) signal from a GNSS satellite (for example, a GPS signal from a global positioning system (GPS) satellite) and performs positioning, to generate position information including the latitude, longitude, and altitude of the vehicle.
  • GNSS global navigation satellite system
  • GPS global positioning system
  • the positioning unit 7640 may specify the current position by exchanging signals with the wireless access point or may acquire the position information from a terminal such as a mobile phone, a PHS or a smartphone having a positioning function.
  • the beacon reception unit 7650 receives, for example, radio waves or electromagnetic waves transmitted from a radio station or the like installed on the road, and acquires information such as the current position, congestion, road closure or required time. Note that the function of the beacon reception unit 7650 may be included in the dedicated communication I/F 7630 described above.
  • the vehicle interior equipment I/F 7660 is a communication interface that mediates connection between the microcomputer 7610 and various interior equipment 7760 existing in the vehicle.
  • the vehicle interior equipment I/F 7660 may establish a wireless connection using a wireless communication protocol such as wireless LAN, Bluetooth (registered trademark), near field communication (NFC), or a wireless USB (WUSB).
  • a wireless communication protocol such as wireless LAN, Bluetooth (registered trademark), near field communication (NFC), or a wireless USB (WUSB).
  • the vehicle interior equipment I/F 7660 may establish wired connection such as a universal serial bus (USB), a high-definition multimedia interface (HDMI (registered trademark)), or a mobile high-definition link (MHL) via a connection terminal not shown (and a cable if necessary).
  • USB universal serial bus
  • HDMI high-definition multimedia interface
  • MHL mobile high-definition link
  • the vehicle interior equipment 7760 may include, for example, at least one of a mobile device or a wearable device possessed by an occupant, or an information device carried in or attached to the vehicle. Furthermore, the vehicle interior equipment 7760 may include a navigation device that performs a route search to an arbitrary destination. The vehicle interior equipment I/F 7660 exchanges control signals or data signals with these vehicle interior equipment 7760.
  • the in-vehicle network I/F 7680 is an interface mediating communication between the microcomputer 7610 and the communication network 7010.
  • the in-vehicle network I/F 7680 transmits and receives signals and the like according to a predetermined protocol supported by the communication network 7010.
  • the microcomputer 7610 of the integrated control unit 7600 controls the vehicle control system 7000 in accordance with various programs on the basis of information acquired via at least one of the general-purpose communication I/F 7620, the dedicated communication I/F 7630, the positioning unit 7640, the beacon reception unit 7650, the vehicle interior equipment I/F 7660, or the in-vehicle network I/F 7680.
  • the microcomputer 7610 may operate a control target value of the drive force generation device, the steering mechanism, or the braking device on the basis of acquired information inside and outside the vehicle, and output a control command to the drive system control unit 7100.
  • the microcomputer 7610 may perform cooperative control for the purpose of function realization of an advanced driver assistance system (ADAS) including collision avoidance or impact mitigation of the vehicle, follow-up running based on inter-vehicle distance, vehicle speed maintenance running, vehicle collision warning, vehicle lane departure warning, or the like.
  • ADAS advanced driver assistance system
  • the microcomputer 7610 may perform cooperative control for the purpose of automatic driving or the like by which a vehicle autonomously runs without depending on the operation of the driver by controlling the drive force generation device, the steering mechanism, the braking device, or the like on the basis of the acquired information on the surroundings of the vehicle.
  • the microcomputer 7610 may generate three-dimensional distance information between the vehicle and a surrounding structure, an object, a person, or the like on the basis of the information acquired via at least one of the general-purpose communication I/F 7620, the dedicated communication I/F 7630, the positioning unit 7640, the beacon reception unit 7650, the vehicle interior equipment I/F 7660, or the in-vehicle network I/F 7680, and create local map information including peripheral information on the current position of the vehicle. Furthermore, the microcomputer 7610 may predict danger such as collision of a vehicle, approach of a pedestrian, or entry into a road where traffic is stopped, or the like on the basis of acquired information to generate a warning signal.
  • the warning signal may be, for example, a signal for generating an alarm sound or for turning on a warning lamp.
  • the audio image output unit 7670 transmits an output signal of at least one of audio and image to an output device capable of visually or audibly notifying the occupant of the vehicle or the outside of the vehicle, of information.
  • an output device an audio speaker 7710, a display unit 7720, and an instrument panel 7730 are illustrated.
  • the display unit 7720 may include at least one of an on-board display or a head-up display, for example.
  • the display unit 7720 may have an augmented reality (AR) display function.
  • the output device may be other devices including a wearable device such as a headphone, a spectacular display worn by an occupant, a projector, a lamp, or the like other than these devices.
  • the output device is a display device
  • the display device visually displays the result obtained by the various processing performed by the microcomputer 7610 or the information received from the other control unit in various formats such as text, image, table, or graph.
  • the audio output device converts an audio signal including reproduced audio data, acoustic data, or the like into an analog signal, and outputs the result audibly.
  • At least two control units connected via the communication network 7010 may be integrated as one control unit.
  • each control unit may be constituted by a plurality of control units.
  • the vehicle control system 7000 may include another control unit not shown.
  • some or all of the functions carried out by any one of the control units may be performed by the other control unit. That is, as long as information is transmitted and received via the communication network 7010, predetermined operation processing may be performed by any control unit.
  • a sensor or device connected to any of the control units may be connected to another control unit, and a plurality of control units may transmit and receive detection information to and from each other via the communication network 7010.
  • the technology according to the present disclosure can be applied to the imaging units 7910, 7912, 7914, 7916, 7918 and the vehicle exterior information detectors 7920, 7922, 7924, 7926, 7928, 7930, among the configurations described above.
  • the circuit area per pixel can be reduced, so that it is possible to reduce the size of the imaging unit and the vehicle exterior information detector.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • Remote Sensing (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Measurement Of Optical Distance (AREA)
  • Optical Radar Systems And Details Thereof (AREA)
  • Light Receiving Elements (AREA)
  • Solid State Image Pick-Up Elements (AREA)
EP19713590.8A 2018-03-16 2019-03-06 Light receiving device and distance measuring device Active EP3765866B1 (en)

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JP2018049178A JP2019158806A (ja) 2018-03-16 2018-03-16 受光装置及び測距装置
PCT/JP2019/008791 WO2019176673A1 (en) 2018-03-16 2019-03-06 Light receiving device and distance measuring device

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US20220384493A1 (en) * 2019-11-20 2022-12-01 Sony Semiconductor Solutions Corporation Solid-state imaging apparatus and distance measurement system
JP7463767B2 (ja) 2020-03-02 2024-04-09 株式会社リコー 受光装置及び距離計測装置
US20230384431A1 (en) * 2020-10-27 2023-11-30 Sony Semiconductor Solutions Corporation Light receiving device and distance measuring apparatus
CN112285675B (zh) * 2020-12-15 2021-05-28 深圳市汇顶科技股份有限公司 飞行时间量测电路及相关芯片及电子装置
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Family Cites Families (9)

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US5187538A (en) * 1990-10-30 1993-02-16 Kabushiki Kaisha Toshiba Laser doppler velocimeter
US20110057736A1 (en) * 2009-04-28 2011-03-10 Skyworks Solutions, Inc. Linear, Voltage-Controlled Ring Oscillator With Current-Mode, Digital Frequency And Gain Control
CN105143921B (zh) * 2013-04-24 2018-10-23 皇家飞利浦有限公司 使用光学探测器像素阵列和像素元触发状态感测电路来对辐射量子的探测
US9313476B2 (en) * 2014-08-07 2016-04-12 Omnivision Technologies, Inc. Precharged latched pixel cell for a time of flight 3D image sensor
CN203981883U (zh) * 2014-08-13 2014-12-03 深圳市瑞尔幸电子有限公司 一种红外照明激光测距夜视仪
US10109667B2 (en) 2015-10-09 2018-10-23 Semiconductor Energy Laboratory Co., Ltd. Imaging device, module, and electronic device
CN108291961B (zh) * 2015-12-08 2022-06-28 松下知识产权经营株式会社 固体摄像装置、距离测定装置及距离测定方法
US10332930B2 (en) * 2015-12-21 2019-06-25 Stmicroelectronics (Research & Development) Limited Single photon avalanche diode (SPAD) array including distributed or tree for readout
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EP3765866A1 (en) 2021-01-20
US20210041540A1 (en) 2021-02-11
CN111868555B (zh) 2024-06-11

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