Classifications

• • G—PHYSICS
  • G01—MEASURING; TESTING
  • G01J—MEASUREMENT OF INTENSITY, VELOCITY, SPECTRAL CONTENT, POLARISATION, PHASE OR PULSE CHARACTERISTICS OF INFRARED, VISIBLE OR ULTRAVIOLET LIGHT; COLORIMETRY; RADIATION PYROMETRY
  • G01J5/00—Radiation pyrometry, e.g. infrared or optical thermometry
  • G01J5/10—Radiation pyrometry, e.g. infrared or optical thermometry using electric radiation detectors
  • G01J5/20—Radiation pyrometry, e.g. infrared or optical thermometry using electric radiation detectors using resistors, thermistors or semiconductors sensitive to radiation, e.g. photoconductive devices
  • G01J5/22—Electrical features thereof
  • G01J5/24—Use of specially adapted circuits, e.g. bridge circuits
• • G—PHYSICS
  • G01—MEASURING; TESTING
  • G01J—MEASUREMENT OF INTENSITY, VELOCITY, SPECTRAL CONTENT, POLARISATION, PHASE OR PULSE CHARACTERISTICS OF INFRARED, VISIBLE OR ULTRAVIOLET LIGHT; COLORIMETRY; RADIATION PYROMETRY
  • G01J5/00—Radiation pyrometry, e.g. infrared or optical thermometry
  • G01J5/10—Radiation pyrometry, e.g. infrared or optical thermometry using electric radiation detectors
  • G01J5/20—Radiation pyrometry, e.g. infrared or optical thermometry using electric radiation detectors using resistors, thermistors or semiconductors sensitive to radiation, e.g. photoconductive devices
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03F—AMPLIFIERS
  • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
  • H03F1/08—Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements
  • H03F1/083—Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements in transistor amplifiers
  • H03F1/086—Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements in transistor amplifiers with FET's
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03F—AMPLIFIERS
  • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
  • H03F3/005—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements using switched capacitors, e.g. dynamic amplifiers; using switched capacitors as resistors in differential amplifiers
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03F—AMPLIFIERS
  • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
  • H03F3/181—Low-frequency amplifiers, e.g. audio preamplifiers
  • H03F3/183—Low-frequency amplifiers, e.g. audio preamplifiers with semiconductor devices only
  • H03F3/185—Low-frequency amplifiers, e.g. audio preamplifiers with semiconductor devices only with field-effect devices
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03F—AMPLIFIERS
  • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
  • H03F3/45—Differential amplifiers
  • H03F3/45071—Differential amplifiers with semiconductor devices only
  • H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
  • H03F3/45475—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using IC blocks as the active amplifying circuit
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03F—AMPLIFIERS
  • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
  • H03F3/45—Differential amplifiers
  • H03F3/45071—Differential amplifiers with semiconductor devices only
  • H03F3/45479—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection
  • H03F3/45928—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection using IC blocks as the active amplifying circuit
  • H03F3/45968—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection using IC blocks as the active amplifying circuit by offset reduction
  • H03F3/45991—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection using IC blocks as the active amplifying circuit by offset reduction by using balancing means
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03F—AMPLIFIERS
  • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
  • H03F3/70—Charge amplifiers
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
  • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
  • H03M1/12—Analogue/digital converters
  • H03M1/18—Automatic control for modifying the range of signals the converter can handle, e.g. gain ranging
  • H03M1/181—Automatic control for modifying the range of signals the converter can handle, e.g. gain ranging in feedback mode, i.e. by determining the range to be selected from one or more previous digital output values
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
  • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
  • H03M1/12—Analogue/digital converters
  • H03M1/50—Analogue/digital converters with intermediate conversion to time interval
  • H03M1/52—Input signal integrated with linear return to datum
• • G—PHYSICS
  • G01—MEASURING; TESTING
  • G01J—MEASUREMENT OF INTENSITY, VELOCITY, SPECTRAL CONTENT, POLARISATION, PHASE OR PULSE CHARACTERISTICS OF INFRARED, VISIBLE OR ULTRAVIOLET LIGHT; COLORIMETRY; RADIATION PYROMETRY
  • G01J5/00—Radiation pyrometry, e.g. infrared or optical thermometry
  • G01J5/10—Radiation pyrometry, e.g. infrared or optical thermometry using electric radiation detectors
  • G01J5/20—Radiation pyrometry, e.g. infrared or optical thermometry using electric radiation detectors using resistors, thermistors or semiconductors sensitive to radiation, e.g. photoconductive devices
  • G01J2005/202—Arrays
  • G01J2005/204—Arrays prepared by semiconductor processing, e.g. VLSI
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03F—AMPLIFIERS
  • H03F2200/00—Indexing scheme relating to amplifiers
  • H03F2200/156—One or more switches are realised in the feedback circuit of the amplifier stage
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03F—AMPLIFIERS
  • H03F2200/00—Indexing scheme relating to amplifiers
  • H03F2200/264—An operational amplifier based integrator or transistor based integrator being used in an amplifying circuit
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03F—AMPLIFIERS
  • H03F2200/00—Indexing scheme relating to amplifiers
  • H03F2200/78—A comparator being used in a controlling circuit of an amplifier

Definitions

• the invention relates to the field of electrical current integration, in particular that of integrators comprising a capacitor connected in feedback on an operational amplifier, and delivering an electric voltage function of the charges received and stored in the capacitor.
• the invention applies in particular, but not exclusively, to the field of the detection of electromagnetic radiation, and particularly that of the infrared. It applies more specifically to the field of thermal imaging using matrix detectors consisting of a matrix of micro-bolometers, whether it is the conventional imaging intended to form thermal images, or of thermographic imaging to obtain temperature measurements.
• the invention thus aims in particular at an integrator with a high reading dynamic, that is to say an integrator capable of measuring an electric current corresponding to a small quantity of electrical charges and of measuring an electric current corresponding to a large quantity of charges. electric.
• the invention aims at the formation of images containing the maximum of useful information, obtained from scenes presenting a high flow dynamics, that is to say characterized by large deviations of energy emitted between the various points of the scene, and more especially a particularly large difference in temperature between "cold" zones and "hot” zones with regard to thermal detectors, of the order of several hundred degrees Celsius .
• microbolometric type thermal detectors in that they particularly benefit from the advantages provided by the invention.
• problems expressed in this context apply to any type of device producing electrical charges to be measured.
• electromagnetic radiation detectors whether detectors operating for example in the visible range, or detectors operating in the infrared or beyond in the so-called Terahertz bands.
• the invention also benefits from detectors sensitive to electromagnetic waves, such as thermal detectors for example of the bolometric and capacitive type, or coupling antennas for the thermal and Terahertz domains, and so-called quantum detectors, sensitive to corpuscles. electromagnetic energy among which we can mention the detectors operating from the X, UV, visible and infrared bands.
• the term "detector” may be understood as any system intended to produce an electrical signal in relation to a unitary, linear or two-dimensional distribution of any phenomenon.
• thermal infrared detectors In the field of so-called “thermal” infrared detectors, it is known to use one-dimensional or two-dimensional matrices of elements sensitive to infrared radiation, capable of operating at ambient temperature, that is to say not requiring cooling at room temperature. very low temperatures, unlike detection devices called “quantum detectors”, which, they require operation at a very low temperature, typically that of liquid nitrogen.
• a thermal infrared detector traditionally uses the variation of a physical quantity of a suitable material called “thermometric” or “bolometric”, depending on its temperature. Most commonly, this physical quantity is the electrical resistivity of said material which varies greatly with temperature.
• the unit sensitive elements of the detector, or “bolometers”, usually take the form of membranes, each comprising a layer of thermometric material, and suspended above a substrate, generally made of silicon, via heat resistance support arms. high, the matrix of suspended membranes is usually referred to as the "retina”.
• These membranes implement, in particular, an absorption function of the incident infrared radiation, a function for converting the power of the radiation absorbed into heating power, and a thermometric function for converting the heating power produced into a variation of the resistivity of the thermometric material.
• these functions can be implemented by one or more distinct elements.
• the support arms of the membranes are also conductive and connected to the thermometric layer thereof. It is usually formed in the substrate above which the membranes are suspended, sequential means for addressing and polarizing the thermometric elements of the membranes, and means for forming the electrical signals that can be used in video formats. This substrate and the integrated means are commonly referred to as the "read circuit".
• a solution generally implemented is the disposition, in the electronic circuit of formation of the signal in relation to the temperature of the imaging bolometers (so named because sensitive to the incident electromagnetic radiation), of a focal plane temperature compensation element (TPF) itself bolometric, that is to say whose electrical behavior follows the temperature of the substrate, but remains substantially insensitive to radiation.
• TPF focal plane temperature compensation element
• This result is obtained for example by means of bolometric structures endowed by construction of a low thermal resistance towards the substrate, and / or by masking these structures behind a screen that is opaque to thermal radiation.
• the implementation of these compensation elements also offers the advantage of eliminating most of the so-called common mode current from imaging bolometers or "active".
• FIG. 1 is a circuit diagram of a bolometric detector 10 without temperature regulation, or "TECless” detector, of the state of the art, comprising a common mode compensation structure.
• Figure 2 is an electrical diagram of a circuit implemented to form a readout signal of a bolometer of the common mode compensated detector.
• TECless detector a circuit implemented to form a readout signal of a bolometer of the common mode compensated detector.
• Such a detector is for example described in the document: "Uncooled amorphous Silicone technology enhancement for 25mhi pixel pitch achievement"; E. Mottin et al, Infrared Technology and Application XXVIII, SPIE, vol. 4820E.
• the detector 10 comprises a two-dimensional matrix 12 of identical bolometric detection unit elements 14, or "pixels", each comprising a sensitive resistive bolometer 16 in the form of a membrane suspended above a substrate, as previously described. , and electrical resistance R ac .
• Each bolometer 16 is connected by one of its terminals to a constant voltage VDET, in particular the ground of the detector 10, and by the other of its terminals to a bias MOS transistor 18 operating in a saturated state, for example an NMOS transistor. , adjusting the voltage V ac across the bolometer 16 by means of a gate control voltage GAC.
• the pixel 14 also comprises a selection switch 20, connected between the MOS transistor 18 and a node S provided for each column of the matrix 12, and controlled by a control signal Select, allowing the selection of the bolometer 16 for its reading.
• the transistor 18 and the switch 20 are usually formed in the substrate under the influence of the membrane of the bolometer 16.
• the elements 16 and 18 form a so-called detection branch.
• the bolometers 16 are therefore biased in voltage under the same voltage V ac .
• the gate voltage GAC being constant, the voltage V ac is therefore also constant.
• the detector 10 also comprises, at the bottom of each column of the matrix 12, a compensation structure 22, also commonly referred to as a "skimming” or “skimming” structure.
• a compensation structure 22 also commonly referred to as a "skimming” or “skimming” structure.
• the compensation structure 22 has the function of producing an electric current for partial or total compensation of this component.
• the structure 22 comprises a compensating bolometer 24, electrical resistance R cm , rendered insensitive to incident radiation from the scene to be observed.
• the bolometer 24 is constructed using the same thermometric material as the bolometer 16, but has a very low thermal resistance towards the substrate. For example :
• the resistive elements of the compensation bolometer 24 are made directly in contact with the substrate, or
• the bolometer 24 comprises a membrane similar to that of the detection bolometers 16 suspended above the substrate by means of structures having a very low thermal resistance, or
• the compensation bolometer 24 comprises a membrane and support arms substantially identical to those of the detection bolometers 16 and a good thermal conductive material fills the space between the membrane of the bolometer 24 and the substrate.
• the electrical resistance of the bolometer 24 is thus essentially dictated by the temperature of the substrate, the bolometer 24 is then said "thermalized" to the substrate.
• the bolometer 24 is connected at one of its terminals to a positive constant voltage VSK, and the compensation structure 22 further comprises a bias MOS transistor 26 operating in a saturated state, of opposite polarity to that of the transistors 18 of the detection 14, for example a PMOS transistor, adjusting the voltage V cm across the bolometer 24 by means of a gate control voltage GCM, and connected between the other terminal of the compensation bolometer 24 and the node S.
• a bias MOS transistor 26 operating in a saturated state, of opposite polarity to that of the transistors 18 of the detection 14, for example a PMOS transistor, adjusting the voltage V cm across the bolometer 24 by means of a gate control voltage GCM, and connected between the other terminal of the compensation bolometer 24 and the node S.
• GCM gate control voltage
• the elements 24 and 26 form a so
• the value of the common compensation mode current is defined by the value of the resistance R cm of the bolometer 24 and the polarization parameters thereof.
• the detector 10 also comprises, at the bottom of each column of the matrix 12, an integrator 28 of the CTIA type (for the English expression “Capacitive Trans Impedance Amplifier”) comprising for example an operational amplifier 30 and a single capacitor 32, of capacitance C M fixed, connected between the inverting input and the output of the amplifier 30.
• the inverting input and the non-inverting input of the latter are also connected respectively to the node S and a positive constant voltage VBUS .
• the voltage VBUS thus constitutes a reference for the output signals, and is between VDET and VSK.
• a switch 34, driven by a Reset signal is also provided in parallel capacitor 32, for the discharge thereof.
• the outputs of CTIA 28 are, for example, connected to sample and hold ( "Sample and Hold") 36 for issuing respective V aut voltages CTIA in multiplexed mode through a multiplexer 38 to one or more amplifier ( s) output series 40. It can also be integrated at the output of the digitization means by analog-to-digital converters (ADCs).
• sample and Hold "Sample and Hold”
• ADCs analog-to-digital converters
• the detector 10 finally comprises a sequencing unit 42 controlling the various switches described above.
• the matrix 12 is read line by line.
• the switches 20 of the pixel line 14 are closed and the switches 20 of the other lines are open.
• the successive reading of all the rows of the matrix 12 constitutes a frame.
• a current I ac flows in the detection bolometer 16 of the pixel under the effect of its voltage polarization by the MOS transistor 18, and a current I cm flows in the compensation bolometer 24 of the compensation structure under the effect of its voltage bias by the MOS transistor 26.
• These currents are subtracted from each other at the node S, and the resulting currents difference is integrated by the CTIA 28 during a predetermined integration time TM.
• the output voltage Vaut of the CTIA 28 thus represents a measurement of the variation of the resistance of the detection bolometer 16 caused by the incident radiation to be detected, since the non-useful part of the current I ac related to the temperature of the substrate is compensated for, less in part, by the current I cm specifically produced to reproduce this non-useful part.
• a CTIA has an electrical dynamic output, or dynamic "reading", fixed. Below a first quantity of electrical charges received at the input, the CTIA delivers a fixed low voltage, called “low saturation voltage” (V satL ). Similarly, above a second quantity of electrical charges received at the input, the CTIA delivers a fixed high voltage called “high saturation voltage” (VsatH). Relation (1) expresses the linear behavior of the CTIA, when it receives a greater amount of electric charges than the first quantity of electric charges, and lower than the second quantity of electric charges.
• the reading dynamic is essentially fixed by the value of the capacitance CM of the capacitor 32. In particular, when this capacitance is fixed, that is to say constant in time, the reading dynamic of the CTIA is also fixed.
• the low saturation voltages VsatL and high VsatH are the limits between which the CTIA provides an output considered to be linear, even though it is generally capable of providing lower or higher voltages. higher than these terminals.
• the capacitance of the integration capacitor also determines the sensitivity, or more exactly the response (better known as the "responsivity") of the detector.
• the response of a detector is defined by the variation of the Apply output signal in relation to the variation of the input signal (scene temperature T sc ene) or DVout / dT sc ene.
• the observable dynamics of the scene, or "scene dynamics" is itself defined by the maximum temperature difference in a scene causing no saturation of the output signals of the CTIAs, or, in other words, the difference between the most high temperature does not induce high saturation of CTIA and the lower temperature does not induce low saturation of CTIA.
• the sensitivity (response) of a detector is therefore the ability of the detector to detect the details of a scene, whereas the detector's scene dynamics is its ability to transcribe, without distortion, very large temperature variations in a single detector. scene. It is thus difficult to simultaneously optimize these two contradictory quantities with a capacitance of the fixed integration capacitor.
• EP 3 140 906 it is known from EP 3 140 906 to use a reversal of the integration capacitor during the integration period Ti nt so as to modify the output voltage VOUT and extend the reading dynamics of the CTIA.
• An exemplary implementation of this document is described with reference to Figure 3 of the state of the art.
• This figure describes an integration device 60 comprising a CTIA type integrator comprising an operational amplifier 62 and a single capacitor 64, of fixed capacitance O , connected between the inverting input (-) and the output of the amplifier. 62.
• the non-inverting input (+) of the latter is connected to a positive and constant voltage VBUS and the inverting input (-) is connected to the input or integration node E through which an electric current I flows. to integrate.
• a switch 66 driven by a signal HDraz, is also provided in parallel with the capacitor 64, for the discharge thereof, and therefore its "reset".
• the device 60 is completed by a sample-and-hold circuit 68 connected to the output of the operational amplifier 62 for sampling and blocking the voltage V aut at the output of the latter.
• the device 60 comprises a circuit 70 for automatically extending the reading dynamics of the single CTIA 62, 64.
• This circuitry 70 comprises:
• circuit 72 reversing the direction of the connection of the capacitor 64 across the operational amplifier 62 on receipt of a control signal 77D [2: 0];
• a comparison circuit 74 detecting a switching condition of the capacitor 64 as a function of the voltage V out at the output of the amplifier 62 and generating the control signal HD ⁇ 2: 0];
• the switching circuit 72 comprises:
• a first switch 78 driven by a signal HDinv, connected between the inverting input (-) of the amplifier 62 and a first terminal 80 of the capacitor 64;
• a second switch 82 driven by a signal HDinv, connected between the output 84 of the amplifier 62 and a second terminal 86 of the capacitor 64;
• a third switch 88 driven by a signal HDinv, connected between the inverting input (-) of the amplifier 62 and the second terminal 86 of the capacitor 64;
• a fourth switch 90 driven by a signal HDinv, connected between the output 86 of the amplifier 62 and the first terminal 80 of the capacitor 64;
• phase generator 92 receiving the control signal HD ⁇ 2: 0] and producing the control signals HDinv and HDinv according to it.
• the HDinv and HDinv signals are in phase opposition. Switching the signal HDinv, and therefore the signal HDinv, therefore causes the inversion of the connection state of the capacitor 64, that is to say its switching.
• the comparison circuit 74 comprises, for its part:
• a comparator 94 receiving on a first terminal (+) the voltage V aut at the output of the amplifier 62 and, on a second terminal (-), a reference voltage VREF greater than the voltage VBUS and less than or equal to the voltage V high saturation its tH CTIA.
• the comparator 94 outputs a voltage S ⁇ mp having a first value when the voltage V aut is lower than the voltage VREF, and having a second value when the voltage V aut is greater than or equal to the voltage VREF.
• the switching of the voltage S COmp from the first value to the second value means that the voltage V aut is increasing and has just crossed the reference voltage VREF;
• a bit counter 96 whose counting input is connected to the output of the comparator 94.
• the integration device 60 comprises an "autozero" circuit 98 connected to the inverting input (-) of the amplifier 62, in order to cancel the offset of the amplifier 62 and the low frequency noise of this in a manner known per se, and for example described in the IEEE Journal of Solid-State Circuits, vol. sc-20, No. 3, June 1985.
• the signals HDraz and HDinv are activated in the high state by the generator 92.
• the closing of the switch 66 discharges the capacitor 64, and following this zeroing, the output voltage V out is equal to VBUS. Since the voltage VREF is greater than the voltage VBUS, the output of the comparator 94 is thus set to its lowest value.
• the autozero system 98 is also implemented.
• the reset command is then released, the generator 92 triggers the opening of the switch 66 and retains the state of the signals HDinv and HDinv.
• the opening of the switch 66 thus marks the beginning of the phase of integration of the input current / input, the autozero system 98 is active to subtract the input offset of the amplifier 62 during the entire phase of the current. 'integration.
• the generator 92 and the switch 66 thus form an initialization circuit of the device which determines the instant of the beginning of the integration period from the falling edge of the RAZ signal to the rising edge of the RAZ signal which marks the final moment of the integration period. Because of the integration, the voltage V out at the output of the amplifier 62 increases from the value VBUS.
• phase generator 92 switches the control signals HDinv and HDinv respectively on the low state and high state. This results in the switching of the capacitor 64 connections between the amplifier 62 and the autozero circuit 98.
• the load Q across the CTIA is of inverse polarity to that presented before switching, so that the output of the amplifier 62 is equal to:
• V out 2. VBUS-VREF (3)
• the output of the comparator 94 then switches to the low state since the voltage V out is strictly lower than the reference voltage VREF. The switching of the capacitor 64 thus reduces the output of the amplifier 62 to a lower level.
• the SCOMP output of the comparator 94 changes polarity again and increments the counter 96 again, and so on.
• the output voltage Vaut (Ti " t ) is sampled and blocked in the sample-and-hold circuit 68 by sending a pulse for the signal FSH while the binary values of the signal HD [2: 0] are also stored in a "latch" type memory stage 76 on reception of the pulse of the same signal FSH.
• the device 60 thus delivers, at the end of an integration phase, an HD signal SH [2: 0] representing the number of commutations of the capacitor 64 as well as the voltage VoutSH equal to the amplifier output voltage 62 .
• the equivalent reading dynamics can therefore be increased automatically by the value 2. (2 "). ⁇ VREF -VBUS), or in other words multiplied by 2", where n is the number of bits of the binary counter 96, which can correspond to a much higher dynamic than that of a conventional CTIA, depending on the maximum value of the binary counter used and the value of the reference voltage VREF.
• This device makes it possible to obtain an automatic and autonomous extension of the reading dynamics of the CTIA as a function of the quantity of electric charges received, without modifying the sensitivity of the signal forming chain, in particular the value of the capacitor and the integration time.
• the capacitor is switched off without being discharged.
• the conserved electrical charges define, after switching, a new voltage at the output of the CTIA, lower (when the output voltage is increasing) than the one before switching, from which integration continues.
• the useful output signal is determined as a function of the number of switches, the decrement (or increment) of voltage produced by a switching, and optionally the output voltage of the CTIA at the end of the integration time.
• this device has spurious noise during switching of the integration capacitor which are visible on the output voltage.
• the document WO 2017/135815 proposes an electronic assembly of the "analog-digital converter" type in which the input voltage to be converted can be in a higher voltage range than the voltage range of the converter.
• the input voltage range can range from -10 to + 10V, while the analog-to-digital converter can only convert between-2.5 and + 2.5V.
• a charge transfer is realized in a feedback-mounted capacitor on the operational amplifier, so as to change the input voltage when the output voltage of the operational amplifier reaches a threshold value.
• the assembly of WO 2017/135815 aims to increase the input dynamics of the circuit.
• the invention aims to increase the dynamic output of the circuit by integrating an input current over an output voltage range greater than the output range available on the operational amplifier.
• WO 2017/135815 proposes to convert a voltage while the invention aims to integrate a current.
• the document WO 2017/135815 does not include an integrator assembly but only an amplifier assembly.
• the technical problem of the invention consists in obtaining a device for integrating an electric current received on an integration node exhibiting an extended reading dynamic without compromising the sensitivity of the system, while limiting the noise in the final signal delivered. .
• the invention proposes to replace the reversal mechanism of the integration capacitor with a circuit allowing a transfer of charges in the integration capacitor.
• the invention firstly relates to a device for integrating an electric current received on an integration node during an integration period, said device comprising:
• an operational amplifier having two inputs and one output; a first input being connected to said integration node and a second input being brought to a constant voltage;
• an integration capacitor connected between said first input and said output of said operational amplifier; said output delivering an output voltage which varies as a function of the evolution of the quantities of charges in said integration capacitor; a circuit for modifying said output voltage;
• a comparison circuit configured to trigger said modification circuit at least once during said integration time when said output voltage is substantially equal to a reference voltage
• a storage circuit configured to store said number of trips occurring during said integration period.
• Said electric current received on said integration node is calculated as a function of said output voltage as well as said number of trips multiplied by said modification of said output voltage induced by said modification circuit.
• the invention is characterized in that the circuit for changing the output voltage is provided by a charge transfer circuit, configured to be connected to said integration node and to transfer charges into said integration capacitor when the comparison circuit detects that said output voltage is substantially equal to said reference voltage.
• the invention makes it possible to use an integration circuit in which the integration capacitor is permanently connected to the operational amplifier. In doing so, the invention makes it possible to limit the noise of the delivered final signal inherent to the multiple switches of the switches.
• the term “substantially” refers to the measurement uncertainties of the circuit performing the comparison.
• the modification circuit corresponds to a circuit with at least one switched capacitor comprising:
• charging means of said at least one switched capacitor configured to charge said at least one switched capacitor when said comparison circuit does not detect that said output voltage is substantially equal to said reference voltage; and means for discharging said at least one switched capacitor configured to connect said at least one switched capacitor to said integration node when said comparison circuit detects that said output voltage is substantially equal to said reference voltage.
• a switched capacitor circuit is also known as a "switched capacitor circuit".
• This switched capacitor circuit comprises a switched capacitor charging phase and a switched capacitor charge transfer phase in the integration capacitor. During the capacitor charging phase, this capacitor must be disconnected from the integration node. When transferring loads, the capacitor must be connected to the integration node. In addition, when the charge transfer is performed, the capacitor can be kept connected to the integration node without changing the behavior of the CTIA.
• this embodiment makes it possible to use the operation of a switched capacitor circuit to efficiently transfer the charges necessary to modify the charges of the integration capacitor and, thus, to modify the output voltage without degrading the behavior of the CTIA. .
• the modification circuit corresponds to a circuit with a switched capacitor, said modification circuit comprising:
• a first controlled switch connected between a low voltage and a first terminal of said switched capacitor
• said first and second switches being controlled when said comparison circuit does not detect that said output voltage is substantially equal to said reference voltage so as to charge said switched capacitor to a voltage value corresponding to said low voltage minus said constant voltage ;
• said third and fourth switches being controlled when said comparison circuit detects that said output voltage is substantially equal to said reference voltage so as to effect a charge transfer of said switched capacitor in said integration capacitor.
• This embodiment makes it possible to use a single additional capacitor per integration device to transfer the charges necessary for modifying the output voltage.
• the CTIA must manage a variation of charges at its input because the connection of the switched capacitor on the integration node modifies the input load of the CTIA compared to the phase in which the switched capacitor is not connected. on the CTIA.
• the modification circuit corresponds to a circuit with two switched capacitors, said modification circuit comprising:
• a first controlled switch connected between a low voltage and a first terminal of a first switched capacitor
• a second controlled switch connected between said constant voltage and a second terminal of said first switched capacitor
• a third controlled switch connected between a high voltage and said first terminal of said first switched capacitor
• a fifth controlled switch connected between said high voltage and a first terminal of a second switched capacitor
• a sixth controlled switch connected between said low voltage and said first terminal of said second switched capacitor
• said first, second, fifth and eighth switches being controlled when said comparison circuit does not detect that said output voltage is substantially equal to said reference voltage so as to charge said first switched capacitor and to carry out a charge transfer of said second capacitor switched in said integration capacitor;
• said third, fourth, sixth and seventh switches being controlled when said comparison circuit detects that said output voltage is substantially equal to said reference voltage so as to charge said second switched capacitor and to carry out a charge transfer of said first switched capacitor in said integration capacitor.
• This embodiment makes it possible to limit the input load variations of the CTIA because the integration node is always connected to one or the other of the switched capacitors.
• a switched capacitor When a switched capacitor has carried out a charge transfer in the integration capacitor, it remains connected to the integration node while the other switched capacitor is charged to be connected to the integration node during the next transition. . Thus, it is not necessary to disconnect the switched capacitor which has made a charge transfer, which limits the load variations on the CTIA and the high and low voltages.
• said two switched capacitors have substantially identical capacitance values. This embodiment makes it possible to obtain almost zero charge variations at the input of the CTIA and at the high and low voltages.
• the high and low voltages must meet different constraints, since the low voltage must charge the switched capacitor whereas the high voltage must allow the transfer of charges from the switched capacitor to the integration capacitor.
• the integration device comprises a generator of said low voltage having a stabilization time greater than the stabilization time of a generator of said high voltage.
• the stabilization time of the high voltage generator is as low as possible.
• the stabilization time of the generator of the low voltage can be higher because the charging time of the switched capacitor is greater than the charge transfer time.
• said high voltage generator and said low voltage generator are configured to supply said low and high voltages of several integration devices.
• This embodiment makes it possible to pool the low and high voltage generation circuit for several integration devices, for example in the context of the use of a matrix network comprising rows and columns with shared integration devices. for each column or for each line.
• said high voltage generator and / or said low voltage generator comprise at least one high voltage and / or low voltage decoupling capacitor.
• This embodiment makes it possible to improve the stabilization time of the generator by using decoupling capacitors with large values, for example between 10 ⁇ F and 100 ⁇ F.
• the modification circuit corresponds to a current injection circuit comprising a current generator and a switch connected between said current generator and said integration node; said switch being controlled by said comparing circuit so as to connect said current generator to said integration node when said comparison circuit detects that said output voltage is substantially equal to said reference voltage.
• a current generator does not modify the complex behavior of an integrator assembly when transferring charges into said integration capacitor.
• this embodiment makes it possible to use a simple current generator to efficiently transfer the charges necessary to modify the output voltage without degrading the behavior of the CTIA.
• this embodiment is very simple to implement.
• the current generator is produced by a current mirror assembly.
• This embodiment makes it possible to adapt the output impedance of the current generator to limit the disturbances of the CTIA.
• the subject of the invention is also an electromagnetic radiation detection system comprising:
• a detection element producing on an output terminal an electric current as a function of the electromagnetic radiation
• the first input terminal of the operational amplifier being able to be connected to the output terminal of the detection element for integrating the current produced by the detection element .
• the detection element comprises:
• a detection branch comprising a detection bolometer having a membrane suspended above a substrate and a bias circuit for adjusting the voltage across the detection bolometer as a function of a voltage setpoint;
• a compensating branch comprising a compensation bolometer carried substantially at the temperature of the substrate, and a bias circuit for adjusting the voltage across the compensation bolometer as a function of a voltage setpoint; and means for forming the difference between the current flowing through the detection bolometer and the current flowing through the compensation bolometer so as to form the electric current to be integrated.
• FIG. 1 is a circuit diagram of an infrared bolometric detector of the state of the art comprising CTIA type integrators for measuring the currents produced by the detection elements;
• FIG. 2 is an electrical diagram illustrating the reading of a sensitive bolometer of the detector of FIG. 1 with the aid of a compensation structure
• FIG. 3 is an electrical diagram of an optimized electrical current integration device of the state of the art
• FIG. 4 is a timing diagram illustrating the output signal of the integration stage and the reset signal of the device of FIG. 3;
• FIG. 5 is an electrical diagram of an electrical current integration device according to a first embodiment of the invention.
• FIG. 6 is an electrical diagram of an electrical current integration device according to a second embodiment of the invention.
• Figure 7 is an electrical diagram of an electric power integration device according to a third embodiment of the invention.
• FIG. 8 is an electrical diagram of the integration device of FIG. 7 in a calibration phase
• FIG. 9 is a timing diagram illustrating the various signals used to perform the calibration of the integration device of FIG. 7.
• the invention relates to an integration device having an increased dynamic using the principle described with reference to Figure 3, wherein the reversal of the integration capacitor 64 is replaced by a charge transfer circuit in the integration capacitor 64.
• FIGS. 5 and 6 illustrate two embodiments in which the charge transfer is obtained by the connection of a charged capacitor on the integration node
• FIG. 7 illustrates an embodiment in which the charge transfer is obtained by the injection of a current on the integration node E.
• an integration device 100a comprises a CTIA type integrator comprising an operational amplifier 62 and a capacitor 64, of fixed capacitance C mt , connected between the inverting input e and the output of the amplifier. 62.
• the non-inverting input e of the latter is connected to a positive and constant voltage VBUS, and the inverting input e is connected to the input or integration node E through which an electric current I to be integrated flows.
• a reset switch is provided in parallel with the capacitor 64, for the discharge thereof, and therefore its "reset".
• the device 100a is preferably completed by a sample-and-hold device (not shown) connected to the output of the operational amplifier 62 for sampling and blocking the voltage V aut at the output of the latter.
• the device 100a is completed by means of automatic extension of the reading dynamics of the only CTIA 62, 64 comprising:
• a switched capacitor circuit 105a connectable to the integration node E to effect charge transfer in the capacitor 64;
• a comparison circuit 74 detecting a charge transfer condition in the capacitor 64 as a function of the voltage Vaut at the output of the amplifier 62;
• phase generator circuit 107 for controlling the switched capacitor circuit 105a in accordance with the comparison circuit
• the switched capacitor circuit 105a comprises:
• a first controlled switch h connected between a low voltage VI and a first terminal of the capacitor C com ?
• a fourth controlled switch U connected between the integration node E and the second terminal of the capacitor C com.
• the first and second switches are controlled analogously and contrary to the control of the third and fourth switches.
• the switches are controlled by a non-overlapping phase generator circuit 107.
• phase generator circuit 107 With the aid of this phase generator circuit 107, the first and second switches, which have the same state, are open, while the third and fourth switches, which have the same state, are closed and vice versa.
• the comparison circuit 74 comprises a comparator 94 receiving on a first terminal (+) the voltage V aut at the output of the amplifier 62 and, on a second terminal (-) a reference voltage VREF greater than the voltage VBUS and less than or equal to a high saturation voltage V sa tH of CTIA.
• a binary counter (not shown) is connected to the output of the comparator 94 so as to count the number of times that the output voltage Vaut has reached the reference voltage VREF.
• the phase generator circuit 107 controls the closing of the third and fourth switches, and the capacitor C CO m is charged to the following value:
• the comparison circuit 74 sends a signal to the phase generator circuit 107 which controls, for a predetermined duration, the closing of the first and second switches and the opening of the third and fourth switches.
• the new charge of capacitor C CO m becomes equal to:
• the output output voltage V out is modified and the amplifier 62 continues to integrate the current I from the new value of its output voltage V aut .
• the predetermined duration is set so that the charge of the capacitor C CO m can be transferred into the capacitor 64 so as to modify the output voltage V out .
• the capacitor C CO m is disconnected from the integration node E and the capacitor C CO m is charged.
• the behavior of the output voltage V aut can therefore be analogous to that described with reference to Figures 4a and 4b, that is to say with several growth phases interspersed by phases of change of the output voltage V aut before the amplifier 62 enters the saturation phase.
• the output voltage V aut may exhibit a decreasing behavior over time with a punctual increase of the output voltage V out by the switched capacitor circuit 105a before reaching the low saturation voltage of the amplifier 62. .
• the phase generator circuit 107 controls the switches.
• other logic circuits may be used to control the switches based on the comparison circuit 74 without changing the invention.
• a buffer and a logic inverter may be arranged at the output of the comparison circuit 74 to directly control the switches.
• the device of FIG. 5 has high VH and low VV voltages used by the switched capacitor circuit 105a.
• the high Vh and low VV voltages can be generated by follower, inverter or any other voltage generating assembly.
• the two voltage generating assemblies may exhibit different behaviors because the low voltage generator VI is used to charge the capacitor C CO m, while the high voltage generator V H is used during the charge transfer. It is therefore preferable for the high voltage generator Vh to have the lowest possible settling time, unlike the low voltage generator VI, which can charge the capacitor C CO m for a much longer time without reducing the reading dynamics. .
• the two voltage generating assemblies are configured to supply the low voltages VI and high Vh of all the integration devices of a column.
• decoupling capacitors are provided on the low voltage VI and high VH when the load of the amplifiers is important.
• FIG. 6 illustrates a second embodiment of the invention in which the switched capacitor circuit 105b comprises:
• a first controlled switch h connected between the low voltage VI and the first terminal of a first capacitor C CO mi;
• a second controlled switch h connected between the constant voltage VBUS and a second terminal of the first capacitor C CO mi; a third controlled switch h connected between the high voltage Vh and the first terminal of the first capacitor C CO mi;
• a fifth controlled switch h connected between the high voltage Vh and a first terminal of a second capacitor C CO m2;
• the first, second, fifth and eighth switches are controlled analogously and contrary to the control of the third, fourth, sixth and seventh switches.
• the first, second, fifth and eighth switches are directly controlled by a first signal of the phase generator circuit 107, while the third, fourth, sixth and seventh switches are controlled by a second complementary signal of the phase generator circuit 107. .
• first, second, fifth and eighth switches which have the same state, are open while the third, fourth, sixth and seventh switches, which have the same state, are closed and vice versa.
• the embodiment of FIG. 6 always comprises a capacitor connected to the integration node E.
• a capacitor C.sub.CO.sub.i mi, C.sub.CO.sub.2 m2 previously charged is connected to the node of FIG. integration E, the charges of this capacitor are transferred to the capacitor 64. Following this phase of charge transfer, the connection of the capacitor on the integration node E has no impact on the integrator assembly.
• the operating equations of this second embodiment of FIG. 6 are identical to the equations described in relation to the first embodiment of FIG. 5.
• the charge transfer in the capacitor 64 is performed by a circuit with one or more switched capacitors.
• a current injection circuit may be used to effect charge transfer, as shown in FIG. 7.
• the current injection circuit 105c of FIG. 7 comprises a current generator 111 delivering a current I g on the integration node E when a switch 19 is closed.
• the current generator 111 may be realized by a current mirror arrangement, for example with a PMOS transistor.
• the switch 19 is controlled by a phase generator circuit 107, similar to the previously described circuit.
• the comparison circuit 74 detects that the output voltage VOUT is substantially equal to the reference voltage VREF
• the current generator 111 is connected to the integration node for a predetermined time T.
• This predetermined time T is clocked by a signal clock in the phase generator circuit 107, and makes it possible to define the quantity of charges transferred in the capacitor 64.
• the current generator 111 transmits a direct current to the integration node E, thus modifying the charges of the integration capacitor 64.
• the variation of the output voltage VOUT of the integrator assembly corresponds to the formula next :
• a current source 112 can be connected to the integration node E to inject a current I c .
• a first step consists in isolating the CTIA from the current I by opening the switch In.
• the output V out is variable and depends on the current I.
• the reset switch Reset is then closed to short-circuit the capacitor 64 and bring the output V out to the voltage VBUS, present on the input e + of the amplifier 62, while the switches b and I 10 are open.
• the comparator 94 switches, the current source 112 is disconnected from the integration node E by opening the switch ho , and the output value V aut is measured to obtain the value of the high voltage VI.
• the current source 111 can be replaced by a switched capacitor circuit, such that 5 or 6, as part of a measurement of the voltage variation DV out of one of these arrangements.
• the current source 111 is connected to the integration node E by closing the switch I 9 for a predetermined time T.
• the switch I 9 is then opened and the output value V out is measured to get the value of the low voltage V2.
• AV out is measured by the difference between the high voltage VI reduced by the low voltage V2.
• a detector for integrating the electric current from a sensitive site for example a bolometer
• a sensitive site for example a bolometer
• technical including: access to extended scene dynamics while maintaining a high sensitivity on the part of the image that is transcribable in the nominal electrical dynamics of the CTIA alone, while the linearity of the signal as a function of the flow is maintained unlike some systems logarithmic response for example;
• the frame frequency (defined by the number of times the whole matrix is read in one second) is kept identical to the usual standards (60Hz for example). In other words, there is no degradation of the information temporal density with respect to some state-of-the-art forms of dynamic extension;
• the obtained scene information is maintained in temporal coherence, or synchronicity, permanent with the scene.
• the space of time separating any event on the stage and the formation of the signal usable by the observer or the system using the signal output stream Vaut does not exceed a frame time, unlike all the detectors or systems whose data stream is over-sampled and / or computationally processed after forming the raw signals to obtain the information deemed exploitable with extended dynamic;
• the invention provides the advantage of not modifying the thermal cycle of the bolometer imposed by the Joule self-heating during the cycle of integration.
• This characteristic is particularly appreciable as to the stability of the continuous level as a function of ambient thermal operating conditions, in particular when small differences in the temperature of the scene are sought with good temporal stability.
• the effectiveness of the possible implementation of the detector without Peltier stabilization module (operation called "TEC-less” in English), increasingly common in the field, is therefore retained;
• parasitic capacitances that represent for example the gates of the connection switches and the connections themselves are an integral part of the integration capacitor and do not add in themselves any interference disturbance.
• the signal formed at the output therefore does not lose any form of quality as a result of the application of the invention.

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• 2018
  • 2018-03-02 FR FR1851818A patent/FR3078596B1/fr active Active
• 2019
  • 2019-02-27 CN CN201980010353.0A patent/CN111656681A/zh active Pending
  • 2019-02-27 KR KR1020207021659A patent/KR102607038B1/ko active IP Right Grant
  • 2019-02-27 EP EP19706685.5A patent/EP3759814A1/fr not_active Ceased
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