NL2016216B1 - Analog to digital data converter. - Google Patents

Analog to digital data converter. Download PDF

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Publication number
NL2016216B1
NL2016216B1 NL2016216A NL2016216A NL2016216B1 NL 2016216 B1 NL2016216 B1 NL 2016216B1 NL 2016216 A NL2016216 A NL 2016216A NL 2016216 A NL2016216 A NL 2016216A NL 2016216 B1 NL2016216 B1 NL 2016216B1
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NL
Netherlands
Prior art keywords
signal
analog
input
amplifier
output
Prior art date
Application number
NL2016216A
Other languages
Dutch (nl)
Inventor
Jeroen Bes Cees
Anton Serdijn Wouter
Lotfi Reza
Original Assignee
Univ Delft Tech
Tech Stw
Publiekrechtelijke Rechtspersoon Acad Ziekenhuis Leiden H O D N Leids Univ Medisch Centrum
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Application filed by Univ Delft Tech, Tech Stw, Publiekrechtelijke Rechtspersoon Acad Ziekenhuis Leiden H O D N Leids Univ Medisch Centrum filed Critical Univ Delft Tech
Priority to NL2016216A priority Critical patent/NL2016216B1/en
Priority to PCT/NL2017/050061 priority patent/WO2017135815A1/en
Application granted granted Critical
Publication of NL2016216B1 publication Critical patent/NL2016216B1/en

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/124—Sampling or signal conditioning arrangements specially adapted for A/D converters
    • H03M1/129—Means for adapting the input signal to the range the converter can handle, e.g. limiting, pre-scaling ; Out-of-range indication
    • H03M1/1295—Clamping, i.e. adjusting the DC level of the input signal to a predetermined value
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/14—Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit
    • H03M1/145—Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit the steps being performed sequentially in series-connected stages
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/18—Automatic control for modifying the range of signals the converter can handle, e.g. gain ranging
    • H03M1/181—Automatic control for modifying the range of signals the converter can handle, e.g. gain ranging in feedback mode, i.e. by determining the range to be selected from one or more previous digital output values
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/48—Servo-type converters
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/34—Analogue value compared with reference values
    • H03M1/36—Analogue value compared with reference values simultaneously only, i.e. parallel type
    • H03M1/361—Analogue value compared with reference values simultaneously only, i.e. parallel type having a separate comparator and reference value for each quantisation level, i.e. full flash converter type

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Analogue/Digital Conversion (AREA)

Abstract

Analog to digital data converter (ADC) (1) comprising an analog signal input (2) and a digital signal output (3), wherein an analog amplifier a signal modifier (4) is provided in a signal path (6) from the analog signal input (2) to the digital signal output (3), and wherein the converter (1) comprises a processor (5) for providing an analog offset signal that modifies an analog signal in the signal path (6) from the analog signal input to the amplifier (4)digital signal output (3), wherein the signal modifier is an analog amplifier (4) that receives an input signal composed of a signal from the analog signal input (2) and the analog offset signal from the processor (5), wherein both the input signal and the analog offset signal are provided to the analog amplifier (4) through separate capacitors circuit elements (C1; C3).

Description

Analog to digital data converter
The invention relates to an analog to digital data converter (ADC) comprising an analog signal input and a digital signal output, wherein a signal modifier is provided in a signal path from the analog signal input to the digital signal output, and wherein the converter comprises a processor for providing an analog offset signal that modifies an analog signal in the signal path from the analog signal input to the digital signal output.
Such an analog to digital converter is known from the article "An Additive Instantaneously Companding Read-out System for Cochlear Implants"; by Cees J. Bes; Chutham Sawigun and Wouter A. Serdijn; proceedings IEEE BioCAS, Paphos, Cyprus, November 3-5, 2010. The device known from this article is used to record the compound action potentials from a stimulated auditory nerve and is designed to cover a 126 dB dynamic range to enable registering both stimulus signals up to 20 V, and artefact and neural response signals which may be as little as down to 10 micro volts. The known system comprises an attenuator to modify the input signal followed by a sample and hold circuit and an ADC in series, as well as two comparator circuits in parallel to the sample and hold circuit and the ADC, which together with the two comparators feed a shift register. An offset generator derives a feedback signal from most significant bits available at the output of the comparators, which feedback signal is fed to the input of the sample and hold circuit so as to modify the output signal of the amplifier which also feeds the sample and hold circuit.
The inventors note that this known device represents a very high level circuit implementation and accordingly have set as an object of the instant invention to simplify the known device and to provide an analog to digital data converter with high dynamic range using high-voltage components to the least possible extent.
The analog to digital converter of the invention is provided with the features of one or more of the appended claims .
Essentially the analog to digital converter of the invention has the feature that the signal modifier is an analog amplifier that receives an input signal composed of an input signal from the analog signal input and the analog offset signal from the processor, wherein both the input signal and the analog offset signal are provided to the analog amplifier through separate circuit elements.
Preferably the circuit elements are capacitors, although resistors, inductors or even diodes could be applied. Using capacitors, and in particular using the capacitor at the input stage of the analog to digital converter, has the advantage not only to provide safety to the patient but also to enable creating a virtual reference voltage at the input of the amplifier itself.
According to the invention the output of the analog amplifier can be maintained at a low voltage by virtue of the analog offset signal at the input of the amplifier that compensates the larger part of the possibly high measurement input voltage at the analog signal input of the amplifier. The only high-voltage component that then remains to be applied in the device of the invention is the circuit element in the signal path from the analog signal input to the amplifier.
Preferential features of the analog to digital converter of the invention are provided in the dependent claims, such as the feature that the analog amplifier is a high gain operational amplifier provided with a feedback capacitor that directly connects the amplifier's output with its input.
Another preferential feature is that the analog amplifier feeds a comparator circuit that drives a counter circuit for determining the most significant bits representative of the analog input signal.
In order to complete the digital representation of the analog input signal advantageously the analog amplifier feeds an analog to digital converter for determining the least significant bits representative of the analog input signal. Beneficially this analog to digital converter can be a low-voltage device.
Suitably the comparator circuit comprises a preset high-voltage reference VH and a preset low voltage reference VL to determine in dependence of the output of the analog amplifier an up count signal and down count signal respectively for the counter circuit representing the said most significant bits representative of the analog input signal at the analog signal input.
In a preferred embodiment wherein use is made of capacitors for the circuit elements, the comparator circuit connects to control logic for switches that are arranged to connect a charged capacitor to the input of the analog amplifier, wherein the charge of the capacitor depends on a switching sequence of the switches.
The invention will hereinafter be further elucidated with reference to the drawing of some exemplary embodiments of an analog to digital converter according to the invention that is not limiting as to the appended claims.
In the drawing: -figure 1 shows a first embodiment of an analog to digital converter according to the invention; -figure 2 shows a second embodiment of an analog to digital converter according to the invention; -figure 3 shows a third embodiment of an analog to digital converter according to the invention; and -figure 4 provides an amplitude-time diagram showing signals of the analog to digital converter according to the invention as depicted in figure 2 and figure 3 in relation to a measurement input signal at the converter's analog signal input.
Whenever in the figures the same reference numerals are applied, these numerals refer to the same parts.
In the following preferred embodiments are depicted wherein the circuit elements are capacitors or in general impedances. This expresses the broadness of the claims which also includes the possibility that the circuit elements are diodes or other impedances such resistors or inductors.
Also without prejudice regarding possible other embodiments of the analog to digital converter of the invention, reference is made to figures 1 , 2 and 3, each representing a suitable embodiment of the converter according to the invention. In each of these shown embodiments the analog to digital converter is generally depicted with reference 1, and comprises an analog signal input 2 (Vin) and a digital signal output 3. There is also an analog output 3' as will be explained hereinafter .
In each said embodiment an analog amplifier 4 is provided in a signal path 6 from the analog signal input 2 to the digital signal output 3, and the converter 1 comprises a processor 5 (delineated by the broken lines) for providing an analog offset signal that modifies an analog signal in the signal path 6 prior to the amplifier 4. For this purpose the analog amplifier 4 receives an input signal composed of a measurement signal at the analog signal input 2 and the analog offset signal from said processor 5, wherein both the measurement signal and the analog offset signal are provided to the analog amplifier 4. In fig. 1 and fig. 2 said signals are fed through separate capacitors, notably a capacitor Cl which is applied to connect the analog signal input 2 that feeds the analog measurement signal to the amplifier 4, and a capacitor C3 which is applied to connect the output of the processor 5 to the amplifier 4. In the embodiment of figure 3 the general case is shown in which said signals are fed through separate impedances Z1 and Z3, which may be resistors or inductors.
Further in both embodiments of figure 1 and figure 2 the analog amplifier 4 is a high gain operational amplifier pro-vided with a feedback capacitor C2 that directly connects the amplifier's output 8 with its input 7. In the embodiment of figure 3 instead of the feedback capacitor C2 a feedback impedance Z2 is shown.
The amplifier's output 8 is further available as an analog output 3' of the converter that after conversion to the digital domain signify the least significant bits of the measurement signal at the analog signal input 2. For this conversion to the digital domain the analog amplifier 4 preferably further feeds a low-voltage analog to digital converter for determining the least significant bits representative of the measurement signal at the analog signal input 2 of the converter 1.
According to the invention in all embodiments of figures 1, 2 and 3 the analog amplifier 4 can be implemented as a low-voltage device, whereas only the earlier mentioned capacitor Cl (or impedance Zl) that connects the analog signal input 2 to the amplifier 4 must be a high-voltage component. Within the terms of this specification, high-voltage relates to voltages higher than 5 V.
In the embodiment of figure 1 the applied processor 5 is a digital to analog converter which provides a coarse feedback signal to the amplifier 4. The feedback signal is derived from the most significant bits that are available at the digital output 3 of the converter 1, which bits are representative of the measurement signal at the analog signal input 2 of the converter 1. The said feedback signal to the amplifier 4 arranges that the output of the amplifier 4 can remain at a low analog voltage value, which in turn is an analog signal at output 3' representative of the least significant bits of the measurement signal at the analog signal input 2 of the converter 1.
In the embodiments of figure 2 and figure 3 the processor 5 comprises several parts and features as comprised in the areas delineated by broken lines, as will be discussed in the following paragraphs.
Figure 2 and figure 3 show that the analog amplifier 4 feeds a comparator circuit 9 forming part of the processor 5, that drives a counter circuit 10 which is used for determining the most significant bits representative of the measurement signal at the analog signal input 2 of the converter 1.
Furthermore the comparator circuit 9 comprises a preset high-voltage reference VH and a preset low voltage reference VL to determine in dependence of the output 8 of the analog amplifier 4 an up count signal and down count signal respectively for the counter circuit 10, wherein the output of the counter circuit 10 represents the most significant bits of the measurement signal at the analog signal input 2 of the converter 1. The comparator circuit 9 connects to control logic 11 that also forms part of the processor 5, which control logic 11 drives switches phil - phi5 that are arranged to connect a charged capacitor C3 (figure 2) or in general an impedance Z3 (figure 3) to the input 7 of the analog amplifier 4.
In the embodiment of figure 2 the charge of the capacitor C3 depends on a switching sequence of the switches phil - phi5.
In the embodiment of figure 3 said switches phil - phi5 are arranged to connect an impedance Z3 to the input 7 of the analog amplifier 4.
For illustrative purposes an example of the switching sequence of the embodiment of figure 2 is provided by figure 4 which shows in its top graph a simulated measurement signal Vin present at the analog signal input 2 of the converter 1, as well as the said preset high-voltage reference VH and the preset low voltage reference VL which are used to determine in dependence of the output 8 of the analog amplifier 4 an up count signal and down count signal respectively for the counter circuit 10. The sawtooth signal that is shown between the levels of the voltage references VH and VL represents the residual voltage at the output 8 of the amplifier 4 which connects to output 3' of the converter, and from which signal a digital representation can be derived that signify the least significant bits representative of the analog signal at the analog signal input 2. The digital representation can simply be derived with an off-the-shelf low-voltage analog to digital converter .
The two lower graphs of figure 4 show in the left graph the switching sequence of the respective switches phil -phi5 when the level of the measurement signal at the analog signal input 2 of the converter 1 is increasing, and in the right graph the switching sequence of the respective switches phil - phi5 is shown when the level of the measurement signal at the analog signal input 2 of the converter 1 is decreasing. In the left graph the switching sequence of the switches phil - phi5 arranges for adding negative charge packets via capacitor C3 to the input 7 of the analog amplifier 4 to compensate for the increasing measurement signal, whereas in the right graph a different switching sequence of the switches phil -phi5 applies that arranges to add positive charge package to the input 7 of the analog amplifier 4 to compensate for the decreasing measurement signal. Accordingly the output 8 of the analog amplifier 4 and output 3' of the converter is maintained at a low-voltage enabling that this analog amplifier 4 can indeed be implemented as a low-voltage device.
The operational behavior of the embodiment of figure 3 is comparable to what has been elucidated with reference to the embodiment of figure 2 as shown in figure 4, wherein of course account must be taken for the different type of impedance that may be applied. This is however all within the general knowledge of the skilled person and requires no further elucidation .
Although the invention has been discussed in the foregoing with reference to exemplary embodiments of the apparatus of the invention, the invention is not restricted to these particular embodiments which can be varied in many ways without departing from the invention. It is for instance possible to use resistors, inductances or diodes instead of capacitors, and this can be implemented by the skilled person using his general knowledge. The discussed exemplary embodiments shall therefore not be used to construe the appended claims strictly in accordance therewith. On the contrary the embodiments are merely intended to explain the wording of the appended claims without intent to limit the claims to these exemplary embodiments. The scope of protection of the invention shall therefore be construed in accordance with the appended claims only, wherein a possible ambiguity in the wording of the claims shall be resolved using these exemplary embodiments .

Claims (7)

1. Analoog-digitaalconvertor (ADC) (1) omvattende een analoge signaalingang (2) en een digitale signaaluitgang (3), waarbij een signaalbewerker (4) voorzien is in een signaalpad (6) van de analoge signaalingang (2) naar de digitale signaaluitgang (3), en waarbij de convertor (1) een processor (5) omvat voor het verschaffen van een analoog offset-signaal dat een analoog signaal in het signaalpad (6) van de analoge signaalingang naar de digitale signaaluitgang (3) modificeert, met het kenmerk, dat de signaalbewerker een analoge versterker (4) is die een ingangssignaal ontvangt dat is samengesteld uit een signaal van de analoge signaalingang (2) en het analoge offset-signaal van de processor (5), waarbij zowel het ingangssignaal als het analoge offset-signaal naar de analoge versterker (4) gevoerd zijn via afzonderlijke schakelingele-menten (Cl, Zl; C3, Z3).An analog-to-digital converter (ADC) (1) comprising an analog signal input (2) and a digital signal output (3), wherein a signal processor (4) is provided with a signal path (6) from the analog signal input (2) to the digital signal output (3), and wherein the converter (1) comprises a processor (5) for providing an analog offset signal that modifies an analog signal in the signal path (6) from the analog signal input to the digital signal output (3), characterized in that the signal processor is an analog amplifier (4) that receives an input signal composed of a signal from the analog signal input (2) and the analog offset signal from the processor (5), wherein both the input signal and the analogue offset signal to the analog amplifier (4) via separate circuit elements (C1, Z1; C3, Z3). 2. ADC volgens conclusie 1, met het kenmerk, dat de analoge versterker (4) een hoge versterking operationele versterker is die voorzien is van een terugkoppelschakelingele-ment (C3; Z3) dat een directe verbinding verschaft tussen de uitgang (8) en de ingang (7) van de versterker.ADC according to claim 1, characterized in that the analog amplifier (4) is a high-gain operational amplifier which is provided with a feedback circuit element (C3; Z3) which provides a direct connection between the output (8) and the input (7) of the amplifier. 3. ADC volgens conclusie 1 of 2, met het kenmerk, dat de analoge versterker (4) een vergelijkingsschakeling (9) voedt met welke een tellerschakeling (10) verbonden is voor het bepalen van de meest significante bits die het ingangssignaal op de analoge signaalingang (2) representeren.ADC according to claim 1 or 2, characterized in that the analog amplifier (4) supplies a comparison circuit (9) to which a counter circuit (10) is connected for determining the most significant bits that have the input signal on the analog signal input (2) represent. 4. ADC volgens één der voorgaande conclusies 1-3, met het kenmerk, dat de analoge versterker (4) een analoog-digitaalconvertor voedt voor het bepalen van de minst significante bits die het ingangssignaal op de analoge signaalingang (2) representeren.ADC according to one of the preceding claims 1 to 3, characterized in that the analog amplifier (4) supplies an analog-to-digital converter for determining the least significant bits that represent the input signal on the analog signal input (2). 5. ADC volgens conclusie 3 of 4, met het kenmerk, dat de vergelijkingsschakeling (9) een vooraf bepaalde hoog-spanningsreferentie VH en een vooraf bepaalde laagspanningsre-ferentie VL omvatten voor het in afhankelijk van een signaal aan de uitgang (8) van de analoge versterker (4) bepalen van een optelsignaal respectievelijk aftelsignaal voor de teller-schakeling (10) die de meest significante bits representeert.ADC according to claim 3 or 4, characterized in that the comparison circuit (9) comprises a predetermined high-voltage reference VH and a predetermined low-voltage reference VL for dependent on a signal at the output (8) of the analogue amplifier (4) determining an addition signal or countdown signal for the counter circuit (10) representing the most significant bits. 6. ADC volgens één der conclusies 1-5, met het kenmerk, dat de schakelingelementen {Cl, Zl; C3, Z3) condensatoren {Cl; C3) zijn.ADC according to one of claims 1 to 5, characterized in that the circuit elements {C1, Z1; C3, Z3) capacitors {C1; C3). 7. ADC volgens conclusie 6, met het kenmerk, dat de vergelijkingschakeling (9) in verbinding staat met regellogica (11) voor schakelaars {phil - phi5) die zijn ingericht voor het verbinden van een geladen condensator (C3) met de ingang (7) van de analoge versterker (4), waarbij de lading van de condensator (C3) afhankelijk is van een schakelvolgorde van de schakelaars (phil - phi5).ADC according to claim 6, characterized in that the comparison circuit (9) is connected to control logic (11) for switches {phil - phi5) which are adapted to connect a charged capacitor (C3) to the input (7) ) of the analog amplifier (4), the charge of the capacitor (C3) being dependent on a switching sequence of the switches (phil - phi5).
NL2016216A 2016-02-03 2016-02-03 Analog to digital data converter. NL2016216B1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
NL2016216A NL2016216B1 (en) 2016-02-03 2016-02-03 Analog to digital data converter.
PCT/NL2017/050061 WO2017135815A1 (en) 2016-02-03 2017-02-01 Analogue to digital data converter

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NL2016216A NL2016216B1 (en) 2016-02-03 2016-02-03 Analog to digital data converter.

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR3078596B1 (en) 2018-03-02 2020-02-14 Ulis HIGH DYNAMIC DEVICE FOR INTEGRATING AN ELECTRIC CURRENT
US11469088B2 (en) * 2020-10-19 2022-10-11 Thermo Finnigan Llc Methods and apparatus of adaptive and automatic adjusting and controlling for optimized electrometer analog signal linearity, sensitivity, and range

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4517550A (en) * 1981-10-27 1985-05-14 Shimadu Corporation Analog to digital conversion method and apparatus
US5014056A (en) * 1988-05-11 1991-05-07 Analog Devices Kk A/D converter with a main range up/down counter and a subrange A/D converter

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4517550A (en) * 1981-10-27 1985-05-14 Shimadu Corporation Analog to digital conversion method and apparatus
US5014056A (en) * 1988-05-11 1991-05-07 Analog Devices Kk A/D converter with a main range up/down counter and a subrange A/D converter

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