EP3667728A1 - Verfahren zur herstellung einer vorrichtung mit lichtemittierenden und/oder lichtempfangenden dioden und mit einem selbst ausgestimmten kollimationsgitter - Google Patents

Verfahren zur herstellung einer vorrichtung mit lichtemittierenden und/oder lichtempfangenden dioden und mit einem selbst ausgestimmten kollimationsgitter Download PDF

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EP3667728A1
EP3667728A1 EP19213658.8A EP19213658A EP3667728A1 EP 3667728 A1 EP3667728 A1 EP 3667728A1 EP 19213658 A EP19213658 A EP 19213658A EP 3667728 A1 EP3667728 A1 EP 3667728A1
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Prior art keywords
substrate
layer
diodes
openings
stack
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French (fr)
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EP3667728B1 (de
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Gabriel Pares
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Commissariat a lEnergie Atomique et aux Energies Alternatives CEA
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Commissariat a lEnergie Atomique CEA
Commissariat a lEnergie Atomique et aux Energies Alternatives CEA
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Definitions

  • this increase in resolution must be done by limiting the losses linked to the reception sensitivity and / or the emissivity of the devices, which implies that the reduction in the useful or sensitive surface of the pixels, that is to say the reception and / or emission surface of the pixels, either accompanied by a reduction in the surface of the peripheral dead zones, that is to say of the surface not emitting or receiving no light , which correspond for example to the regions occupied by the electrodes of the diodes and by the isolation regions located between and around the pixels.
  • This reduction in the surface of the peripheral dead zones involves minimizing their width around the pixels while maintaining or improving the optical separation between the pixels.
  • an optical pixel separation element disposed above the emissive and / or receiving face of the pixels.
  • Such an optical pixel separation element called collimation grid or separation grid, makes it possible to avoid parasitic reflections between neighboring pixels and, in the case of a photo-emitting device, to improve the directivity of light emission. .
  • the collimation grid is reported above the pixels, after their completion.
  • the walls forming the collimation grid are produced as thinly as possible, for example with a width less than about 5 ⁇ m for pixels each having a useful area whose sides have a dimension (width) equal to approximately 40 ⁇ m, and with a significant height, for example greater than approximately 10 ⁇ m.
  • Such dimensions lead to the collimating grid having a significant aspect ratio (height / width ratio), for example greater than 2.
  • the verticality, the low roughness and a good reflectivity of the walls make it possible to obtain a collimation grid which does not disturb the reflection, diffraction and diffusion of the optical signals received and / or emitted by the pixels.
  • such a collimation grid can be performed during the manufacturing of the interconnection levels, also called BEOL (“Back-End Of Line”), of the device.
  • BEOL Back-End Of Line
  • One of these interconnection levels, formed on the side of the front face of the diodes, can be dedicated to the production of the collimation grid. This configuration makes it possible to obtain a high degree of integration, and therefore a small footprint, as well as good alignment of the collimation grid with the pixels.
  • this configuration is not applicable to a device producing a light emission and / or reception from the rear face of the diodes because the interconnection levels are made on the front of the device.
  • the height of the collimation grid thus obtained is limited by the techniques used to produce the interconnection levels, this height generally being between approximately 1 ⁇ m and 3 ⁇ m.
  • the collimation grid is therefore produced by a specific process implemented after the achievement of the interconnection levels, the transfer of the device to a support and removal of the substrate from which the device is made. The withdrawal of the substrate frees the rear face of the diodes on which the collimating grid is produced.
  • the main problems to manage in this case are the alignment of the collimation grid with the pixels, and the realization of the collimation grid with an important form factor.
  • the alignment accuracy obtained can be less than approximately 1 ⁇ m.
  • the alignment must take account of a possible deformation of the devices which may appear after having removed the substrates from which the devices are made.
  • the steps implemented to produce the collimation grid may be subject to constraints related in particular to the technique used to transfer the devices to their support, such as for example temperature constraints not to be exceeded or constraints on the chemicals that can be used without damaging the bonding interface between the devices and the support.
  • the collimation grid is produced on a unitary light emission and / or reception device, for example of millimeter size, transferred to a support corresponding for example to an active circuit of ASIC type ("Application-Specific Integrated Circuit", or integrated circuit specific to an application) by means of electrical connections of the type, for example, micro-pillar or micro-ball, it is difficult to obtain a good alignment between the collimation grid and the pixels because the techniques of microelectronics are no longer usable for the creation of the collimation grid. he It is also difficult to produce the collimation grid with a large form factor taking into account the methods applicable to this scale and the topology of the device.
  • the collimation grid cannot be produced on the device before it is transferred to the support because on the one hand it is necessary to secure the device to the support before removing the substrate to keep good mechanical stability of the assembly , and on the other hand the topology created by the collimation grid would make it very difficult to transfer the device to its support.
  • a collimation grid on a unitary light emission and / or reception device it is possible to reconstitute a plate from the devices previously transferred to their supports (for example diodes each assembled on a CMOS chip), in order to allow the use of microelectronics techniques capable of achieving the alignment performance and the resolution necessary for producing the collimation grid.
  • Such a method involves securing the devices and their supports on a plate, then making a flat surface by embedding them in an encapsulation material without damaging the devices.
  • the collimation grid is then produced by lithography on the rear faces of the devices.
  • An object of the present invention is to provide a solution for optically separating the adjacent pixels of a photo-emitting and / or photoreceptor device on the rear face while minimizing the area occupied on the device to achieve it, offering good alignment between the pixels and the collimation grid used to achieve this optical separation, which is compatible with the production of a collimation grid having a high aspect ratio, for example greater than or equal to 2, and which can be applied to unitary devices or to several devices arranged on the same support.
  • the collimating grid and the first electrodes of the diodes are formed by the same elements (the first electrically conductive portions), using, for their production, the substrate from which the diodes are produced.
  • the collimating grid is self-aligned with the first electrodes of the diodes, which limits the optical losses within the device and eliminates the problems of alignment of the collimating grid with respect to the diodes encountered in the methods. of the prior art. This also makes it possible to reduce the dimensions of the dead zones within the device since no surface is lost due to a misalignment between the collimation grid and the pixels.
  • the elements forming the collimating grid are produced before the substrate is removed, which avoids the problems linked to a possible deformation of the diodes which may appear after having removed the substrate, and removes the constraints related to the technique used to transfer the devices on their support since the elements of the collimation grid are produced before the substrate is removed.
  • This method also has the advantage of making it possible to produce the collimation grid with a very favorable geometry in order to obtain good optical insulation performance between the pixels and low spurious reflections between the pixels.
  • the collimating grid can in particular be produced such that the parts of the first electrically conductive portions forming this grid have a form factor for example greater than 2, or advantageously greater than or equal to 4.
  • This method also offers great freedom regarding the geometry with which the elements of the collimation grid are made, because the shape of the parts of the first electrically conductive portions forming the collimation grid is defined by the shape of the first openings made in the substrate which can be easily adapted according to needs.
  • This method also has the advantage of being able to be implemented on the scale of the substrate by microelectronics techniques with great precision, great robustness and great reproducibility, but also for unitary devices.
  • This process advantageously combines the production of the collimation grid with a production of the electrodes of the diodes which is efficient and which contributes to the optimization of the useful surface of the diodes.
  • the collimation grid thus produced does not exhibit any discontinuity with the first electrodes of the diodes, which leads to better mechanical strength of the collimation grid on the diodes, a weaker cross-talk, and a reduction in reflections. parasites within the device.
  • the simultaneous production of the collimation grid and the first electrodes of the diodes also makes it possible to reduce the total number of steps to be implemented in order to produce the collimation grid and the first electrodes of the diodes.
  • This method applies to the production of a device, the diodes of which provide photo-emission and / or photo-reception from a rear face of the stack of layers (face located on the side of the substrate on which the stack of layers is arranged).
  • the diodes can be electrically interconnected at their front faces.
  • the diode junctions correspond to p-i-n junctions.
  • the part of the substrate in which the additional etching extending the first openings is carried out can have a thickness of between 1 ⁇ m and 20 ⁇ m. This depth can correspond to the height of the collimation grid obtained.
  • the final height of the collimating grid of the device may however be different from this depth if for example additional portions of electrically conductive material are formed on the first electrically conductive portions, for example after having removed the substrate, to increase the height of the collimation grid.
  • the part of the substrate in which the additional etching extending the first openings is implemented may have a thickness greater than 3 ⁇ m in order to obtain a collimation grid with a height greater than 3 ⁇ m.
  • a ratio between the thickness of the part of the substrate in which the additional etching extending the first openings is implemented and a smaller dimension of each first opening in a plane parallel to an interface between the substrate and the stack of layers (this smaller dimension corresponding to the width of the parts of the first electrically conductive portions forming the collimation grid), corresponding to the aspect ratio of parts of the first electrically conductive portions forming the collimation grid, can be greater than or equal to 2, or even advantageously greater than or equal to 4.
  • the first etching of the stack can be implemented such that the first openings also pass through part of the first layer, and the dielectric portions can be produced such that they cover, in the first openings, lateral flanks of said part. of the first layer. This configuration allows good electrical insulation to be formed between the first electrodes and the second semiconductor layer.
  • This dielectric mask also contributes to achieving good electrical insulation between the first and second electrodes at the front faces of the diodes.
  • the second etching of the stack can be carried out such that the lateral flanks of the dielectric portions are aligned with the lateral flanks of the portions of the first layer.
  • the method can also comprise, between the second etching of the stack and the production of the first electrically conductive portions, the production of second openings passing through the dielectric mask and in which the second electrodes can be at least partially produced.
  • the first and second electrodes can be produced by depositing at least one electrically conductive material in the first and second openings and on the dielectric mask, then by implementing a planarization step of the electrically conductive material with stopping on the dielectric mask.
  • the stack can also comprise an electrically conductive layer such that the second layer is disposed between the electrically conductive layer and the first layer, and the first etching of the stack can be implemented such that the first openings pass through the layer electrically conductive and delimit portions of the electrically conductive layer forming a part of each of the second electrodes.
  • the method may further comprise, between the production of the first electrically conductive portions and the removal of the substrate, the implementation of a transfer of the stack and of the substrate on a support such that the stack is disposed between the substrate and the support.
  • the front face of the stack is arranged opposite the support.
  • the transfer of the stack and the substrate can be implemented with electrically conductive connection elements electrically connecting the first and second electrodes of the diodes to the support during the implementation of the transfer of the stack and the substrate on the support .
  • the step of removing the substrate can be implemented collectively for several devices with photo-emitting and / or photo-receiving diodes each comprising a stack and a substrate transferred onto a support, and the supports of the devices with photo-emitting diodes and / or photo-receptors can be secured to a retaining plate before the implementation of the step of removing the substrate.
  • the first openings can be made such that they form a grid pattern surrounding each of the diodes.
  • each of the first openings delimiting pn junctions of photo-emitting diodes has a smaller dimension, at the level of a bottom wall formed in the substrate, which is less than a smaller dimension of the first opening at an interface between the substrate and the stack, and / or each of the first openings delimiting pn junctions of light-receiving diodes has a smaller dimension, at the level of the bottom wall formed in the substrate, which is greater than the smallest dimension of the first opening at the interface between the substrate and the stack.
  • Such a configuration is favorable for improving the directivity of emission of the photo-emitting diodes and reducing the cross-talk between photo-receiving diodes.
  • the method may also include, after the step of removing the substrate, the implementation of a step of depositing at least one anti-reflection and / or metallic layer on the collimation grid, and / or the setting implementing a treatment increasing the roughness of the collimation grid. Such steps can improve the optical qualities of the collimation grid.
  • the Figures 1A to 1J represent the steps of a method for producing a device 100 with photo-emitting and / or photo-receiving diodes according to a particular embodiment.
  • the device 100 comprises several diodes 102 forming at least one matrix of diodes and serving as matrix (s) of pixels of the device 100.
  • the diodes 102 can be produced one beside the other without forming an array of diodes, that is to say without regular spacing between them.
  • the diodes 102 correspond to photo-emitting diodes, here LEDs.
  • the device 100 is produced from a substrate 104 comprising for example sapphire and / or silicon and / or a semiconductor for example similar to that used to form the active part of the diodes 102, and / or of the silicide of carbon and / or glass and / or any other material allowing the substrate 104 to form a growth substrate allowing the production of the semiconductor stack forming the active part of the diodes 102.
  • the substrate 104 serves as a support for the deposition and / or the growth of layers intended for producing the diodes 102 of the device 100.
  • a stack 106 of layers is formed on the substrate 104. This stack 106 comprises materials from which the diodes 102 will be produced.
  • the stack 106 comprises a first layer 108 of semiconductor doped with a first type of conductivity, for example of the n type, deposited on the substrate 104.
  • this first layer 108 corresponds to a superposition of several separate layers of semiconductor, for example a layer 110 of n + doped semiconductor with a donor concentration for example of between approximately 5.10 17 and 5.10 20 donors / cm 3 on which is placed another layer 112 of n- doped semiconductor with a concentration of donors for example between approximately 10 17 and 5.10 19 donors / cm 3 .
  • layer 110 comprises GaN and layer 112 comprises InGaN.
  • the thickness of layer 110 is for example greater than approximately 100 nm, and here equal to approximately 3 ⁇ m, and that of layer 112 is for example between approximately 5 nm and 500 nm.
  • the total thickness of the first layer 108 that is to say the sum of the thicknesses of the layers 110 and 112 in the example described here, is for example between approximately 20 nm and 10 ⁇ m, and preferably between about 2 ⁇ m and 4 ⁇ m.
  • the layer 110 here forms a buffer layer disposed between the layer 112 and the substrate 104 and is used in particular to filter the growth defects of the layer 112 so that these defects are not found in the layer 112.
  • the layers 110 and 112 can be doped with the same level of n-type doping (unlike the case described above where the layer 110 is doped n + and the layer 112 is doped n-).
  • the first layer 108 may correspond to a single layer of n-doped semiconductor, and with a concentration of donors for example between approximately 10 17 and 5.10 20 donors / cm 3 , comprising for example GaN and whose the thickness is for example between approximately 20 nm and 10 ⁇ m, and advantageously between approximately 2 ⁇ m and 4 ⁇ m.
  • the stack 106 also includes one or more emissive layers 114, for example five emissive layers 114, each intended to form, in the diodes 102, a quantum well.
  • emissive layers 114 On the figure 1A , only three emissive layers 114 are shown.
  • the emissive layers 114 comprise for example InGaN.
  • Each of the emissive layers 114 is arranged between two barrier layers (not visible on the figures 1A - 1J ), including for example GaN.
  • the emissive layers 114 are arranged on the first layer 108.
  • the emissive layers 114 comprise so-called intrinsic semiconductor materials, that is to say unintentionally doped (with a concentration of residual donors nest for example equal to approximately 10 17 donors / cm 3 , or between approximately 10 15 and 10 18 donors / cm 3 ).
  • the thickness of each of the emissive layers 114 is for example equal to approximately 3 nm and more generally between approximately 0.5 nm and 10 nm, and the thickness of each of the barrier layers is for example between approximately 1 nm and 25 nm.
  • the stack 106 also comprises a second layer 116 of semiconductor doped according to a second type of conductivity, opposite to that of the doping of the first layer 108 and therefore here of type p, with a concentration of acceptors for example between approximately 10 17 and 5.10 19 acceptors / cm 3 .
  • the second layer 116 is arranged on the emissive layers 114.
  • the first and second layers 108 and 116 (and more particularly the layers 112 and 116 in the example described here) are intended to form the pn junctions of the diodes 102.
  • the semi- conductor of the second layer 116 is for example GaN and its thickness is for example between approximately 20 nm and 10 ⁇ m.
  • an electron blocking layer (not visible on the figure 1A ) can be placed between the second layer 116 and the emissive layers 114, this electron blocking layer comprising for example AIGaN with for example about 12% aluminum and p-doped with a concentration of acceptors for example equal at approximately 1.10 17 acceptors / cm 3 .
  • the stack 106 also includes an electrically conductive layer 118 intended to form, in each of the diodes 102, part of a second electrode (corresponding to the anode in the example described here) which will be in contact with the semiconductor of the second layer 116.
  • the electrically conductive layer 118 is disposed on the second layer 116.
  • the electrically conductive material used is for example optically reflective, and corresponds for example to aluminum.
  • the stack 106 also includes a layer 120 intended to form a hard dielectric mask, placed on the electrically conductive layer 118.
  • the material of this layer 120 is for example Si0 2 .
  • the upper side of the layer 120 here forms a front face 122 of the stack 106, this front face 122 being on the side opposite to that disposed against the substrate 104.
  • a first etching of the stack 106 is implemented from the front face 122 of the stack 106 to form, in the stack 106, first openings 124 which will then be used to make the first electrodes (corresponding to the cathodes in the example described here) of the diodes 102 as well as the collimation grid of the device 100.
  • This first etching is first of all carried out in the layer 120 to form a dielectric mask 126 which will serve as an etching mask for the etching of the other layers of the stack 106.
  • the pattern formed by the first openings 124 in the dielectric mask 126 corresponds to that of the first electrodes of diodes 102 and of the collimating grid.
  • the first openings 124 are also intended to delimit portions of the first and second layers 108 and 116 forming the pn junctions of the diodes 102.
  • the diodes 102 are produced in the form of mesa structures, or structures in islets.
  • the cathodes of the diodes 102 form a cathode common to several diodes 102, or to all the diodes 102, of the device 100.
  • An etching of the electrically conductive layer 118 is then implemented according to the pattern of the dielectric mask 126. Remaining portions 128 of the layer 118 are intended to form parts of the second electrodes of the diodes 102.
  • etching of the second layer 116 is then implemented according to the pattern of the dielectric mask 126, forming portions 130 of doped semiconductor intended to form part of the pn junctions of the diodes 102 (see figure 1B ).
  • the layers 116, 118 and 120 are for example etched by the implementation of reactive ion etching by a plasma torch system, or ICP-RIE for "Inductively Coupled Plasma - Reactive Ion Etching".
  • the first openings 124 are extended by etching in the emissive layers 114 and in part of the thickness of the first layer 108, always according to the pattern defined by the dielectric mask 126. This etching is stopped at a depth level located in the first layer 108 and such that the bottom walls of the first openings 124 are formed by the first layer 108. In the example described here, the etching is stopped at a level located in layer 112 such that layer 110 and part of the thickness of layer 112 are not etched.
  • the thickness, referenced "b" on the figure 1C , the layer 112 which is etched is for example between approximately 100 nm and 5 ⁇ m.
  • the remaining thickness of the layer 112 denoted “e” therefore results from the choice of the initial thicknesses of the layers 110 and 112 and of the depth of the etching in the layer 112.
  • the choice of the etching depth produced, and therefore of the remaining thickness of the first layer 108 in the bottom of the first openings 124, depends in particular on the initial thickness of the first layer 108 (and therefore on the initial thicknesses of the layers 110 and 112 in the embodiment described here) and this so that the remaining thickness of the first layer 108 is sufficient to make good electrical contact between the semiconductor (s) of the first layer 108 and the first electrodes of the diodes 102 which will be produced subsequently in the first openings 124.
  • this etching can be stopped at the level of the upper face of the layer 110 such that this layer 110 is not etched but that the entire thickness of the layer 112 is etched. According to another variant, this etching can be stopped at a level located in the layer 110 such that, in the first layer 108, only part of the thickness of the layer 110 is not etched.
  • the remaining portions of the emissive layer or layers 114 form active areas 132 of the diodes 102.
  • This first etching also forms portions 134 of portions 136 of doped semiconductor intended to form, with the portions 130, the pn junctions (pin junctions in the example described here, due to the presence of the emissive layers 114 between the first and second layers 108, 116) of the diodes 102 (on the figure 1C , the parts 134 are symbolically delimited from the rest of the portions 136 by dotted lines).
  • first openings 124 corresponding to the distance between two neighboring diode mesa structures 102 is for example greater than or equal to about 50 nm, the minimum distance between two neighboring diodes 102 being defined by the minimum resolution of the lithography used.
  • This dimension “a” corresponds to the sum of the width of a portion of electrically conductive material which will be produced between the two mesa structures of the diodes 102 to form a cathode common to these diodes 102 and the thicknesses of two vertical dielectric portions which will be also arranged between the two mesa structures of the diodes 102.
  • the dimension "a" is a function of the width of the cathode produced between the diodes 102 which is chosen in particular as a function of the acceptable losses linked to the supply of electric current to the areas furthest from peripheral contact points.
  • the etching implemented is a dry etching, for example by a plasma based on Cl 2 or an RIE etching, for example ICP-RIE.
  • the dimensions of the sides of one of the mesa structures can be between approximately 500 nm and 1 mm, or between 500 nm and several millimeters, depending on the intended applications. For applications using high power diodes (for example LED bulbs to form car headlights), the dimensions of diodes 102 will be larger than for applications using lower power diodes 102.
  • a dielectric layer corresponding for example to a SiN / Si0 2 bilayer, and forming a passivation layer, is then deposited with a conforming thickness, for example between approximately 5 nm and 1 ⁇ m and advantageously equal to approximately 200 nm, on the dielectric mask 126 and along the walls of the first openings 124, thus covering the side walls of the dielectric mask 126, electrically conductive portions 128, semiconductor portions 130, active zones 132 and portions 134 of the portions 136.
  • the dielectric layer is also deposited on the non-etched parts of the first layer 108 forming the bottom walls of the first openings 124.
  • This dielectric layer is for example formed by a PECVD (chemical vapor deposition assisted by plasma) or ALD deposition (atomic layer deposition) depending on the nature of the material (s) deposited.
  • Anisotropic etching for example dry etching such as RIE etching, is then implemented such that the parts of the dielectric layer being in the first openings 124 and not covering the side walls of the mesa structures of the diodes 102 are deleted, thus revealing the parts of the first layer 108 located at the bottom of the first openings 124.
  • the parts of this dielectric layer covering the upper face of the dielectric mask 126 are also deleted.
  • portions 138 of the dielectric layer covering the side walls of the dielectric mask 126, electrically conductive portions 128, semiconductor portions 130, active areas 132 and portions 134 of the semiconductor portions 136 are retained. in the first openings 124.
  • a second etching of the stack 106 is implemented, extending the first openings 124 through the remaining thickness of the first layer 108 of semiconductor until reaching the substrate 104, that is to say up to 'so that the bottom walls of the first openings 124 are formed by the substrate 104.
  • This second etching makes it possible to delimit the portions of semiconductor 136 therebetween and completes the formation of the mesa structures of the diodes 102.
  • This second etching makes it possible to reveal lateral sides 140 of the portions 136 which will form electrical contact zones for the first electrodes of the diodes 102.
  • the portions of the dielectric mask 126, the electrically conductive portions 128, the semiconductor portions 130 and 136, the active areas 132 and the dielectric portions 138 form mesa structures, that is, that is, stacks in the form of islands, arranged on the substrate 104.
  • Each mesa structure of each diode 102 has a section, in a plane parallel to the face of the substrate 104 on which these structures rest, for example in the form of a disc .
  • Each of the mesa structures can therefore form a cylindrical island.
  • Mesa structures of different shape can be envisaged, for example in the form of a paving stone.
  • Another additional anisotropic etching step for example of the RIE or DRIE type and selective with respect to the materials of the diodes 102 other than that or those of the substrate 104, is implemented to extend the first openings 124 through a portion of the thickness of the substrate 104, called “c” on the figure 1E .
  • First electrically conductive portions are intended to be produced in the first openings 124 to form the first electrodes of the diodes 102 as well as the collimating grid of the device 100.
  • the depth "c" of the parts of the first openings 124 in the substrate 104 corresponds to the height of the collimation grid which will be obtained at the end of the process.
  • the value of this depth “c” thus depends on the type of diodes 102 and on the desired separation and / or focusing performance.
  • the depth “c” is for example between approximately 1 ⁇ m and 20 ⁇ m, and advantageously greater than or equal to approximately 10 ⁇ m.
  • the depth “c” is for example equal to 10 ⁇ m.
  • each of the portions 138 is called “d”
  • the width, or more generally the lateral dimension, of each of the first openings 124 in the substrate 104 is equal to "a - 2d”.
  • the dimensions a, c and d are therefore chosen such that the form factor (height / width) of the first openings 124 is advantageously greater than or equal to 2, or even greater than or equal to 4.
  • Second openings 142 are then produced through the dielectric mask 126, forming locations for the production of the second electrodes of the diodes 102 ( figure 1E ). These second openings 142 pass through the entire thickness of the dielectric mask 126 so that the bottom walls of the second openings 142 are formed by the electrically conductive portions 128. This etching is for example of the ICP-RIE type.
  • a first electrically conductive material 144 is then deposited in the first and second openings 124, 142 as well as on the dielectric mask 126 ( figure 1F ).
  • This first electrically conductive material 144 is deposited in a conforming manner, that is to say by forming a layer of substantially constant thickness on the dielectric mask 126 and along the side walls and the bottom walls of the first and second openings 124 , 142.
  • the first electrically conductive material 144 is formed by the deposit, for example PVD type, a first layer of titanium, for example between 5 nm and 300 nm thick, followed by deposition, for example PVD, of a second layer of aluminum, for example between about 50 nm and 1 ⁇ m.
  • the deposition techniques used are chosen so that they are adapted to the large form factor of the volumes formed by the first openings 124, and correspond for example to those used to deposit the electrically conductive material or materials of the conductive vias or TSV (“Through-Silicon Via”).
  • the first electrically conductive material 144 is in electrical contact with the lateral flanks 140 of the semiconductor portions 136 in the first openings 124, and with the portions 128 at the bottom walls of the second openings 142.
  • a second electrically conductive material 146 is deposited by filling the remaining volumes of the first and second openings 124, 142.
  • the thickness of this second electrically conductive material 146 is such that it also covers the parts of the first electrically conductive material 144 disposed on the dielectric mask 126.
  • the second electrically conductive material 146 is for example copper which can be formed by the implementation of a full plate electrochemical deposition (ECD or “Electro-Chemical Deposition”), that is to say on the whole of the structure previously produced.
  • the diodes 102 of the future device 100 are completed by implementing a chemical mechanical planarization (CMP) in order to remove the portions of the first and second electrically conductive materials 144 and 146 which protrude from the first and second openings 124, 142 (see figure 1H ).
  • CMP chemical mechanical planarization
  • This planarization makes it possible to electrically isolate the electrically conductive materials present in the first openings 124 from those disposed in the second openings 142.
  • the electrically conductive materials present in the first openings 124 form first electrically conductive portions 148 extending over the entire height of the mesa structures of the diodes 102, which are electrically connected to the semiconductor portions 136 only at the flanks side 140, and which extend into the substrate 104.
  • the parts of these first electrically conductive portions 148 located at the mesa structures of the diodes 102 form the first electrodes of the diodes 102, and the parts of these first electrically conductive portions 148 are found in the layer 108 and in the substrate 104 are intended to form the collimation grid of the future device 100.
  • the electrically conductive materials present in the second openings 142 form second electrically conductive portions 150 corresponding to the second electrodes of the diodes 102, each in electrical contact with one of the semiconductor portions 130 via one of the electrically portions conductive 128.
  • the structure obtained comprises an upper face 147 which is substantially planar, formed by the upper faces of the first and second electrically conductive portions 148, 150, of the dielectric portions 138 and of the dielectric mask 126.
  • This face 147 corresponds to the front face of the diodes 102 at which electrical connections with the electrodes will be made.
  • the first electrically conductive portions 148 are well electrically insulated from the semiconductor portions 130 and from the active areas 132.
  • the thickness “d” of the dielectric portions 138 can be chosen such that a leakage current acceptable is tolerated on each of the diodes 102, for example less than about 1% of the nominal current passing through the diode 102, when they are subjected to a potential difference (applied between the cathode and the anode) for example of the order of 4 Volts.
  • the minimum thickness of the dielectric portions 138 is for example between approximately 3 nm and 5 nm, or between 3 nm and 4 nm, depending on the material or materials used to make the dielectric portions 138.
  • the planarization step is advantageously put implemented until the first and second electrically conductive portions 148, 150 are over-etched relative to the dielectric materials of the portions 138 and of the dielectric mask 126, forming in the first and second electrically conductive portions 148, 150 hollows at the upper faces of these portions.
  • These recesses can have a depth, with respect to the plane of the upper face 147, of between approximately 5 nm and 150 nm.
  • This over-etching can be obtained by playing on the etching anisotropy and thanks to the etching selectivity which exists between the dielectric materials of the portions 138 and of the mask 126 and the materials of the electrically conductive portions 148, 150.
  • the CMP work has a different abrasion speed depending on the materials, and in the process described here, the abrasion of the materials of the electrically conductive portions 148, 150 is faster than that of the dielectric materials of the portions 138 and of the mask 126.
  • This is translated, at the level of the upper face 147, by a withdrawal of the materials from the electrically conductive portions 148, 150 with respect to the dielectric portions 138 and to the dielectric mask 126.
  • the electrodes of the diodes 102 remain perfectly isolated from one another thanks to an intrinsic property of the planarization implemented.
  • Such over-etching can also be implemented by an RIE etching process.
  • the semiconductor portions 136 are of the n type and the semiconductor portions 130 are of the p type.
  • the semiconductor portions 136 may be p-type and the semiconductor portions 130 may be n-type.
  • the first electrically conductive portions 148 form the anodes of the diodes 102 and the second electrically conductive portions 150 form, with the conductive portions 128, the cathodes of the diodes 102.
  • the substantially flat surface obtained at the level of the upper face 147 makes it possible to easily hybridize the matrix of diodes 102 produced with any type of support such as an electronic circuit.
  • any type of support such as an electronic circuit.
  • direct bonding also called bonding by molecular adhesion
  • the diode array 102 is transferred to a support 152 comprising electrical connection elements 154 to which the first and second electrodes of the diodes 102 are electrically connected.
  • the face 147 of the array of diodes 102 corresponding to the front faces of the diodes 102, is arranged opposite the support 152.
  • the electrical connection elements 154 correspond for example to balls of fusible alloy (comprising for example SnAg and / or indium), or copper pillars covered with solder material, or micro-inserts, or micro-tubes.
  • This support 152 can correspond to an electronic circuit, comprising for example CMOS electronic components, on which the diode array 102 is transferred and to which the diode array 102 is electrically connected. Such an electronic circuit can in particular be used to electrically control the diodes 102 corresponding for example to light-emitting diodes and / or to process the signals delivered by the diodes 102 corresponding for example to photodiodes.
  • the support 152 may correspond to a passive element not comprising electronic components, such as for example a card or an organic substrate.
  • connection pads 156 of UBM type are produced on the face 147, against the first and second electrodes of the diodes 102, before the diodes are transferred to the support 152. These connection pads 156 provide good electrical contact between the first and second electrodes of the diodes 102 and the electrical connection elements 154.
  • the presence of the substrate 104 makes it possible to ensure sufficient mechanical rigidity for handling and securing the diode array 102 to the support 154.
  • the substrate 104 is removed, thereby freeing the rear faces 158 of the diodes through which the light is intended to enter or exit depending on whether the diodes 102 are photo-emitting or photo-receiving diodes.
  • the techniques of removal of the substrate 104 which are implemented must take into account the presence of the parts of the first electrically conductive portions 148 located in the substrate 104 and which are intended to form the collimation grid. Thus, the removal process implemented is selective with respect to the material (s) of the first electrically conductive portions 148 present in the substrate 104.
  • the substrate 104 it is possible to remove at first a portion of the thickness of the substrate 104, in which the first electrically conductive portions 148 do not extend, by the implementation of a non-selective process, for example by lapping, then removing the remaining portions of the substrate 104 so selective, for example by chemical or physical etching. It is also possible to remove the substrate 104 by laser peeling ("laser lift-off"). When the substrate 104 comprises sapphire, this substrate 104 can be removed by RIE plasma etching. The technique or techniques used to remove the substrate 104 are adapted as a function of the material of the substrate 104.
  • the structure obtained after the removal of the substrate 104 is shown in the figure 1J .
  • the parts of the first electrically conductive portions 148 released from the substrate 104 form at least partially the collimation grid 160 of the device 100.
  • the collimation grid 160 After removing the substrate 104, it is possible to deposit one or more layers of material (x) on the collimation grid 160 and / or to carry out one or more surface treatments of the collimation grid 160.
  • a treatment aimed at improving the performance of the collimation grid 160 may include the deposition of a metallic material on the collimation grid 160, improving the optical qualities of the collimation grid 160 such as for example the anti-reflection properties of the collimation grid 160.
  • This treatment (for example an etching) can also increase the roughness of the collimation grid 160.
  • This treatment may or may not be selective with respect to the rear faces 158 diodes 102.
  • the device 100 advantageously comprises a matrix of diodes 102 which are light-emitting diodes, the microelectronic device possibly being part of a device LED display (screens, projector, video wall, etc.).
  • This matrix of diodes 102 comprises the first electrically conductive portions 148 which form a cathode common to all the diodes 102, and each diode 102 comprises a second electrically conductive portion 150 forming an anode making it possible to carry out the individual addressing of each of the diodes 102.
  • the microelectronic device 100 may comprise a matrix of diodes 102 which are photo-receiving diodes, or photodiodes.
  • the anodes and the cathodes of the diodes 102 are not used to supply current to the diodes 102 but are used to recover the currents photo-generated by the diodes 102.
  • the mesa structures of the diodes 102 may not comprise layers between the doped semiconductor portions 130 and 136 (corresponding to the emissive active areas or to portions of intrinsic semiconductor), and the p and n doped semiconductors are then placed directly against each other.
  • the first electrically conductive portions 148 are produced such that the parts forming the collimating grid 160 have lateral flanks substantially perpendicular to the rear faces 158 of the diodes 102.
  • the angles formed between these lateral flanks and the rear faces 158 of the diodes 102 are not equal to 90 °.
  • the first openings 124 can be made such that their width, at their bottom walls located in the substrate 104, is less than their width at a interface between the substrate 104 and the stack of layers forming the pn junctions of the diodes 102.
  • This profile of the first openings 124 is therefore found on the parts of the first electrically conductive portions 148 forming the collimation grid 160.
  • This particular profile of the grid collimation 160 is advantageous when the diodes 102 correspond to light-emitting diodes because such a grid of collimation makes it possible to reduce the stray reflections of the light emitted by the diodes 102.
  • the collimation grid 160 can be produced with a profile opposite to that described above, that is to say such that the width of the first electrically conductive portions 148, at level of the bottom walls located in the substrate 104, ie greater than their width at the interface between the substrate 104 and the stack of layers forming the pn junctions of the diodes 102.
  • This particular profile of the collimation grid 160 is advantageous when the diodes 102 correspond to photodiodes because such a collimation grid 160 makes it possible to reduce the cross-talk effect between the diodes 102.
  • the layer 110 after having removed the substrate 104, it is possible to partially etch the layer 110, over part of its thickness, in order to increase the height of the parts of the first electrically conductive portions 148 forming the collimation grid 160 .
  • the step of removing the substrate 104 and possibly of the partial etching of the layer 110 can be implemented collectively for several devices 100.
  • several future devices 100 each comprising the diodes 102 transferred to the support 152 but also comprising the substrate 104 are transferred to a retaining plate 200, and are for example held on this plate by means of a layer of temporary glue 202
  • the future devices 100 are protected by an encapsulating material 204, comprising for example a polymer, formed around the devices 100 but not covering the substrates 104 of the future devices 100 so that these substrates 104 are accessible.
  • the substrates 104 of future devices 100 can then be removed using the techniques described above, and this without risk of damaging the diodes 102 thanks to the presence of the encapsulating material 204.
  • the encapsulating material 204 is removed, for example by dissolution, and the devices 100 are detached from the retaining plate 200.
  • a step of processing the collimation grids 160 of the devices 100 can be implemented collectively before removing the encapsulating material 204.

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  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • Manufacturing & Machinery (AREA)
  • Led Devices (AREA)
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EP19213658.8A 2018-12-13 2019-12-04 Verfahren zur herstellung einer vorrichtung mit lichtemittierenden und/oder lichtempfangenden dioden und mit einem selbst ausgerichteten kollimationsgitter Active EP3667728B1 (de)

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FR1872886A FR3090200B1 (fr) 2018-12-13 2018-12-13 Procede de realisation d’un dispositif a diodes photo-emettrices et/ou photo-receptrices et a grille de collimation auto-alignee

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EP4092739A1 (de) * 2021-05-18 2022-11-23 Commissariat à l'énergie atomique et aux énergies alternatives Verfahren zur herstellung einer optoelektronischen vorrichtung, entsprechende vorrichtung und system mit dieser vorrichtung
FR3123153A1 (fr) * 2021-05-18 2022-11-25 Commissariat A L'energie Atomique Et Aux Energies Alternatives Procédé de fabrication d'un dispositif optoélectronique
FR3123145A1 (fr) * 2021-05-18 2022-11-25 Commissariat A L'energie Atomique Et Aux Energies Alternatives Procédé de fabrication d'un dispositif optoélectronique

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US11169326B2 (en) 2018-02-26 2021-11-09 Invensas Bonding Technologies, Inc. Integrated optical waveguides, direct-bonded waveguide interface joints, optical routing and interconnects
US11762200B2 (en) 2019-12-17 2023-09-19 Adeia Semiconductor Bonding Technologies Inc. Bonded optical devices
US11177397B2 (en) * 2020-01-09 2021-11-16 Vanguard International Semiconductor Corporation Semiconductor devices and methods for forming the same
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US11158759B1 (en) * 2020-04-16 2021-10-26 International Business Machines Corporation Chip carrier integrating power harvesting and regulation diodes and fabrication thereof
CN111864016B (zh) * 2020-06-30 2021-07-13 南京中电熊猫液晶显示科技有限公司 一种微型发光二极管的制造方法
US20220029050A1 (en) * 2020-07-21 2022-01-27 Lumileds Llc Methods of manufacturing a light-emitting device with metal inlay and top contacts
CN115832864A (zh) * 2021-09-18 2023-03-21 默升科技集团有限公司 到表面发射器的高频信号耦合

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EP4092736A1 (de) * 2021-05-18 2022-11-23 Commissariat à l'énergie atomique et aux énergies alternatives Verfahren zur herstellung einer optoelektronischen vorrichtung, entsprechende vorrichtung und system mit dieser vorrichtung
EP4092739A1 (de) * 2021-05-18 2022-11-23 Commissariat à l'énergie atomique et aux énergies alternatives Verfahren zur herstellung einer optoelektronischen vorrichtung, entsprechende vorrichtung und system mit dieser vorrichtung
FR3123153A1 (fr) * 2021-05-18 2022-11-25 Commissariat A L'energie Atomique Et Aux Energies Alternatives Procédé de fabrication d'un dispositif optoélectronique
FR3123145A1 (fr) * 2021-05-18 2022-11-25 Commissariat A L'energie Atomique Et Aux Energies Alternatives Procédé de fabrication d'un dispositif optoélectronique
FR3123152A1 (fr) * 2021-05-18 2022-11-25 Commissariat A L'energie Atomique Et Aux Energies Alternatives Procédé de fabrication d'un dispositif optoélectronique
FR3123146A1 (fr) * 2021-05-18 2022-11-25 Commissariat A L'energie Atomique Et Aux Energies Alternatives Procédé de fabrication d'un dispositif optoélectronique

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US11063172B2 (en) 2021-07-13
FR3090200B1 (fr) 2021-01-15
EP3667728B1 (de) 2021-03-31
CN111326613A (zh) 2020-06-23
US20200194614A1 (en) 2020-06-18
CN111326613B (zh) 2024-04-30
FR3090200A1 (fr) 2020-06-19

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