EP3606047B1 - Dispositif d'imagerie à semi-conducteurs et procédé d'entraînement de dispositif d'imagerie à semi-conducteurs - Google Patents

Dispositif d'imagerie à semi-conducteurs et procédé d'entraînement de dispositif d'imagerie à semi-conducteurs Download PDF

Info

Publication number
EP3606047B1
EP3606047B1 EP19189029.2A EP19189029A EP3606047B1 EP 3606047 B1 EP3606047 B1 EP 3606047B1 EP 19189029 A EP19189029 A EP 19189029A EP 3606047 B1 EP3606047 B1 EP 3606047B1
Authority
EP
European Patent Office
Prior art keywords
voltage
node
switch
signal
potential
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
EP19189029.2A
Other languages
German (de)
English (en)
Other versions
EP3606047A2 (fr
EP3606047C0 (fr
EP3606047A3 (fr
Inventor
Miku Goto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Brillnics Singapore Pte Ltd
Original Assignee
Brillnics Singapore Pte Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP2019116368A external-priority patent/JP7514065B2/ja
Application filed by Brillnics Singapore Pte Ltd filed Critical Brillnics Singapore Pte Ltd
Publication of EP3606047A2 publication Critical patent/EP3606047A2/fr
Publication of EP3606047A3 publication Critical patent/EP3606047A3/fr
Application granted granted Critical
Publication of EP3606047B1 publication Critical patent/EP3606047B1/fr
Publication of EP3606047C0 publication Critical patent/EP3606047C0/fr
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/709—Circuitry for control of the power supply
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14609—Pixel-elements with integrated switching, control, storage or amplification elements
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H04N25/766—Addressed sensors, e.g. MOS or CMOS sensors comprising control or output lines used for a plurality of functions, e.g. for pixel output, driving, reset or power
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H04N25/779—Circuitry for scanning or addressing the pixel array
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H04N25/7795—Circuitry for generating timing or clock signals
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H04N25/78—Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14643—Photodiode arrays; MOS imagers
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
    • H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/50—Control of the SSIS exposure
    • H04N25/53—Control of the integration time
    • H04N25/531—Control of the integration time by controlling rolling shutters in CMOS SSIS

Definitions

  • the present invention relates to a solid-state imaging device and a method for driving a solid-state imaging device.
  • CMOS complementary metal oxide semiconductor
  • the CMOS image sensor has been widely applied as a part of various electronic apparatuses such as a digital camera, a video camera, a surveillance camera, a medical endoscope, a personal computer (PC), a portable terminal device (mobile device) such as a mobile phone, etc.
  • CN 1 798 272 A discloses a CMOS image sensor.
  • CN 108 306 502 A discloses a charge pump circuit.
  • JP 2006 319684 A discloses an imaging device and power feeding method.
  • EP 0 862 260 A2 discloses a charge pump circuit.
  • the CMOS image sensor has a floating diffusion (FD) amplifier including a photodiode (photoelectric conversion element) and an FD for each pixel.
  • FD floating diffusion
  • a column parallel output type in which one row in a pixel array is selected and simultaneously read in a column output direction is the mainstream.
  • Fig. 1 is a diagram illustrating a configuration example of a pixel part and a vertical scanning circuit of a general column parallel output type solid-state imaging device (CMOS image sensor).
  • CMOS image sensor general column parallel output type solid-state imaging device
  • a solid-state imaging device 1 of Fig. 1 a pixel part 2 in which pixels PXL are arranged in a matrix, and a vertical scanning circuit (row scanning circuit) 3 for driving the pixels through a row scanning control line in a shutter row and a reading row are illustrated.
  • Fig. 1 illustrates a pixel array of one row.
  • each of the pixels PXL of the pixel part 2 includes, as active elements, four elements corresponding to a transfer transistor TG-Tr as a transfer element, a reset transistor RST-Tr as a reset element, a source follower transistor SF-Tr as a source follower element (amplifying element), and a selection transistor SEL-Tr as a selection element.
  • the transfer transistor TG-Tr is held in a non-conductive state during a charge storage period of the photodiode PD, and is held in a conductive state by a drive control signal DTG applied to a gate through a control signal line LTG to transfer electric charge photo-electrically converted by the photodiode PD to a floating diffusion FD in a transfer duration in which stored electric charge of the photodiode PD are transferred to the floating diffusion FD.
  • the reset transistor RST-Tr resets a potential of the floating diffusion FD to a potential VDD of a power supply line when a drive control signal (reset signal) DRST is applied to a gate thereof through a control signal line LRST.
  • a gate of the source follower transistor SF-Tr is connected to the floating diffusion FD.
  • the source follower transistor SF-Tr is connected to a vertical signal line LSGN through the select transistor SEL-Tr, and is included in a source follower and a constant current source of a load circuit outside the pixel part.
  • a drive control signal (address signal or select signal) DSEL is applied to a gate of the selection transistor SEL-Tr through the control signal line LSEL to turn on the selection transistor SEL-Tr.
  • the select transistor SEL-Tr When the select transistor SEL-Tr is turned on, the source follower transistor SF-Tr amplifies the potential of the floating diffusion FD and outputs a voltage corresponding to the potential to the vertical signal line LSGN.
  • a voltage output from each of the pixels PXL is output to a column parallel processing part as a pixel signal reading circuit through the vertical signal line LSGN.
  • image data is converted, for example, from an analog signal to a digital signal and transferred to a signal processing part in a subsequent stage, where predetermined image signal processing is performed to obtain a desired image.
  • a vertical scanning circuit 3 includes a row driver 31 that applies a drive control signal DTG (DRST, DSEL) at a level of a positive power-source voltage to a corresponding control signal line LTG (LRST, LSEL) upon reception of a control signal TG (RST, SEL), and a voltage supply part 32 that supplies a voltage different from a positive power-source voltage vaa, for example, a voltage higher than or equal to the positive power-source voltage vaa to a driver.
  • DTG drive control signal
  • LTG LTG
  • the voltage supply part 32 includes an operational amplifier (Op Amp) OPA32, a capacitor bridge circuit CB32 including an internal capacitor Cbst having an internal capacitance of about 100 pF, switches SW (1 to 4), etc., and an external capacitor Cext having a capacitance of about 10 nF.
  • OPA32 operational amplifier
  • CB32 capacitor bridge circuit including an internal capacitor Cbst having an internal capacitance of about 100 pF, switches SW (1 to 4), etc.
  • an external capacitor Cext having a capacitance of about 10 nF.
  • CMOS image sensor as a solid-state imaging device 10
  • an operation of successively scanning and reading photocharge generated and stored by the photodiode for each pixel or for each row is performed.
  • this successive scanning that is, when a rolling shutter is employed as an electronic shutter, it is impossible to set the same start time and end time of exposure for storing the photocharge for all pixels. For this reason, in the case of successive scanning, there is a problem that distortion occurs in a captured image when capturing a moving subject.
  • a global shutter that executes exposure start and exposure end at the same timing for all pixels in a pixel array part is employed as the electronic shutter.
  • CMOS image sensor adopting the global shutter as the electronic shutter for example, a signal holding part that holds a signal read from a photoelectric conversion reading part in a signal holding capacitor is provided in a pixel.
  • electric charges are stored as voltage signals from the photodiode all at once in the signal holding capacitor of the signal holding part, and then successively read to ensure simultaneousness of the entire image (for example, see Non-Patent Literature 1).
  • Non-Patent Literature 1 J. Aoki, et al., "A Rolling-Shutter Distortion-Free 3D Stacked Image Sensor with -160dB Parasitic Light Sensitivity In-Pixel Storage Node” ISSCC 2013 / SESSION 27 / IMAGE SENSORS / 27.3 .).
  • the vertical scanning circuit 3 including the voltage supply part 32 and the row driver 31 of the CMOS image sensor with a rolling shutter operation needs to drive only one row of a pixel array.
  • the operational amplifier OPA32 is used to charge the capacitor Cbst in a chip with a desired reference voltage vref, and generate a power-source voltage corresponding to an overvoltage or undervoltage by pumping up using the power-source voltage vaa. Then, subsequently, electric charge is transferred to the external capacitor Cext a plurality of times.
  • a booster of the vertical scanning circuit 3 of the CMOS image sensor with the global shutter operation needs to drive the entire pixel array of the pixel part 2, and thus the load capacity is significantly large.
  • the load capacity is about 1,000 times the load capacity of the rolling shutter operation.
  • a charge up time needs to be multiplied by 1,000 times.
  • the capacitance of the internal capacitor Cbst needs to be under 1,000x.
  • the operating speed (charge and transfer cycle) needs to be under 1,000x.
  • the operational amplifier OPA32 needs to have a significantly large slew rate. Therefore, at present, it is significantly difficult to design a voltage supply part (booster) of the CMOS image sensor having the global shutter function on a silicon substrate.
  • the invention provides a solid-state imaging device, a method for driving a solid-state imaging device according to the independent claims, capable of achieving low power consumption with a simpler circuit and a smaller area, and capable of realizing high-speed charging. Further advantageous embodiments of the invention are disclosed in the dependent claims.
  • a solid-state imaging device which includes: a pixel part in which a plurality of pixels are disposed in a matrix; and a reading part configured to read pixel signals from the pixel part in units of one or more rows by applying, to a control signal line, a drive control signal at a predetermined level in accordance with a control signal.
  • the reading part includes: a driver configured to apply the drive control signal at a voltage level supplied upon reception of the control signal to the control signal line corresponding to the driver; and a voltage supply part configured to supply a voltage different from a first power-source voltage or a voltage different from a second power-source voltage to the driver.
  • the voltage supply part includes: a first node; a second node; a capacitor including a first electrode and a second electrode, the first electrode being connected with the first node, the second electrode being connected with the second node; a first power-source potential; a second power-source potential; a first switch configured to selectively connect between the first power-source potential and the first node or the second node in accordance with a first signal; a second switch configured to selectively connect between the second power-source potential and the second node or the first node in accordance with a second signal; and at least one of a third switch and a fourth switch, the third switch being configured to selectively connect between the first power-source potential and the second node in accordance with a third signal, the fourth switch being configured to selectively connect between the second power-source potential and the first node in accordance with a fourth signal.
  • the first node is connected with a first power-source voltage terminal of the driver when the voltage supply part includes the third switch.
  • the second node is connected with
  • a method for driving a solid-state imaging device including: a pixel part in which a plurality of pixels are disposed in a matrix; and a reading part configured to read pixel signals from the pixel part in units of one or more rows by applying, to a control signal line, a drive control signal at a predetermined level in accordance with a control signal.
  • the reading part includes: a driver configured to apply the drive control signal at a voltage level supplied upon reception of the control signal to the control signal line corresponding to the driver; and a voltage supply part configured to supply a voltage different from a first power-source voltage or a voltage different from a second power-source voltage to the driver.
  • the voltage supply part includes: a first node; a second node; a capacitor including a first electrode and a second electrode, the first electrode being connected with the first node, the second electrode being connected with the second node; a first power-source potential; a second power-source potential; a first switch configured to selectively connect between the first power-source potential and the first node or the second node in accordance with a first signal; a second switch configured to selectively connect between the second power-source potential and the second node or the first node in accordance with a second signal; and a third switch configured to selectively connect between the first power-source potential and the second node in accordance with a third signal.
  • the first node is connected with a first power-source voltage terminal of the driver.
  • the method includes: in a first duration, setting the potential of the first node to be the first power-source potential and setting the potential of the second node to be the second power-source potential as a reference potential, or setting the potential of the first node to be the second power-source potential as a reference potential and setting the potential of the second node to be the first power-source potential, by turning on the first and second switches through the first and second signals that are active and turning off the third switch through the third signal that is inactive; in a second duration, setting the potential of the first node to be a potential up to a potential higher than the first power-source potential and twice as high as the first power-source potential, or setting the potential of the first node to be a potential up to a potential lower than the first power-source potential by a predetermined potential, by setting the first and second signals to be inactive to turn off the first and second switches and setting the third signal to be active to turn on the third switch; and receiving, by the driver, the control signal while receiving supply of a voltage higher than the first
  • the method for driving a solid-state imaging device includes: a pixel part in which a plurality of pixels are disposed in a matrix; and a reading part configured to read pixel signals from the pixel part in units of one or more rows by applying, to a control signal line, a drive control signal at a predetermined level in accordance with a control signal.
  • the reading part includes: a driver configured to apply the drive control signal at a voltage level supplied upon reception of the control signal to the control signal line corresponding to the driver; and a voltage supply part configured to supply a voltage different from a first power-source voltage or a voltage different from a second power-source voltage to the driver.
  • the voltage supply part includes: a first node; a second node; a capacitor including a first electrode and a second electrode, the first electrode being connected with the first node, the second electrode being connected with the second node; a first power-source potential; a second power-source potential; a first switch configured to selectively connect between the first power-source potential and the first node or the second node in accordance with a first signal; a second switch configured to selectively connect between the second power-source potential and the second node or the first node in accordance with a second signal; and a fourth switch configured to selectively connect between the second power-source potential and the first node in accordance with a fourth signal.
  • the second node is connected with a second power-source voltage terminal of the driver.
  • the method includes: in a first duration, setting the potential of the first node to be the first power-source potential and setting the potential of the second node to be the second power-source potential as a reference potential, or setting the potential of the first node to be the second power-source potential as a reference potential and setting the potential of the second node to be the first power-source potential, by turning on the first and second switches through the first and second signals that are active and turning off the fourth switch through the fourth signal that is inactive; in a second duration, setting the potential of the second node to be a potential lower than the second power-source potential and up to the first power-source potential level on the negative side, or setting the potential of the second node to be a potential higher than the second power-source potential and up to a predetermined potential on the positive side, by setting the first and second signals to be inactive to turn off the first and second switches and setting the fourth signal to be active to turn on the fourth switch; receiving, by the driver, the control signal while receiving supply of a voltage lower than the second power-
  • An electronic apparatus which includes: a solid-state imaging device; and an optical system through which an object image is formed on the solid-state imaging device.
  • the solid-state imaging device includes: a pixel part in which a plurality of pixels are disposed in a matrix; and a reading part configured to read pixel signals from the pixel part in units of one or more rows by applying, to a control signal line, a drive control signal at a predetermined level in accordance with a control signal.
  • the reading part includes: a driver configured to apply the drive control signal at a voltage level supplied upon reception of the control signal to the control signal line corresponding to the driver; and a voltage supply part configured to supply a voltage different from a first power-source voltage or a voltage different from a second power-source voltage to the driver.
  • the voltage supply part includes: a first node; a second node; a capacitor including a first electrode and a second electrode, the first electrode being connected with the first node, the second electrode being connected with the second node; a first power-source potential; a second power-source potential; a first switch configured to selectively connect between the first power-source potential and the first node or the second node in accordance with a first signal; a second switch configured to selectively connect between the second power-source potential and the second node or the first node in accordance with a second signal; and at least one of a third switch and a fourth switch, the third switch being configured to selectively connect between the first power-source potential and the second node in accordance with a third signal, the fourth switch being configured to selectively connect between the second power-source potential and the first node in accordance with a fourth signal.
  • the first node is connected with a first power-source voltage terminal of the driver when the voltage supply part includes the third switch.
  • the second node is connected with
  • Fig. 2 is a block diagram illustrating a configuration example of a solid-state imaging device according to a first embodiment.
  • the solid-state imaging device 10 includes a CMOS image sensor.
  • the solid-state imaging device 10 includes, as main components, a pixel part 20 as an imaging part, a vertical scanning circuit (row scanning circuit) 30, a reading circuit (column reading circuit) 40, a horizontal scanning circuit (column scanning circuit) 50, and a timing control circuit 60.
  • a pixel part 20 as an imaging part
  • a vertical scanning circuit (row scanning circuit) 30, a reading circuit (column reading circuit) 40, a horizontal scanning circuit (column scanning circuit) 50, and a timing control circuit 60 constitute a reading part 70 of a pixel signal.
  • a voltage supply part that supplies a voltage different from a positive power-source voltage, for example, a voltage higher or lower than the positive power-source voltage (or a voltage different from a negative power-source voltage, for example, a voltage lower or higher than the negative power-source voltage) to a row driver in the vertical scanning circuit 30 basically includes a first power-source potential vaa, a second power-source potential vgnd, three switches SW, and an external capacitor Cext31 in a semiconductor substrate (chip), and is configured to be able to achieve low power consumption with a simpler circuit and a smaller area, realize high-speed charging, and be applied to a CMOS image sensor having a rolling shutter function and a global shutter function.
  • the voltage supply part of the present embodiment basically requires only a switch of silicon and one external capacitor, does not require an internal operational amplifier for charging and discharging a capacitor, and does not require an internal capacitor that consumes area and power.
  • a high-speed operation as an external capacitor is charged by an external power supply having significantly small output impedance, and an output voltage of the voltage supply part can be adjusted when a level determination part (voltage detection circuit) is used or when a charging time is controlled.
  • Fig. 3 is a circuit diagram illustrating a configuration example of a pixel of the solid-state imaging device 10 according to the first embodiment.
  • This pixel PXL20 includes, for example, a photodiode (PD) which is a photoelectric conversion element. Further, for this photodiode PD21, one transfer transistor TG21-Tr, one reset transistor RST21-Tr, one source follower transistor SF21-Tr, and one selection transistor SEL21-Tr are included.
  • PD photodiode
  • one transfer transistor TG21-Tr, one reset transistor RST21-Tr, one source follower transistor SF21-Tr, and one selection transistor SEL21-Tr are included.
  • the photodiode PD21 generates and stores signal charges (here, electrons) whose amount corresponds to the amount of incident light.
  • signal charges here, electrons
  • each transistor corresponds to an n-type transistor.
  • the signal charges may correspond to holes and each transistor may correspond to a p-type transistor.
  • the present embodiment is effective in a case in which each transistor is shared among a plurality of photodiodes, or in a case in which a three-transistor (3Tr) pixel not having a selection transistor is employed.
  • the transfer transistor TG21-Tr is connected between the photodiode PD21 and a floating diffusion FD21 and is controlled by a drive control signal DTG21 supplied to a gate through a drive control line LTG21.
  • the transfer transistor TG21-Tr is selected during a period in which the drive control signal DTG21 applied to the drive control line LTG21 is at a high level (H) to become conductive, and transfers the electrons photo-electrically converted by the photodiode PD21 to the floating diffusion FD21.
  • the reset transistor RST21-Tr is connected between a power line VRst and the floating diffusion FD21, and is controlled by a drive control signal DRST21 supplied to a gate through the drive control line LRST21.
  • the reset transistor RST21-Tr may be configured to be connected between a power line VDD and the floating diffusion FD21, and controlled through the drive control line LRST21.
  • the reset transistor RST21-Tr is selected during a period in which the drive control signal DRST21 applied to the drive control line LRST21 is at the H level to become conductive, and resets the floating diffusion FD21 to a potential of the power line VRst (or VDD).
  • the source follower transistor SF21-Tr and the selection transistor SEL21-Tr are connected in series between the power line VDD and the vertical signal line LSGN21.
  • the floating diffusion FD21 is connected to a gate of the source follower transistor SF21-Tr.
  • the selection transistor SEL21-Tr is controlled by a drive control signal DSEL21 supplied to the gate through the drive control line LSEL21.
  • the selection transistor SEL21-Tr is selected during a period in which the drive control signal DSEL21 applied to the drive control line LSEL21 is at H to become conductive.
  • the source follower transistor SF21-Tr outputs a column output analog signal VSL according to the potential of the floating diffusion FD21 to the vertical signal line LSGN21.
  • the respective gates of the transfer transistor TG21-Tr, the reset transistor RST21-Tr, and the selection transistor SEL21-Tr are connected row by row, these operations are simultaneously performed in parallel for each pixel of one row.
  • n drive control lines LTG21, n drive control lines LRST21, n drive control lines LSEL21, and m vertical signal lines LSGN21 are present.
  • each of the drive control lines LTG21, LRST21, and LSEL21 is indicated as one row scanning drive control line.
  • the vertical scanning circuit 30 drives the pixels through the row scanning drive control line in the shutter row and the reading row in accordance with control of the timing control circuit 60. In addition, according to an address signal, the vertical scanning circuit 30 outputs row selection signals of row addresses of a read row for reading a signal and a shutter row for resetting the electric charges stored in the photodiode PD21. Specific configurations and functions of the row driver and the voltage supply part of the vertical scanning circuit 30 will be described later.
  • the reading circuit 40 includes a plurality of column signal processing circuits (not illustrated) arranged corresponding to respective column outputs of the pixel part 20, and is configured such that column parallel processing can be performed by the plurality of column signal processing circuits.
  • the reading circuit 40 can include a correlated double sampling (CDS) circuit, an analog digital (AD) converter (ADC), an amplifier (AMP), a sample/hold (S/H) circuit, etc.
  • CDS correlated double sampling
  • AD analog digital
  • AMP amplifier
  • S/H sample/hold
  • the reading circuit 40 may include an ADC 41 that converts each column output analog signal VSL of the pixel part 20 into a digital signal.
  • an amplifier (AMP) 42 for amplifying each column output analog signal VSL of the pixel part 20 may be disposed in the reading circuit 40.
  • AMP amplifier
  • a sample/hold (S/H) circuit 43 that samples and holds each column output analog signal VSL of the pixel part 20 may be disposed in the reading circuit 40.
  • a static random access memory (SRAM) as a column memory that stores a signal obtained by performing predetermined processing on a pixel signal output from each column of the pixel part 20 may be disposed.
  • the horizontal scanning circuit 50 scans signals processed by the plurality of column signal processing circuits such as the ADC of the reading circuit 40, etc., transfers the signals in a horizontal direction, and outputs the signals to the reading part 70.
  • the timing control circuit 60 generates timing signals necessary for signal processing of the pixel part 20, the vertical scanning circuit 30, the reading circuit 40, the horizontal scanning circuit 50, etc.
  • the reading part 70 controls the vertical scanning circuit 30, etc. in a rolling shutter mode or a global shutter mode to apply the drive control signal DTG21 (DRST21, DSEL21) at a predetermined level in accordance with a control signal TG21 (RST21, SEL21) to a predetermined drive control line LTG21 (LRST21, LSEL21), thereby reading pixel signals from the pixel part 20 in units of one or more rows (all rows in the global shutter mode).
  • Fig. 5 is a circuit diagram illustrating a specific configuration example of the driver and the voltage supply part of the vertical scanning circuit 30 in the solid-state imaging device 10 according to the first embodiment.
  • the vertical scanning circuit 30 includes a plurality of row drivers 310 and a voltage supply part 320.
  • Each of the row drivers 310 applies a voltage different from the first power-source voltage (positive power-source voltage) vaa supplied from the voltage supply part 320, for example, a voltage higher than the positive power-source voltage vaa, for example, the drive control signal DTG21 (DRST21, DSEL21) at a level of (vaa + vref) to the corresponding drive control line LTG21 (LRST21, LSEL21) upon reception of the control signal TG21 (RST21, SEL21).
  • a voltage different from the first power-source voltage (positive power-source voltage) vaa supplied from the voltage supply part 320 for example, a voltage higher than the positive power-source voltage vaa, for example, the drive control signal DTG21 (DRST21, DSEL21) at a level of (vaa + vref) to the corresponding drive control line LTG21 (LRST21, LSEL21) upon reception of the control signal TG21 (RST21, SEL21).
  • two inverters 311 and 312 are connected in series to an input line of the control signal TG21 (RST21, SEL21), and a first power-source voltage terminal TVAA is connected to a voltage supply line of the voltage supply part 320 (first node ND31).
  • the two inverters 311 and 312 are configured by CMOS inverters (in Fig. 5 , a latter stage side is illustrated by a specific circuit).
  • CMOS inverter 312 a p-channel MOS (PMOS) transistor PT31 and an n-channel MOS (NMOS) transistor NT31 are connected in series between the first power-source voltage terminal TVAA and a reference potential VSS (for example, a ground potential GND). Specifically, a source of the PMOS transistor PT31 is connected to the first power-source voltage terminal TVAA, and a source of the NMOS transistor NT31 is connected to the reference potential VSS. Further, a drain of the PMOS transistor PT31 and a drain of the NMOS transistor NT31 are connected to form an output node NDOT, and the output node NDOT is connected to the corresponding drive control line LTG21 (LRST21, LSEL21). An input node is formed by a gate of the PMOS transistor PT31 and a gate of the NMOS transistor NT31, and is connected to an output terminal of the inverter 311 in a former stage element.
  • PMOS p-channel MOS
  • the voltage supply part 320 generates a voltage higher than the first power-source voltage (positive power-source voltage) vaa, for example, (vaa + vref), and supplies the voltage to the row driver 310.
  • the voltage supply part 320 includes the first node ND31, a second node ND32, and the external capacitor Cext31 in which a first electrode EL31 is connected to the first node ND31 via a first connection terminal T31 and a second electrode EL32 is connected to the second node ND32 via a second connection terminal T32.
  • the voltage supply part 320 includes a first power-source potential line Lvaa of the first power-source potential (positive power-source potential) vaa, a second power-source potential line Lvgnd of the second power-source potential (negative power-source potential) vgnd, a first switch SW31, a second switch SW32, a third switch SW33, a fifth switch SW35, and a level determination part 321.
  • the first switch SW31 is formed of, for example, an NMOS transistor, and selectively connects between the first power-source potential line Lvaa and the first node ND31 in accordance with a first signal S31.
  • the second switch SW32 is formed of, for example, an NMOS transistor, and selectively connects between the second power-source potential line Lvgnd and the second node ND32 in accordance with a second signal S32.
  • the third switch SW33 is formed of, for example, an NMOS transistor, and selectively connects between the first power-source potential line Lvaa and the second node ND32 in accordance with a third signal S33.
  • the first node ND31 is connected to the first power-source voltage terminal TVAA of the row driver 310.
  • the fifth switch SW35 is formed of, for example, an NMOS transistor, and selectively connects between the first node ND31 and the second node ND32 in accordance with a fifth signal S35.
  • the level determination part 321 In the case of determining that a potential level VND31 of the first node ND31 is lower than a reference voltage vref set arbitrarily, the level determination part 321 outputs the first signal S31 that is active, for example, at the high (H) level to the first switch SW31 to turn on the first switch SW31. In the case of determining that the potential level VND31 of the first node ND31 has reached the reference voltage vref, the level determination part 321 outputs the first signal S31 that is inactive, in this example, at the low level to the first switch SW31 to turn off the first switch SW31.
  • the level determination part 321 of the first embodiment includes a comparator CMP31 whose non-inverted input (+) is connected to a supply line of the reference voltage vref and whose inverted input terminal (-) is connected to the first node ND31.
  • the comparator CMP31 compares the potential level VND31 of the first node ND31 with the reference voltage vref, and outputs the first signal S31 at the active H level to the first switch SW31 to turn on the first switch SW31 when the potential level VND31 of the first node ND31 is lower than the reference voltage vref. In a case in which the potential level VND31 of the first node ND31 has reached the reference voltage vref, the comparator CMP31 outputs the first signal S31 at the inactive L level to the first switch SW31 to turn off the first switch SW31.
  • the comparator CMP31 as the level determination part 321 when an enable signal CMP_ENA is at the active H level, the comparator CMP31 as the level determination part 321 is in an operational state and performs level determination processing.
  • a booster 322 includes the first node ND31, the second node ND32, the first power-source potential line Lvaa of the first power-source potential (positive power-source potential) vaa, the second power-source potential line Lvgnd of the second power-source potential (negative power-source potential) vgnd, the first switch SW31, the second switch SW32, the third switch SW33, the fifth switch SW35, and the comparator CMP31 as the level determination part 321 except for the external capacitor Cext31.
  • the voltage supply part 320 in the first embodiment At the time of generating a voltage (vaa + vref) higher than the positive power-source voltage supplied to the row driver 310, the voltage supply part 320 in the first embodiment generates the voltage (vaa + vref) higher than the positive power-source voltage vaa at a desired level and supplies the generated voltage to the row driver 310 through the reset duration PRST, the first duration PFST, and the second duration PSCD.
  • the potential level VND31 (vaa + vref) of the first node ND31 can be adjusted.
  • the characteristic configurations and functions of the row driver 310 and the voltage supply part 320 of the vertical scanning circuit 30 of the solid-state imaging device 10 have been described above. Next, a description will be given of a voltage generation operation, etc. of the voltage supply part 320 and the row driver 310 in the vertical scanning circuit 30 of the solid-state imaging device 10 according to the first embodiment.
  • a case in which the transfer transistor TG21-Tr of the pixel PXL20 is driven to read the pixel will be described as an example.
  • Fig. 6A to Fig. 6J are timing charts of the voltage generation operation, etc. of the voltage supply part 320 and the row driver 310 in the vertical scanning circuit 30 of the solid-state imaging device 10 according to the first embodiment.
  • Fig. 6A illustrates a control signal TG of the transfer transistor TG21-Tr of the pixel PXL20.
  • Fig. 6B illustrates the second signal S32 for turning on and off the second switch SW32 of the voltage supply part 320.
  • Fig. 6C illustrates the fifth signal S35 for turning on and off the fifth switch SW35 of the voltage supply part 320.
  • Fig. 6D illustrates the enable signal CMP_ENA for the comparator CMP31 of the voltage supply part 320.
  • Fig. 6E illustrates the first signal S31 for turning on and off the first switch SW31 of the voltage supply part 320.
  • Fig. 6F illustrates the third signal S33 for turning on and off the third switch SW33 of the voltage supply part 320.
  • Fig. 6A illustrates a control signal TG of the transfer transistor TG21-Tr of the pixel PXL20.
  • Fig. 6B illustrates the second signal S32 for turning on and off the second switch SW32 of the voltage supply
  • FIG. 6G illustrates level transition of the first node ND31 of the voltage supply part 320.
  • Fig. 6H illustrates level transition of the second node ND32 of the voltage supply part 320.
  • Fig. 6I illustrates level transition of the first node ND31 of the voltage supply part 320.
  • Fig. 6J illustrates a drive control signal DTG applied from the row driver 310 of the voltage supply part 320 to the drive control line LTG21.
  • the reset duration PRST is set before the first duration PFST for generating a voltage.
  • the enable signal CMP_ENA is set to the inactive L level and the comparator CMP31 is held in the non-operational state. Since the comparator CMP31 is in the non-operational state, the first signal S31 corresponding to an output thereof is held at the inactive L level, and the first switch SW31 is held in the off state accordingly.
  • the third signal S33 is set to the inactive L level, and the third switch SW33 is held in the off state.
  • the second signal S32 in a state in which the first switch SW31 and the third switch SW33 are turned off, the second signal S32 is set to the active H level, the second switch SW32 is held in the on state, and the second node ND32 is connected to the power-source potential line Lvgnd.
  • the fifth signal S35 is set to the active H level, the fifth switch SW35 is held in the on state, and the first node ND31 and the second node ND32 are connected. In this way, the first node ND31 and the second node ND32 are set to the second power-source potential vgnd and reset (discharged).
  • the reset duration PRST when the first node ND31 and the second node ND32 are reset to the second power-source potential vgnd, the fifth signal S35 is set to the inactive L level, the fifth switch SW35 is switched to the off state, and the first node ND31 and the second node ND32 are disconnected.
  • the second signal S32 is held at the active H level until immediately before the end of the subsequent first duration PFST. Accordingly, the second switch SW32 is held in the on state immediately before the start of the second duration PSCD, and is held in a state where the second node ND32 is connected to the second power-source potential line Lvgnd. Therefore, the second node ND32 is held at the second power-source potential vgnd until immediately before the second duration PSCD is started.
  • processing in the first duration PFST is subsequently performed.
  • the enable signal CMP_ENA is switched to the active H level
  • the comparator CMP31 is switched to the operational state.
  • comparison processing of the potential level VND31 of the first node ND31 and the reference voltage vref is started.
  • the first signal S31 at the active H level is output to the first switch SW31 to turn on the first switch SW31.
  • the first switch SW31 As the first switch SW31 is switched to the on state, the first node ND31 is connected to the first power-source potential line Lvaa, the first node ND31 is charged, and the potential level VND31 thereof rises from the second power-source potential vgnd to the reference voltage vref.
  • the comparator CMP31 detects that the potential level VND31 of the first node ND31 has reached the reference voltage vref, the first signal S31 is switched to the inactive L level and output to the first switch SW31, and the first switch SW31 is turned off. In this way, the first node ND31 is disconnected from the first power-source potential line Lvaa.
  • the enable signal CMP_ENA is set to the inactive L level, and the comparator CMP31 is switched to the non-operational state.
  • the second signal S32 is switched to the L level, the second switch SW32 is switched to the off state, and the second node ND32 is disconnected from the second power-source potential line Lvgnd.
  • processing in the second duration PSCD is subsequently performed.
  • the third signal S33 is switched to the active H level.
  • the third switch SW33 is turned on, the second node ND32 is connected to the first power-source potential line Lvaa, and the first node ND31 is boosted to a potential (vaa + vref) by capacitive coupling of the external capacitor Cext31.
  • the boosted voltage (vaa + vref) is supplied from the first node ND31 to the first power-source voltage terminal TVAA of the row driver 310 as a voltage to be supplied higher than the positive power-source voltage (first power-source voltage).
  • the drive control signal DTG21 upon reception of the control signal TG21, the drive control signal DTG21 at a level of the voltage (vaa + vref) higher than the first power-source voltage (positive power-source voltage) vaa supplied from the voltage supply part 320 is applied to the corresponding drive control line LTG21.
  • Electric charges of the external capacitor Cext31 are divided by the capacitor Cext31 and the load capacity of the pixel array of the pixel part 20, and a voltage of the drive control signal DTG21 (vout1p) becomes slightly lower than the boosted voltage (vaa + vref).
  • the vertical scanning circuit 30 includes the voltage supply part 320 that generates the voltage different from the first power-source voltage (positive power-source voltage) vaa, for example, the voltage higher than the positive power-source voltage vaa (for example, vaa + vref) and supplies the generated voltage to the row driver 310.
  • the voltage supply part 320 includes the external capacitor Cext31 in which the first node ND31, the second node ND32, and the first electrode EL31 are connected to the first node ND31 via the first connection terminal T31, and the second electrode EL32 is connected to the second node ND32 via the second connection terminal T32.
  • the voltage supply part 320 includes the first power-source potential line Lvaa of the first power-source potential (positive power-source potential) vaa, the second power-source potential line Lvgnd of the second power-source potential (negative power-source potential) vgnd, the first switch SW31, the second switch SW32, the third switch SW33, the fifth switch SW35, and the comparator CMP31 as the level determination part 321.
  • the comparator CMP31 compares the potential level VND31 of the first node ND31 with the reference voltage vref, outputs the first signal S31 at the active H level to the first switch SW31 to turn on the first switch SW31 when the potential level VND31 of the first node ND31 is lower than the reference voltage vref, and outputs the first signal S31 at the inactive L level to the first switch SW31 to turn off the first switch SW31 when the potential level VND31 of the first node ND31 reaches the reference voltage vref.
  • the voltage supply part 320 that supplies a voltage higher or lower than the positive power-source voltage (or a voltage lower than the negative power-source voltage) to the row driver in the vertical scanning circuit 30 of the first embodiment basically includes the first power-source potential vaa, the second power-source potential vgnd, the three switches SW31, SW32, and SW33, and the external capacitor Cext31 in the semiconductor substrate (chip), can achieve low power consumption with a simpler circuit and a smaller area, can realize high-speed charging, and can be applied to the CMOS image sensor having the rolling shutter function and the global shutter function.
  • the voltage supply part of the first embodiment basically requires only a switch of silicon and one external capacitor, does not require an internal operational amplifier for charging and discharging a capacitor, and does not require an internal capacitor that consumes area and power.
  • a high-speed operation as an external capacitor is charged by an external power supply having significantly small output impedance, and an output voltage of the voltage supply part can be adjusted when the comparator CMP31 corresponding to the level determination part (voltage detection circuit) is used or when a charging time is controlled.
  • Fig. 7 is a diagram illustrating a configuration example of a pixel part and a vertical scanning circuit of a solid-state imaging device according to a second embodiment.
  • Fig. 8A to Fig. 8J are timing charts of a voltage generation operation, etc. of a voltage supply part 320A and a row driver 310A in the vertical scanning circuit 30A of the solid-state imaging device 10A according to the second embodiment.
  • a level determination part 321A includes a counter CNT31 instead of the comparator.
  • the counter CNT31 Upon reception of an enable signal COUN_TENA at the active H level, the counter CNT31 counts a clock CLK0 in an operational state (enabled state), and outputs the first signal S31 at the active H level to the switch SW31 to turn off the switch SW31 when a count value is a target value, which is a value ( ⁇ vx) corresponding to a case in which the potential level VND31 of the first node ND31 is lower than the reference voltage vref (does not reach the reference voltage) in this example.
  • a target value which is a value ( ⁇ vx) corresponding to a case in which the potential level VND31 of the first node ND31 is lower than the reference voltage vref (does not reach the reference voltage) in this example.
  • the counter CNT31 Upon reaching a value (vx) corresponding to a case in which the potential level VND31 of the first node ND31 reaches the reference voltage vref, the counter CNT31 outputs the first signal S31 at the inactive L level to the switch SW31 to turn off the switch SW31.
  • the third signal S33 is switched to the active H level.
  • the third switch SW33 is turned on, the second node ND32 is connected to the first power-source potential line Lvaa, and the first node ND31 is boosted to a potential (vaa + vx (for example, vref)) by capacitive coupling of the external capacitor Cext31.
  • the boosted voltage (vaa + vx (vref)) is supplied from the first node ND31 to a first power-source voltage terminal TVAA of the row driver 310A as a voltage to be supplied higher than the positive power-source voltage (first power-source voltage).
  • the drive control signal DTG21 upon reception of the control signal TG21, the drive control signal DTG21 at a level of the voltage (vaa + vx) higher than the first power-source voltage (positive power-source voltage) vaa supplied from the voltage supply part 320 is applied to the corresponding drive control line LTG21.
  • the potential level VND31 (vaa + vx) of the first node ND31 can be adjusted.
  • Fig. 9 is a diagram illustrating a configuration example of a pixel part and a vertical scanning circuit of a solid-state imaging device according to a third embodiment.
  • Fig. 10A to Fig. 10G are timing charts of a voltage generation operation, etc. of a voltage supply part 320B and a row driver 310B in the vertical scanning circuit 30B of the solid-state imaging device 10B according to the third embodiment.
  • a difference between the solid-state imaging device 10B according to the third embodiment and the solid-state imaging devices 10 and 10A according to the first and second embodiments described above is as follows.
  • the level determination parts 321 and 321A and the fifth switch SW35 are not provided, and the voltage supplied to the row driver 310B is boosted up to 2vaa, which is twice the first power-source voltage vaa.
  • processing in the reset duration is not performed, and a boosting operation is performed in processing in the first duration PFST and the second duration PSCD.
  • the first signal S31 and the second signal S32 are shared by the first switch SW31 and the second switch SW32, and the shared signal and the third signal S33 for the third switch SW33 are in reverse phase.
  • the first node ND31 is connected to the first power-source potential line Lvaa and is at a positive power-source voltage vaa level
  • the second node ND32 is connected to the second power-source potential line Lvgnd and is at a negative power-source voltage vgnd level.
  • the first signal S31 is switched to the inactive L level
  • the third signal S33 is switched to the active H level.
  • the second node ND32 is at the positive power-source voltage vaa level
  • the first node ND31 is boosted up to a voltage (2vaa) level, which is twice the power-source voltage vaa.
  • the boosted voltage (2 vaa) is supplied from the first node ND31 to the first power-source voltage terminal TVAA of the row driver 310B as a voltage to be supplied higher than the positive power-source voltage (first power-source voltage).
  • the drive control signal DTG21 upon reception of the control signal TG21, the drive control signal DTG21 at a level of a voltage (2vaa) higher than the first power-source voltage (positive power-source voltage) vaa supplied from the voltage supply part 320B is applied to the corresponding drive control line LTG21.
  • the voltage supply part 320B basically includes the first power-source potential Vaa, the second power-source potential Vgnd, the three switches SW31, SW32, and SW33, and the external capacitor Cext31 in the semiconductor substrate (chip), can achieve low power consumption with a simpler circuit and a smaller area, can realize high-speed charging, and can be applied to the CMOS image sensor having the rolling shutter function and the global shutter function.
  • Fig. 11 is a diagram illustrating a configuration example of a pixel part and a vertical scanning circuit of a solid-state imaging device according to a fourth embodiment.
  • Fig. 12A to Fig. 12J are timing charts of a voltage generation operation, etc. of a voltage supply part 320C and a row driver 310C in the vertical scanning circuit 30C of the solid-state imaging device 10C according to the fourth embodiment.
  • a difference between the solid-state imaging device 10C according to the fourth embodiment and the solid-state imaging device 10 according to the first embodiment described above is as follows.
  • the voltage supply part 320C of the solid-state imaging device 10C according to the fourth embodiment is configured to generate a voltage lower than the positive power-source voltage vaa instead of generating a voltage higher than the positive power-source voltage vaa and supply the generated voltage to the first power-source voltage terminal TVAA of the row driver 310C.
  • the solid-state imaging device 10C according to the fourth embodiment is different from the solid-state imaging device 10 according to the first embodiment in the configuration of the voltage supply part 320C.
  • the voltage supply part 320C generates a voltage lower than the first power-source voltage (positive power-source voltage) vaa, for example, (vaa - vref), and supplies the generated voltage to the row driver 310C.
  • the voltage supply part 320C includes the external capacitor Cext31 in which the first node ND31, the second node ND32, and the first electrode EL31 are connected to the first node ND31 via the first connection terminal T31, and the second electrode EL32 is connected to the second node ND32 via the second connection terminal T32.
  • the voltage supply part 320C includes a first power-source potential line Lvaa of the first power-source potential (positive power-source potential) vaa, a second power-source potential line Lvgnd of the second power-source potential (negative power-source potential) vgnd, a first switch SW31, a second switch SW32, a third switch SW33, a fifth switch SW35, and a level determination part 321C.
  • the first switch SW31 selectively connects between the first power-source potential line Lvaa and the second node ND32 in accordance with a first signal S31.
  • the second switch SW32 selectively connects between the second power-source potential line Lvgnd and the first node ND31 in accordance with a second signal S32.
  • the third switch SW33 selectively connects between the first power-source potential line Lvaa and the second node ND32 in accordance with a third signal S33.
  • the first node ND31 is connected to the first power-source voltage terminal TVAA of the row driver 310.
  • the fifth switch SW35 is formed of, for example, an NMOS transistor, and selectively connects between the first node ND31 and the second node ND32 in accordance with a fifth signal S35.
  • the level determination part 321C In the case of determining that a potential level VND32 of the second node ND32 is lower than a reference voltage vref set arbitrarily, the level determination part 321C outputs the first signal S31 that is active, for example, at the high (H) level to the first switch SW31 to turn on the first switch SW31. In the case of determining that the potential level VND32 of the second node ND32 has reached the reference voltage vref, the level determination part 321C outputs the first signal S31 that is inactive, in this example, at the low level to the first switch SW31 to turn off the first switch SW31.
  • the level determination part 321C of the fourth embodiment includes a comparator CMP31C whose non-inverted input (+) is connected to a supply line of the reference voltage vref and whose inverted input terminal (-) is connected to the second node ND32.
  • the comparator CMP31C compares the potential level VND32 of the second node ND32 with the reference voltage vref, and outputs the first signal S31 at the active H level to the first switch SW31 to turn on the first switch SW31 when the potential level VND32 of the second node ND32 is lower than the reference voltage vref. In a case in which the potential level VND32 of the second node ND32 has reached the reference voltage vref, the comparator CMP31C outputs the first signal S31 at the inactive L level to the first switch SW31 to turn off the first switch SW31.
  • the comparator CMP31C as the level determination part 321C is in an operational state and performs level determination processing.
  • a booster 322C includes the first node ND31, the second node ND32, the first power-source potential line Lvaa of the first power-source potential (positive power-source potential) vaa, the second power-source potential line Lvgnd of the second power-source potential (negative power-source potential) vgnd, the first switch SW31, the second switch SW32, the third switch SW33, the fifth switch SW35, and the comparator CMP31C as the level determination part 321C except for the external capacitor Cext31.
  • the voltage supply part 320C in the fourth embodiment At the time of generating a voltage (vaa - vref) higher than the positive power-source voltage supplied to the row driver 310C, the voltage supply part 320C in the fourth embodiment generates the voltage (vaa - vref) lower than the positive power-source voltage vaa at a desired level and supplies the generated voltage to the row driver 310C through the reset duration PRST, the first duration PFST, and the second duration PSCD.
  • the potential level VND32 (vaa - vref) of the second node ND32 can be adjusted.
  • Fig. 12A to Fig. 12J are timing charts of the voltage generation operation, etc. of the voltage supply part 320C and the row driver 310C in the vertical scanning circuit 30C of the solid-state imaging device 10C according to the fourth embodiment.
  • Fig. 12A illustrates the control signal TG of the transfer transistor TG21 - Tr of the pixel PXL20.
  • Fig. 12B illustrates the second signal S32 for turning on and off the second switch SW32 of the voltage supply part 320C.
  • Fig. 12C illustrates the fifth signal S35 for turning on and off the fifth switch SW35 of the voltage supply part 320C.
  • Fig. 12D illustrates the enable signal CMP_ENA for the comparator CMP31C of the voltage supply part 320C.
  • Fig. 12E illustrates the first signal S31 for turning on and off the first switch SW31 of the voltage supply part 320C.
  • Fig. 12F illustrates the third signal S33 for turning on and off the third switch SW33 of the voltage supply part 320C.
  • Fig. 12A illustrates the control signal TG of the transfer transistor TG21 - Tr of the pixel PXL20.
  • Fig. 12B illustrates the second signal S32 for turning on and off the second switch SW32
  • FIG. 12G illustrates level transition of the second node ND32 of the voltage supply part 320C.
  • Fig. 12H illustrates level transition of the first node ND31 of the voltage supply part 320.
  • Fig. 121 illustrates level transition of the first node ND31 of the voltage supply part 320C.
  • Fig. 12J illustrates the drive control signal DTG applied from the row driver 310C of the voltage supply part 320C to the drive control line LTG21.
  • the reset duration PRST is set before the first duration PFST for generating a voltage.
  • the enable signal CMP_ENA is set to the inactive L level and the comparator CMP31C is held in the non-operational state. Since the comparator CMP31C is in the non-operational state, the first signal S31 corresponding to an output thereof is held at the inactive L level, and the first switch SW31 is held in the off state accordingly.
  • the third signal S33 is set to the inactive L level, and the third switch SW33 is held in the off state.
  • the second signal S32 in a state in which the first switch SW31 and the third switch SW33 are turned off, the second signal S32 is set to the active H level, the second switch SW32 is held in the on state, and the first node ND31 is connected to the power-source potential line Lvgnd.
  • the fifth signal S35 is set to the active H level, the fifth switch SW35 is held in the on state, and the first node ND31 and the second node ND32 are connected. In this way, the first node ND31 and the second node ND32 are set to the second power-source potential vgnd and reset (discharged).
  • the reset duration PRST when the first node ND31 and the second node ND32 are reset to the second power-source potential vgnd, the fifth signal S35 is set to the inactive L level, the fifth switch SW35 is switched to the off state, and the first node ND31 and the second node ND32 are disconnected.
  • the second signal S32 is held at the active H level until immediately before the end of the subsequent first duration PFST. Accordingly, the second switch SW32 is held in the on state immediately before the start of the second duration PSCD, and is held in a state where the first node ND31 is connected to the second power-source potential line Lvgnd. Therefore, the first node ND31 is held at the second power-source potential vgnd until immediately before the second duration PSCD is started.
  • processing in the first duration PFST is subsequently performed.
  • the enable signal CMP_ENA is switched to the active H level
  • the comparator CMP31C is switched to the operational state.
  • comparison processing of the potential level VND32 of the second node ND32 and the reference voltage vref is started.
  • the first signal S31 at the active H level is output to the first switch SW31 to turn on the first switch SW31.
  • the second node ND32 As the first switch SW31 is switched to the on state, the second node ND32 is connected to the first power-source potential line Lvaa, the second node ND32 is charged, and the potential level VND32 thereof rises from the second power-source potential vgnd to the reference voltage vref.
  • the comparator CMP31C detects that the potential level VND32 of the second node ND32 has reached the reference voltage vref, the first signal S31 is switched to the inactive L level and output to the first switch SW31, and the first switch SW31 is turned off. In this way, the second node ND32 is disconnected from the first power-source potential line Lvaa.
  • the enable signal CMP_ENA is set to the inactive L level, and the comparator CMP31C is switched to the non-operational state.
  • the second signal S32 is switched to the L level, the second switch SW32 is switched to the off state, and the first node ND31 is disconnected from the second power-source potential line Lvgnd.
  • processing in the second duration PSCD is subsequently performed.
  • the third signal S33 is switched to the active H level.
  • the third switch SW33 is turned on, the second node ND32 is connected to the first power-source potential line Lvaa, and the first node ND31 is stepped downed to a potential (vaa - vref) by capacitive coupling of the external capacitor Cext31.
  • the step-down voltage (vaa - vref) is supplied from the first node ND31 to the first power-source voltage terminal TVAA of the row driver 310C as a voltage to be supplied lower than the positive power-source voltage (first power-source voltage).
  • the drive control signal DTG21 upon reception of the control signal TG21, the drive control signal DTG21 at a level of the voltage (vaa - vref) lower than the first power-source voltage (positive power-source voltage) vaa supplied from the voltage supply part 320 is applied to the corresponding drive control line LTG21.
  • Electric charges of the external capacitor Cext31 are divided by the capacitor Cext31 and the load capacity of the pixel array of the pixel part 20, and a voltage of the drive control signal DTG21 (vout1p) becomes slightly lower than the step-down voltage (vaa - vref).
  • the vertical scanning circuit 30 includes the voltage supply part 320C that generates the voltage different from the first power-source voltage (positive power-source voltage) vaa, for example, the voltage lower than the positive power-source voltage vaa (for example, vaa - vref) and supplies the generated voltage to the row driver 310C.
  • the voltage supply part 320C includes the external capacitor Cext31 in which the first node ND31, the second node ND32, and the first electrode EL31 are connected to the first node ND31 via the first connection terminal T31, and the second electrode EL32 is connected to the second node ND32 via the second connection terminal T32.
  • the voltage supply part 320C includes the first power-source potential line Lvaa of the first power-source potential (positive power-source potential) vaa, the second power-source potential line Lvgnd of the second power-source potential (negative power-source potential) vgnd, the first switch SW31, the second switch SW32, the third switch SW33, the fifth switch SW35, and the comparator CMP31 as the level determination part 321.
  • the comparator CMP31C compares the potential level VND32 of the second node ND32 with the reference voltage vref, outputs the first signal S31 at the active H level to the first switch SW31 to turn on the first switch SW31 when the potential level VND32 of the second node ND32 is lower than the reference voltage vref, and outputs the first signal S31 at the inactive L level to the first switch SW31 to turn off the first switch SW31 when the potential level VND32 of the second node ND32 reaches the reference voltage vref.
  • the voltage supply part 320C that supplies a voltage lower than the positive power-source voltage to the row driver in the vertical scanning circuit 30C of the fourth embodiment basically includes the first power-source potential vaa, the second power-source potential vgnd, the three switches SW31, SW32, and SW33, and the external capacitor Cext31 in the semiconductor substrate (chip), can achieve low power consumption with a simpler circuit and a smaller area, can realize high-speed charging, and can be applied to the CMOS image sensor having the rolling shutter function and the global shutter function.
  • the voltage supply part of the fourth embodiment basically requires only a switch of silicon and one external capacitor, does not require an internal operational amplifier for charging and discharging a capacitor, and does not require an internal capacitor that consumes area and power.
  • a high-speed operation as an external capacitor is charged by an external power supply having significantly small output impedance, and an output voltage of the voltage supply part can be adjusted when the comparator CMP31C corresponding to the level determination part (voltage detection circuit) is used or when a charging time is controlled.
  • Fig. 13 is a diagram illustrating a configuration example of a pixel part and a vertical scanning circuit of a solid-state imaging device according to a fifth embodiment.
  • Fig. 14A to Fig. 14K are timing charts of a voltage generation operation, etc. of a voltage supply part 320D and a row driver 310D in the vertical scanning circuit 30D of the solid-state imaging device 10D according to the fifth embodiment.
  • a difference between the solid-state imaging device 10D according to the fifth embodiment and the solid-state imaging device 10 according to the first embodiment described above is as follows.
  • a switch SW36D is connected between the first node ND31 and the first power-source voltage terminal TVAA of the row driver 310D, and a capacitor C32D is connected between the first power-source voltage terminal TVAA and the first power-source potential line Lvaa of the positive power-source potential vaa.
  • the switch SW36D is on/off controlled by the third signal S33, and selectively connects between the first node ND31 and the first power-source voltage terminal TVAA in accordance with the third signal S33.
  • the third switch SW33 is turned on, the second node ND32 is connected to the first power-source potential line Lvaa, and the first node ND31 is boosted up to a potential (vaa + vref) by capacitive coupling of the external capacitor Cext31.
  • the switch SW36D is turned on. While the switch SW36D is turned on, the boosted voltage (vaa + vref) is supplied from the first node ND31 to the first power-source voltage terminal TVAA of the row driver 310D as a voltage to be supplied higher than the positive power-source voltage (first power-source voltage).
  • the voltage level of the first power-source voltage terminal TVAA is held at a stable level by the capacitor C32D.
  • Fig. 15 is a diagram illustrating a configuration example of a pixel part and a vertical scanning circuit of a solid-state imaging device according to a sixth embodiment.
  • Fig. 16A to Fig. 16L are timing charts of a voltage generation operation, etc. of a voltage supply part 320E and a row driver 310E in the vertical scanning circuit 30E of the solid-state imaging device 10E according to the sixth embodiment.
  • a difference between the solid-state imaging device 10E according to the sixth embodiment and the solid-state imaging device 10A according to the second embodiment described above is as follows.
  • a switch SW36E is connected between the first node ND31 and the first power-source voltage terminal TVAA of the row driver 310E, and a capacitor C32E is connected between the first power-source voltage terminal TVAA and the first power-source potential line Lvaa of the positive power-source potential vaa.
  • the switch SW36E is on/off controlled by the third signal S33, and selectively connects between the first node ND31 and the first power-source voltage terminal TVAA in accordance with the third signal S33.
  • the third switch SW33 is turned on, the second node ND32 is connected to the first power-source potential line Lvaa, and the first node ND31 is boosted up to a potential (vaa + vx (for example, vref)) by capacitive coupling of the external capacitor Cext31.
  • the switch SW36E is turned on. While the switch SW36E is turned on, the boosted voltage (vaa + vx (vref)) is supplied from the first node ND31 to the first power-source voltage terminal TVAA of the row driver 310E as a voltage to be supplied higher than the positive power-source voltage (first power-source voltage).
  • the voltage level of the first power-source voltage terminal TVAA is held at a stable level by the capacitor C32E.
  • Fig. 17 is a diagram illustrating a configuration example of a pixel part and a vertical scanning circuit of a solid-state imaging device according to a seventh embodiment.
  • Fig. 18A to Fig. 18H are timing charts of a voltage generation operation, etc. of a voltage supply part 320F and a row driver 310F in the vertical scanning circuit 30F of the solid-state imaging device 10F according to the seventh embodiment.
  • a difference between the solid-state imaging device 10F according to the seventh embodiment and the solid-state imaging device 10B according to the third embodiment described above is as follows.
  • a switch SW36F is connected between the first node ND31 and the first power-source voltage terminal TVAA of the row driver 310F, and a capacitor C32F is connected between the first power-source voltage terminal TVAA and the first power-source potential line Lvaa of the positive power-source potential vaa.
  • the switch SW36F is on/off controlled by the third signal S33, and selectively connects between the first node ND31 and the first power-source voltage terminal TVAA in accordance with the third signal S33.
  • the third switch SW33 is turned on, the second node ND32 is connected to the first power-source potential line Lvaa, and the first node ND31 is boosted up to a potential (2vaa) by capacitive coupling of the external capacitor Cext31.
  • the switch SW36F is turned on. While the switch SW36F is turned on, the boosted voltage (2vaa) is supplied from the first node ND31 to the first power-source voltage terminal TVAA of the row driver 310F as a voltage to be supplied higher than the positive power-source voltage (first power-source voltage). In addition, the voltage level of the first power-source voltage terminal TVAA is held at a stable level by the capacitor C32F.
  • Electric charges of the external capacitor Cext31 are divided by the capacitor Cext31 and the load capacity of the pixel array of the pixel part 20, and a voltage of the drive control signal DTG21 (vout1p) becomes slightly lower than the boosted voltage (2vaa). Thereafter, the third signal S33 is at a low level, and the first signal S31 is at a low level again.
  • a node vhi rd (TVAA) is maintained at about 2vaa.
  • Fig. 19 is a diagram illustrating a configuration example of a pixel part and a vertical scanning circuit of a solid-state imaging device according to an eighth embodiment.
  • Fig. 20A to Fig. 20K are timing charts of a voltage generation operation, etc. of a voltage supply part 320G and a row driver 310G in the vertical scanning circuit 30G of the solid-state imaging device 10G according to the eighth embodiment.
  • a difference between the solid-state imaging device 10G according to the eighth embodiment and the solid-state imaging device 10C according to the fourth embodiment described above is as follows.
  • a switch SW36G is connected between the first node ND31 and the first power-source voltage terminal TVAA of the row driver 310G, and a capacitor C32G is connected between the first power-source voltage terminal TVAA and the first power-source potential line Lvaa of the positive power-source potential vaa.
  • the switch SW36G is on/off controlled by the third signal S33, and selectively connects between the first node ND31 and the first power-source voltage terminal TVAA in accordance with the third signal S33.
  • the third switch SW33 is turned on, the second node ND32 is connected to the first power-source potential line Lvaa, and the first node ND31 is stepped down up to the potential (vaa - vref) by capacitive coupling of the external capacitor Cext31.
  • the switch SW36G is turned on. While the switch SW36G is turned on, the step-down voltage (vaa - vref) is supplied from the first node ND31 to the first power-source voltage terminal TVAA of the row driver 310G as a voltage to be supplied lower than the positive power-source voltage (first power-source voltage).
  • the voltage level of the first power-source voltage terminal TVAA is held at a stable level by the capacitor C32G.
  • Fig. 21 is a diagram illustrating a configuration example of a pixel part and a vertical scanning circuit of a solid-state imaging device according to a ninth embodiment.
  • Fig. 22A to Fig. 22K are timing charts of a voltage generation operation, etc. of a voltage supply part 320H and a row driver 310H in the vertical scanning circuit 30H of the solid-state imaging device 10H according to the ninth embodiment.
  • a difference between the solid-state imaging device 10H according to the ninth embodiment and the solid-state imaging device 10 according to the first embodiment described above is as follows.
  • the voltage supply part 320H of the solid-state imaging device 10H according to the ninth embodiment is configured to generate a voltage lower than the negative power-source voltage vgnd instead of generating a voltage higher than the positive power-source voltage vaa and supply the generated voltage to the second power-source voltage terminal TVGND of the row driver 310H.
  • a comparator CMP31H as a level determination part 321H and the fifth switch SW35 are provided, and a voltage supplied to the row driver 310H can be adjusted to a voltage lower than the second power-source voltage (negative power-source voltage) vgnd.
  • processing in the reset duration is performed, and then the boosting operation is performed in processing in the first duration PFST and the second duration PSCD.
  • a basic operation is similar to that of the first embodiment, and thus a detailed description thereof is omitted here.
  • the comparator CMP31H compares the potential level of the first node ND31 with the reference voltage vref2, outputs the first signal S31 at the active H level to the first switch SW31 to turn on the first switch SW31 when the potential level of the first node ND31 has not reached the reference voltage vref, and outputs the first signal S31 at the inactive L level to the first switch SW31 to turn off the first switch SW31 when the potential level of the first node ND31 has reached the reference voltage vref.
  • a fourth switch SW34 that selectively connects between the second power-source potential line Lvgnd of the second power-source potential vgnd and the first node ND31 in accordance with the fourth signal S34 is provided.
  • the second node ND32 is connected to the second power-source voltage terminal TVGND of the row driver 310H.
  • the first switch SW31 and the second switch SW32 are turned on by the first signal S31 and the second signal S32 at the active H level, and the fourth switch SW34 is turned off by the fourth signal S34 at the inactive L level, so that the potential of the first node ND31 is set to the first power-source potential vaa, and the potential of the second node ND32 is set to the second power-source potential vgnd corresponding to the reference potential.
  • the first signal S31 and the second signal S32 are switched to the inactive L level to turn off the first switch SW31 and the second switch SW32, and the fourth signal S34 is switches to the active H level and turns on the fourth switch SW34.
  • the potential of the second node ND32 is lower than the second power-source potential vgnd, and is set to a potential -vref corresponding to the potential of the reference potential vref on the negative side.
  • the drive control signal DTG21 at a level of a voltage -vaa supplied from the voltage supply part 320H is applied to the corresponding drive control line LTG21.
  • Electric charges of the external capacitor Cext31 are divided by the capacitor Cext31 and the load capacity of the pixel array of the pixel part 20, and a voltage of the drive control signal DTG21 (vout1p) becomes slightly higher than the supplied voltage (-vref).
  • Fig. 23 is a diagram illustrating a configuration example of a pixel part and a vertical scanning circuit of a solid-state imaging device according to a tenth embodiment.
  • Fig. 24A to Fig. 24L are timing charts of a voltage generation operation, etc. of a voltage supply part 320I and a row driver 3101 in the vertical scanning circuit 301 of the solid-state imaging device 101 according to the tenth embodiment.
  • the level determination part 321I includes a counter CNT31I instead of the comparator.
  • the third signal S33 is switched to the active H level.
  • the third switch SW33 is turned on, the second node ND32 is connected to the second power-source potential line Lvgnd, and the second node ND32 is stepped down up to a potential (vgnd - vx (for example, vref)) by capacitive coupling of the external capacitor Cext31.
  • the step-down voltage (vgnd - vx (vref)) is supplied from the second node ND32 to the second power-source voltage terminal TVGND of the row driver 3101 as a voltage to be supplied lower than the negative power-source voltage (second power-source voltage).
  • the potential level VND32 (vgnd - vx) of the second node ND32 can be adjusted.
  • Fig. 25 is a diagram illustrating a configuration example of a pixel part and a vertical scanning circuit of a solid-state imaging device according to an eleventh embodiment.
  • Fig. 26A to Fig. 26G are timing charts of a voltage generation operation, etc. of a voltage supply part 320J and a row driver 310J in the vertical scanning circuit 30J of the solid-state imaging device 10J according to the eleventh embodiment.
  • a difference between the solid-state imaging device 10J according to the eleventh embodiment and the solid-state imaging device 10B according to the third embodiment described above is as follows.
  • a voltage lower than the negative power-source voltage vgnd is generated and supplied to the second power-source voltage terminal TVGND of the row driver 310J.
  • the fourth switch SW34 that selectively connects between the second power-source potential line Lvgnd of the second power supply potential vgnd and the first node ND31 in accordance with the fourth signal S34 is provided.
  • the second node ND32 is connected to the second power-source voltage terminal TVGND of the row driver 310J.
  • the first switch SW31 and the second switch SW32 are turned on by the first signal S31 and the second signal S32 at the active H level, and the fourth switch SW34 is turned off by the fourth signal S34 at the inactive L level, so that the potential of the first node ND31 is set to the first power-source potential vaa, and the potential of the second node ND32 is set to the second power-source potential vgnd corresponding to the reference potential.
  • the first signal S31 and the second signal S32 are switched to the inactive L level to turn off the first switch SW31 and the second switch SW32, and the fourth signal S34 is switches to the active H level and turns on the fourth switch SW34.
  • the potential of the second node ND32 is lower than the second power-source potential vgnd, and is set to a potential -vaa corresponding to the potential of the first power-source potential vaa on the negative side.
  • the drive control signal DTG21 at a level of a voltage -vaa supplied from the voltage supply part 320C is applied to the corresponding drive control line LTG21.
  • Electric charges of the external capacitor Cext31 are divided by the capacitor Cext31 and the load capacity of the pixel array of the pixel part 20, and a voltage of the drive control signal DTG21 (vout1p) becomes slightly higher than the supplied voltage (-vaa).
  • Fig. 27 is a diagram illustrating a configuration example of a pixel part and a vertical scanning circuit of a solid-state imaging device according to a twelfth embodiment.
  • Fig. 28A to Fig. 28K are timing charts of a voltage generation operation, etc. of a voltage supply part 320K and a row driver 310K in the vertical scanning circuit 30K of the solid-state imaging device 10K according to the twelfth embodiment.
  • a difference between the solid-state imaging device 10K according to the twelfth embodiment and the solid-state imaging device 10H according to the ninth embodiment described above is as follows.
  • the voltage supply part 320K of the solid-state imaging device 10K according to the twelfth embodiment instead of generating a voltage lower than the negative power-source voltage vgnd, a voltage higher than the negative power-source voltage vgnd is generated and supplied to the second power-source voltage terminal TVGND of the row driver 310K.
  • the solid-state imaging device 10K according to the twelfth embodiment is different from the solid-state imaging device 10H according to the ninth embodiment in a configuration of the voltage supply part 320K.
  • the voltage supply part 320K generates a voltage higher than the second power-source voltage (negative power-source voltage) vgnd, for example, (vgnd + vref), and supplies the generated voltage to the row driver 310K.
  • the first switch SW31 selectively connects between the first power-source potential line Lvaa and the second node ND32 in accordance with the first signal S31.
  • the second switch SW32 selectively connects between the second power-source potential line Lvgnd and the first node ND31 in accordance with the second signal S32.
  • the fourth switch SW34 selectively connects between the second power-source potential line Lvgnd and the first node ND31 in accordance with the fourth signal S34.
  • the second node ND32 is connected to the second power-source voltage terminal TVGND of the row driver 310K.
  • the fifth switch SW35 is formed of, for example, an NMOS transistor, and selectively connects between the first node ND31 and the second node ND32 in accordance with the fifth signal S35.
  • the level determination part 321K of the twelfth embodiment includes a comparator CMP31K whose non-inverted input (+) is connected to a supply line of the reference voltage vref and whose inverted input terminal (-) is connected to the second node ND32.
  • the comparator CMP31K compares the potential level VND32 of the second node ND32 with the reference voltage vref, and outputs the first signal S31 at the active H level to the first switch SW31 to turn on the first switch SW31 when the potential level VND32 of the second node ND32 is lower than the reference voltage vref. In a case in which the potential level VND32 of the second node ND32 has reached the reference voltage vref, the comparator CMP31C outputs the first signal S31 at the inactive L level to the first switch SW31 to turn off the first switch SW31.
  • the voltage supply part 320K in the twelfth embodiment At the time of generating a voltage (vgnd + vref) higher than the negative power-source voltage supplied to the row driver 310K, the voltage supply part 320K in the twelfth embodiment generates the voltage (vgnd + vref) higher than the negative power-source voltage vgnd at a desired level and supplies the generated voltage to the row driver 310K through the reset duration PRST, the first duration PFST, and the second duration PSCD.
  • Specific control timing is similar to that in a case in which the boosted voltage is -vref.
  • the first node ND31 is connected to the second power-source potential line Lvgnd when the voltage level of the second node ND32 becomes +vref, it can be considered that this operation is not pump-up.
  • the boost voltage +vref is adjustable when the reference voltage vref changes.
  • Fig. 29 is a diagram illustrating a configuration example of a pixel part and a vertical scanning circuit of a solid-state imaging device according to a thirteenth embodiment.
  • Fig. 30A to Fig. 30K are timing charts of a voltage generation operation, etc. of a voltage supply part 320L and a row driver 310L in the vertical scanning circuit 30L of the solid-state imaging device 10L according to the thirteenth embodiment.
  • a difference between the solid-state imaging device 10L according to the thirteenth embodiment and the solid-state imaging device 10H according to the ninth embodiment described above is as follows.
  • a switch SW36L is connected between the second node ND32 and the second power-source voltage terminal TVGND of the row driver 310L, and a capacitor C32L is connected between the second power-source voltage terminal TVGND and the second power-source potential line Lvgnd of the negative power-source potential vgnd.
  • the switch SW36L is on/off controlled by the fourth signal S34, and selectively connects between the second node ND32 and the second power-source voltage terminal TVGND in accordance with the fourth signal S34.
  • the fourth switch SW34 is turned on, the first node ND31 is connected to the second power-source potential line Lvgnd, and the second node ND32 is stepped down to the potential (-vref) on the negative side by capacitive coupling of the external capacitor Cext31.
  • the switch SW36L is turned on. While the switch SW36L is turned on, the step-down voltage (-vref) is supplied from the second node ND32 to the second power-source voltage terminal TVGND of the row driver 310L as a voltage to be supplied lower than the negative power-source voltage (second power-source voltage).
  • the voltage level of the second power-source voltage terminal TVGND is held at a stable level by the capacitor C32L.
  • Fig. 31 is a diagram illustrating a configuration example of a pixel part and a vertical scanning circuit of a solid-state imaging device according to a fourteenth embodiment.
  • Fig. 32A to Fig. 32L are timing charts of a voltage generation operation, etc. of a voltage supply part 320M and a row driver 310M in the vertical scanning circuit 30M of the solid-state imaging device 10M according to the fourteenth embodiment.
  • a difference between the solid-state imaging device 10M according to the fourteenth embodiment and the solid-state imaging device 101 according to the tenth embodiment described above is as follows.
  • a switch SW36M is connected between the second node ND32 and the second power-source voltage terminal TVGND of the row driver 310M, and a capacitor C32M is connected between the second power-source voltage terminal TVGND and the second power-source potential line Lvgnd of the negative power-source potential vgnd.
  • the switch SW36M is on/off controlled by the fourth signal S34, and selectively connects between the second node ND32 and the second power-source voltage terminal TVGND in accordance with the fourth signal S34.
  • the fourth switch SW34 is turned on, the first node ND31 is connected to the second power-source potential line Lvgnd, and the second node ND32 is stepped down to the potential (-vx (for example, vref)) on the negative side by capacitive coupling of the external capacitor Cext31.
  • the switch SW36M is turned on. While the switch SW36M is turned on, the step-down voltage (-vx (vref)) is supplied from the second node ND32 to the second power-source voltage terminal TVGND of the row driver 310M as a voltage to be supplied lower than the negative power-source voltage (second power-source voltage).
  • the voltage level of the second power-source voltage terminal TVGND is held at a stable level by the capacitor C32M.
  • Fig. 33 is a diagram illustrating a configuration example of a pixel part and a vertical scanning circuit of a solid-state imaging device according to a fifteenth embodiment.
  • Fig. 34A to Fig. 34H are timing charts of a voltage generation operation, etc. of a voltage supply part 320N and a row driver 310N in the vertical scanning circuit 30N of the solid-state imaging device 10N according to the fifteenth embodiment.
  • a difference between the solid-state imaging device 10N according to the fifteenth embodiment and the solid-state imaging device 10M according to the eleventh embodiment described above is as follows.
  • a switch SW36N is connected between the second node ND32 and the second power-source voltage terminal TVGND of the row driver 310N, and a capacitor C32N is connected between the second power-source voltage terminal TVGND and the second power-source potential line Lvgnd of the negative power-source potential vgnd.
  • the switch SW36N is on/off controlled by the fourth signal S34, and selectively connects between the second node ND32 and the second power-source voltage terminal TVGND in accordance with the fourth signal S34.
  • the fourth switch SW34 is turned on, the first node ND31 is connected to the second power-source potential line Lvgnd, and the second node ND32 is stepped down to the potential (-vaa) on the negative side by capacitive coupling of the external capacitor Cext31.
  • the switch SW36N is turned on. While the switch SW36N is turned on, the step-down voltage (-vaa) is supplied from the second node ND32 to the second power-source voltage terminal TVGND of the row driver 310N as a voltage to be supplied lower than the negative power-source voltage (second power-source voltage).
  • the voltage level of the second power-source voltage terminal TVGND is held at a stable level by the capacitor C32N.
  • Fig. 35 is a diagram illustrating a configuration example of a pixel part and a vertical scanning circuit of a solid-state imaging device according to a sixteenth embodiment.
  • Fig. 36A to Fig. 36K are timing charts of a voltage generation operation, etc. of a voltage supply part 3200 and a row driver 3100 in the vertical scanning circuit 30O of the solid-state imaging device 10O according to the sixteenth embodiment.
  • a difference between the solid-state imaging device 10O according to the sixteenth embodiment and the solid-state imaging device 10K according to the twelfth embodiment described above is as follows.
  • a switch SW36O is connected between the second node ND32 and the second power-source voltage terminal TVGND of the row driver 3100, and a capacitor C32O is connected between the second power-source voltage terminal TVGND and the second power-source potential line Lvgnd of the negative power-source potential vgnd.
  • the switch SW36O is on/off controlled by the fourth signal S34, and selectively connects between the second node ND32 and the second power-source voltage terminal TVGND in accordance with the fourth signal S34.
  • the fourth switch SW34 is turned on, the first node ND31 is connected to the second power-source potential line Lvgnd, and the second node ND32 is boosted to the potential (vref) on the positive side by capacitive coupling of the external capacitor Cext31.
  • the switch SW36O is turned on. While the switch SW36O is turned on, the boosted voltage (vref) is supplied from the second node ND32 to the second power-source voltage terminal TVGND of the row driver 3100 as a voltage to be supplied higher than the negative power-source voltage (second power-source voltage).
  • the voltage level of the second power-source voltage terminal TVGND is held at a stable level by the capacitor C32O.
  • the solid-state imaging devices 10 and 10A to 10O described above can be applied as imaging devices to electronic apparatuses such as a digital camera, a video camera, a portable terminal, a surveillance camera, a medical endoscope camera, etc.
  • Fig. 37 is a diagram illustrating an example of a configuration of an electronic apparatus to which a solid-state imaging device according to an embodiment is applied.
  • the electronic apparatus 800 includes a CMOS image sensor 810 to which the solid-state imaging devices 10 and 10A to 10O according to the present embodiments are applicable. Further, the electronic apparatus 800 includes an optical system (lens, etc.) 820 that guides incident light to a pixel area of the CMOS image sensor 810. The electronic apparatus 800 includes a signal processing circuit (PRC) 830 that processes an output signal of the CMOS image sensor 810.
  • PRC signal processing circuit
  • the signal processing circuit 830 performs predetermine signal processing on an output signal of the CMOS image sensor 810.
  • Various modes can be adopted for an image signal processed by the signal processing circuit 830.
  • the image signal can be displayed as a moving image on a monitor including a liquid crystal display, etc., output to a printer, or directly recorded on a recording medium such as a memory card.
  • CMOS image sensor 810 As described above, by mounting the solid-state imaging devices 10 and 10A to 10O described above as the CMOS image sensor 810, it is possible to provide a high-performance, small-sized, and low-cost camera system. Further, it is possible to realize an electronic apparatus such as a surveillance camera, a medical endoscope camera, etc. used for applications having restrictions on camera installation requirements such as a mounting size, the number of connectable cables, a cable length, an installation height, etc.

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Electromagnetism (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Transforming Light Signals Into Electric Signals (AREA)

Claims (14)

  1. Dispositif d'imagerie à l'état solide (10) comprenant :
    une partie de pixel (20) dans laquelle une pluralité de pixels sont disposés dans une matrice ; et
    un circuit de balayage vertical (30) configuré pour piloter la pluralité de pixels, dans lequel le circuit de balayage vertical (30) comprend :
    un pilote (310) configuré pour appliquer un signal de commande de pilote à un niveau de tension fourni lors de la réception d'un signal de commande à la ligne de signal de commande correspondant au pilote (310) ;
    une partie d'alimentation en tension (320) agencée dans un substrat semiconducteur, la partie d'alimentation en tension (320) étant configurée pour fournir une tension survoltée différente d'une tension de source d'alimentation positive (vaa) au pilote (310) ; et
    un condensateur externe (Cext31) agencé à l'extérieur du substrat semiconducteur, le condensateur externe (Cext31) comprenant une première
    électrode (EL31) et une deuxième électrode (EL32) ;
    dans lequel la partie d'alimentation en tension (320) comprend :
    un premier noeud (ND31) connecté à la première électrode (EL31) du condensateur externe (Cext31) ;
    un deuxième noeud (ND32) connecté à la deuxième électrode (EL32) du condensateur externe (Cext31) ;
    un potentiel positif de la source d'alimentation (Lvaa);
    un potentiel de masse de la source d'alimentation (Lvgnd) ;
    un premier commutateur (SW31) configuré pour établir sélectivement une connexion entre le potentiel positif de source d'alimentation (Lvaa) et le premier noeud (ND31) conformément à un premier signal (S31) ;
    un deuxième commutateur (SW32) configuré pour établir une connexion sélective entre le potentiel de source d'alimentation de masse et le deuxième noeud (ND32) conformément à un deuxième signal (S32) ; et
    un troisième commutateur (SW33) configuré pour établir une connexion sélective entre le potentiel positif de la source d'alimentation et le deuxième noeud (ND32) conformément à un troisième signal (S33),
    un comparateur (CMP31) configuré pour comparer un niveau de potentiel du premier noeud (ND31) avec une tension de référence (vref), activer le premier commutateur (SW31) en délivrant le premier signal (S31) qui est actif au premier commutateur (SW31) lorsque le niveau de potentiel du premier noeud (ND31) n'a pas atteint la tension de référence, et désactiver le premier commutateur (SW31) en émettant le premier signal (S31) qui est inactif vers le premier commutateur (SW31) lorsque le niveau de potentiel du premier noeud (ND31) a atteint la tension de référence ;
    dans lequel le premier noeud (ND31) est connecté à une borne de tension de source d'alimentation positive (PT31) du pilote (310), dans lequel la tension survoltée est déterminée sur la base de la tension de source d'alimentation positive (vaa) et de la tension de référence (vref), dans lequel le comparateur exécute un traitement de détermination de niveau lorsqu'un signal de validation (CMP-ENA) est actif,
    dans lequel la partie d'alimentation en tension (320) comprend un cinquième commutateur (SW35) configuré pour se connecter sélectivement entre le premier noeud (ND31) et le deuxième noeud (ND32) conformément à un cinquième signal,
    dans lequel, dans une durée de réinitialisation (PRST) avant la première durée, tout en établissant le signal de validation pour qu'il soit inactif pour maintenir le comparateur dans un état non opérationnel et en désactivant le premier commutateur (SW31) par le premier signal (S31) qui est inactif, la partie d'alimentation en tension (320) établit les premier et deuxième noeuds (ND31, ND32) pour qu'ils soient le potentiel de source d'alimentation au sol pour la réinitialisation en activant les deuxième et cinquième commutateurs via les deuxième et cinquième signaux qui sont actifs et en désactivant le un troisième commutateur (SW33) via le troisième signal qui est inactif ; et
    dans lequel, dans la première durée, la partie d'alimentation en tension (320) règle le signal d'activation pour qu'il soit actif afin de maintenir le comparateur I dans un état opérationnel et active le premier commutateur (SW31) via le premier signal (S31) qui est actif.
  2. Dispositif d'imagerie à semi-conducteurs selon la revendication 1, dans lequel, dans une première durée (PFST), la partie d'alimentation en tension (320) établit un potentiel du premier noeud (ND31) pour qu'il soit le potentiel positif de la source d'alimentation et établit un potentiel du deuxième noeud (ND32) pour être le potentiel de tension de masse de la source d'alimentation en tant que potentiel de référence en activant les premier et deuxième commutateurs par les premier et deuxième signaux (S31 ; S32) qui sont actifs et en désactivant le troisième commutateur (SW33) via le troisième signal qui est inactif ; et
    dans une deuxième durée (PSCD), la partie d'alimentation en tension (320) établit le potentiel du premier noeud (ND31) pour qu'il soit la tension survoltée qui est supérieure au potentiel positif de la source d'alimentation (vaa) par la tension de référence (vref) en définissant les premier et deuxième signaux (S31 ; S32) pour qu'ils soient inactifs pour désactiver les premier et deuxième commutateurs et en définissant le troisième signal pour qu'il soit actif pour activer le troisième commutateur (SW33), et
    dans lequel, tout en recevant une alimentation d'une tension supérieure à la tension de source d'alimentation positive générée au cours de la deuxième durée, le pilote (310) reçoit le signal de commande et applique le signal de commande de pilote à un niveau de tension supérieur à la tension de source d'alimentation positive à la ligne de signal de commande correspondant au pilote (310).
  3. Dispositif d'imagerie à semi-conducteurs selon l'une quelconque des revendications 1 ou 2, comprenant en outre un commutateur (SW36D, S36G) configuré pour se connecter sélectivement entre la borne de tension d'alimentation positive du pilote (310) et le premier noeud (ND31).
  4. Dispositif d'imagerie à semi-conducteurs selon la revendication 3, comprenant en outre un condensateur (C32D, C32G) connecté à la borne de tension d'alimentation positive du pilote (310).
  5. Dispositif d'imagerie à l'état solide (10C) comprenant :
    une partie de pixel (20) dans laquelle une pluralité de pixels sont disposés dans une matrice ; et
    un circuit de balayage vertical (30) configuré pour piloter la pluralité de pixels, dans lequel le circuit de balayage vertical (30) comprend :
    un pilote (310) configuré pour appliquer un signal de commande de pilote à un niveau de tension fourni lors de la réception d'un signal de commande à la ligne de signal de commande correspondant au pilote (310) ;
    une partie d'alimentation en tension (320) agencée dans un substrat semiconducteur,
    la partie d'alimentation en tension (320) étant configurée pour fournir une tension abaissée différente d'une tension de source d'alimentation positive (vaa) au pilote (310) ; et
    un condensateur externe (Cext31) disposé à l'extérieur du substrat semiconducteur, le condensateur externe (Cext31) comprenant une première
    électrode (EL31) et une deuxième électrode (EL32) ;
    dans lequel la partie d'alimentation en tension (320) comprend.
    un premier noeud (ND31) connecté à la première électrode (EL31) du condensateur externe (Cext31) ;
    un deuxième noeud (ND32) connecté à la deuxième électrode (EL32) du condensateur externe (Cext31) ;
    un potentiel positif de la source d'alimentation (Lvaa);
    un potentiel de masse de la source d'alimentation (Lvgnd) ;
    un premier commutateur (SW31) configuré pour établir sélectivement une connexion entre le potentiel positif de source d'alimentation (Lvaa) et le deuxième noeud (ND32) conformément à un premier signal (S31) ;
    un deuxième commutateur (SW32) configuré pour établir sélectivement une connexion entre le potentiel de source d'alimentation de masse et le premier noeud (ND31) conformément à un deuxième signal (S32) ; et
    un troisième commutateur (SW33) configuré pour établir une connexion sélective entre le potentiel positif de la source d'alimentation et le deuxième noeud (ND32) conformément à un troisième signal (S33),
    un comparateur (CMP31) configuré pour comparer un niveau de potentiel du deuxième noeud (ND32) avec une tension de référence (Vref), activer le premier commutateur (SW31) en délivrant le premier signal (S31) qui est actif au premier commutateur (SW31) lorsque le niveau de potentiel du deuxième noeud (ND32) n'a pas atteint la tension de référence, et éteindre le premier commutateur (SW31) en émettant le premier signal (S31) qui est inactif vers le premier commutateur (SW31) lorsque le niveau de potentiel du deuxième noeud (ND32) a atteint la tension de référence ;
    le premier noeud (ND31) est connecté à une borne de tension d'alimentation positive (PT31) du pilote (310),
    dans lequel la tension abaissée est déterminée sur la base de la tension d'alimentation positive (vaa) et de la tension de référence,
    dans lequel le comparateur exécute un traitement de détermination de niveau lorsqu'un signal de validation (CMP-ENA) est actif,
    dans lequel la partie d'alimentation en tension (320) comprend un cinquième commutateur (SW35) configuré pour se connecter sélectivement entre le premier noeud (ND31) et le deuxième noeud (ND32) conformément à un cinquième signal,
    dans lequel, dans une durée de réinitialisation (PRST) avant la première durée, tout en établissant le signal de validation pour qu'il soit inactif pour maintenir le comparateur dans un état non opérationnel et en désactivant le premier commutateur (SW31) par le premier signal (S31) qui est inactif, la partie d'alimentation en tension (320) définit les premier et deuxième noeuds (ND31 ND32) comme étant le potentiel de source d'alimentation de masse pour la réinitialisation en activant les deuxième et cinquième commutateurs via les deuxième et cinquième signaux qui sont actifs et en désactivant le troisième commutateur (SW33) à travers le troisième signal qui est inactif ; et
    dans lequel, dans la première durée, la partie d'alimentation en tension (320) règle le signal de validation pour qu'il soit actif afin de maintenir le comparateur I dans un état opérationnel et active le premier commutateur (SW31) via le premier signal (S31) qui est actif.
  6. Dispositif d'imagerie à l'état solide selon la revendication 5, dans lequel
    dans une première durée (PFST), la partie d'alimentation en tension (320) établit un potentiel du premier noeud (ND31) pour qu'il soit le potentiel de tension de masse de la source d'alimentation en tant que potentiel de référence et établit un potentiel du deuxième noeud (ND32) pour qu'il soit le potentiel positif de la source d'alimentation en activant les premier et deuxième commutateurs via les premier et deuxième signaux (S31; S32) qui sont actifs et en désactivant le troisième commutateur (SW33) via le troisième signal qui est inactif ; et
    dans une deuxième durée (PSCD), la partie d'alimentation en tension (320) établit le potentiel du premier noeud (ND31) pour qu'il soit la abaissée qui est inférieure au potentiel positif de la source d'alimentation (vaa) par la tension de référence (vref) en réglant les premier et deuxième signaux (S31 ; S32) pour qu'ils soient inactifs pour désactiver les premier et deuxième commutateurs et en réglant le troisième signal pour qu'il soit actif pour activer le troisième commutateur (SW33), et
    tout en recevant une alimentation d'une tension inférieure à la tension de source d'alimentation positive générée au cours de la deuxième durée, le pilote (310) reçoit le signal de commande et applique le signal de commande de pilote à un niveau de tension inférieur à la tension de source d'alimentation positive à la ligne de signal de commande correspondant au pilote (310).
  7. Un dispositif d'imagerie à l'état solide (10H) comprenant :
    une partie de pixel (20) dans laquelle une pluralité de pixels sont disposés dans une matrice ; et un circuit de balayage vertical (30) configuré pour piloter la pluralité de pixels, dans lequel le circuit de balayage vertical (30) comprend :
    un pilote (310) configuré pour appliquer un signal de commande de pilote à un niveau de tension fourni lors de la réception d'un signal de commande à la ligne de signal de commande correspondant au pilote (310) ;
    une partie d'alimentation en tension (320) agencée dans un substrat semiconducteur, la partie d'alimentation en tension (320) étant configurée pour fournir une tension survoltée différente d'une tension de masse de la source d'alimentation (vgnd) au pilote (310) ; et
    un condensateur externe (Cext31) disposé à l'extérieur du substrat semiconducteur, le condensateur externe (Cext31) comprenant une première électrode (EL31) et une deuxième électrode (EL32) ;
    dans lequel la partie d'alimentation en tension (320) comprend :
    un premier noeud (ND31) connecté à la première électrode (EL31) du condensateur externe (Cext31) ;
    un deuxième noeud (ND32) connecté à la deuxième électrode (EL32) du condensateur externe (Cext31) ;
    un potentiel positif de la source d'alimentation (Lvaa);
    un potentiel de masse de la source d'alimentation (Lvgnd) ;
    un premier commutateur (SW31) configuré pour établir sélectivement une connexion entre le potentiel positif de source d'alimentation (Lvaa) et le premier noeud (ND31) conformément à un premier signal (S31) ; un deuxième commutateur (SW32) configuré pour établir une connexion sélective entre le potentiel de source d'alimentation de masse et le deuxième noeud (ND32) conformément à un deuxième signal (S32) ; et
    un quatrième commutateur (SW34) configuré pour établir une connexion sélective entre le potentiel de source d'alimentation de masse et le premier noeud (ND31) conformément à un quatrième signal (S34),
    un comparateur (CMP31) configuré pour comparer un niveau de potentiel du premier noeud (ND31) avec une tension de référence (Vref), activer le premier commutateur (SW31) en délivrant le premier signal (S31) qui est actif au premier commutateur (SW31) lorsque le niveau de potentiel du premier noeud (ND31) n'a pas atteint la tension de référence, et désactiver le premier commutateur (SW31) en émettant le premier signal (S31) qui est inactif vers le premier commutateur (SW31) lorsque le niveau de potentiel du premier noeud (ND31) a atteint la tension de référence ;
    le deuxième noeud (ND32) est connecté à une borne de tension d'alimentation négative (NT31) du pilote (310), et
    dans lequel la tension survoltée est déterminée sur la base de la tension de masse de la source d'alimentation (vgnd) et de la tension de référence (vref),
    dans lequel le comparateur effectue un traitement de détermination de niveau lorsqu'un signal de validation est actif,
    dans lequel la partie d'alimentation en tension (320) comprend un cinquième commutateur (SW35) configuré pour se connecter sélectivement entre le premier noeud (ND31) et le deuxième noeud (ND32) conformément à un cinquième signal, et
    dans lequel, dans une durée de réinitialisation avant la première durée, tout en établissant le signal de validation pour qu'il soit inactif afin de maintenir le comparateur dans un état non opérationnel et en désactivant le premier commutateur (SW31) via le premier signal (S31) qui est inactif, la tension la partie d'alimentation (320) définit les premier et deuxième noeuds (ND31, ND32) comme étant le potentiel de tension de masse de la source d'alimentation pour la réinitialisation en activant les deuxième et cinquième commutateurs via les deuxième et cinquième signaux qui sont actifs et en désactivant le quatrième commutateur (SW34) via le quatrième signal qui est inactif ; et
    dans lequel, dans la première durée, la partie d'alimentation en tension (320) règle le signal de validation pour qu'il soit actif afin de maintenir le comparateur dans un état opérationnel et active le premier commutateur (SW31) via le premier signal (S31) qui est actif.
  8. Dispositif d'imagerie à semi-conducteurs selon la revendication 7, dans lequel
    dans une première durée (PFST), la partie alimentation en tension (320) établit un potentiel du premier noeud (ND31) pour être le potentiel positif de la source d'alimentation et établit un potentiel du deuxième noeud (ND32) pour être le potentiel de la tension de masse de la source d'alimentation en tant que potentiel de référence en activant les premier et deuxième commutateurs par le biais des premier et deuxième signaux (S31 ; S32) qui sont actifs et en désactivant le quatrième commutateur (SW34) par le biais du quatrième signal qui est inactif ; et
    dans une deuxième durée (PSCD), la partie d'alimentation en tension (320) établit le potentiel du deuxième noeud (ND32) pour qu'il soit la tension survoltée (vgnd-vref) qui est inférieure au potentiel de la tension de masse de la source d'alimentation et jusqu'à la tension de référence (vref) sur le côté négatif en mettant les premier et deuxième signaux (S31 ; S32) pour qu'ils soient inactifs pour désactiver les premier et deuxième commutateurs et en définissant le quatrième signal pour qu'il soit actif pour activer le quatrième commutateur (SW34), et
    tout en recevant une alimentation d'une tension inférieure à la tension de masse de la source d'alimentation générée au cours de la deuxième durée, le pilote (310) reçoit le signal de commande et applique le signal de commande de pilotage à un niveau de tension inférieur à la tension de masse de la source d'alimentation à la ligne de signal de commande correspondant au pilote (310).
  9. Un dispositif d'imagerie à semi-conducteurs (10K) comprenant :
    une partie de pixel (20) dans laquelle une pluralité de pixels sont disposés dans une matrice ; et un circuit de balayage vertical (30) configuré pour piloter la pluralité de pixels,
    dans lequel le circuit de balayage vertical (30) comprend :
    un pilote (310) configuré pour appliquer un signal de commande de pilote à un niveau de tension fourni lors de la réception d'un signal de commande à la ligne de signal de commande correspondant au pilote (310) ;
    une partie d'alimentation en tension (320) agencée dans un substrat semiconducteur, la partie d'alimentation en tension (320) étant configurée pour fournir une tension survoltée différente d'une tension de masse de la source d'alimentation (vgnd) au pilote (310) ; et
    un condensateur externe (Cext31) disposé à l'extérieur du substrat semiconducteur, le condensateur externe (Cext31) comprenant une première électrode (EL31) et une deuxième électrode (EL32) ;
    dans lequel la partie d'alimentation en tension (320) comprend :
    un premier noeud (ND31) connecté à la première électrode (EL31) du condensateur externe (Cext31) ;
    un deuxième noeud (ND32) connecté à la deuxième électrode (EL32) du condensateur externe (Cext31) ;
    un potentiel positif de la source d'alimentation (Lvaa);
    un potentiel de masse de la source d'alimentation (Lvgnd) ;
    un premier commutateur (SW31) configuré pour établir sélectivement une connexion entre le potentiel positif de source d'alimentation (Lvaa) et le deuxième noeud (ND32) conformément à un premier signal (S31) ;
    un deuxième commutateur (SW32) configuré pour établir sélectivement une connexion entre le potentiel de source d'alimentation de masse et le premier noeud (ND31) conformément à un deuxième signal (S32) ; et
    un quatrième commutateur (SW34) configuré pour établir une connexion sélective entre le potentiel de source d'alimentation de masse et le premier noeud (ND31) conformément à un quatrième signal (S34),
    un comparateur (CMP31) configuré pour comparer un niveau de potentiel du deuxième noeud (ND32) avec une tension de référence (Vref), activer le premier commutateur (SW31) en délivrant le premier signal (S31) qui est actif au premier commutateur (SW31) lorsque le niveau de potentiel du deuxième noeud (ND32) n'a pas atteint la tension de référence, et éteindre le premier commutateur (SW31) en émettant le premier signal (S31) qui est inactif vers le premier commutateur (SW31) lorsque le niveau de potentiel du deuxième noeud (ND32) a atteint la tension de référence ;
    le deuxième noeud (ND32) est connecté à une borne de tension d'alimentation négative (NT31) du pilote (310), et
    dans lequel la tension survoltée est déterminée sur la base de la tension de masse de la source d'alimentation (vgnd) et de la tension de référence (vref),
    dans lequel le comparateur effectue un traitement de détermination de niveau lorsqu'un signal de validation est actif,
    dans lequel la partie d'alimentation en tension (320) comprend un cinquième commutateur (SW35) configuré pour se connecter sélectivement entre le premier noeud (ND31) et le deuxième noeud (ND32) conformément à un cinquième signal, et
    dans lequel, dans une durée de réinitialisation avant la première durée, tout en établissant le signal de validation pour qu'il soit inactif afin de maintenir le comparateur dans un état non opérationnel et en désactivant le premier commutateur (SW31) via le premier signal (S31) qui est inactif, la tension la partie d'alimentation (320) définit les premier et deuxième noeuds (ND31, ND32) comme étant le potentiel de tension de masse de la source d'alimentation pour la réinitialisation en activant les deuxième et cinquième commutateurs via les deuxième et cinquième signaux qui sont actifs et en désactivant le quatrième commutateur (SW34) via le quatrième signal qui est inactif ; et
    dans lequel, dans la première durée, la partie d'alimentation en tension (320) règle le signal de validation pour qu'il soit actif afin de maintenir le comparateur dans un état opérationnel et active le premier commutateur (SW31) via le premier signal (S31) qui est actif.
  10. Dispositif d'imagerie à l'état solide selon la revendication 9, dans lequel
    dans une première durée (PFST), la partie d'alimentation en tension (320) établit un potentiel du premier noeud (ND31) pour qu'il soit le potentiel de tension de masse de la source d'alimentation en tant que potentiel de référence et établit un potentiel du deuxième noeud (ND32) pour qu'il soit le potentiel positif de la source d'alimentation en activant les premier et deuxième commutateurs via les premier et deuxième signaux (S31; S32) qui sont actifs et en désactivant le quatrième commutateur (SW34) via le quatrième signal qui est inactif ; et
    dans une deuxième durée (PSCD), la partie d'alimentation en tension (320) fixe le potentiel du deuxième noeud (ND32) à la tension survoltée (vgnd+vref) qui est supérieure au potentiel de la source d'alimentation de masse et jusqu'à la tension de référence (vref) sur le côté positif en réglant les premier et deuxième signaux (S31 ; S32) pour qu'ils soient inactifs pour éteindre les premier et deuxième commutateurs et en réglant le quatrième signal pour qu'il soit actif pour allumer le quatrième commutateur (SW34), et
    tout en recevant une alimentation d'une tension supérieure à la tension de masse de la source d'alimentation générée au cours de la deuxième durée, le pilote (310) reçoit le signal de commande et applique le signal de commande de pilotage à un niveau de tension supérieur à la tension de masse de la source d'alimentation à la ligne de signal de commande correspondant au pilote (310).
  11. Dispositif d'imagerie à semi-conducteurs selon l'une quelconque des revendications 7 à 10, comprenant en outre un commutateur (SW36L, SW360) configuré pour se connecter sélectivement entre la borne de tension de source d'alimentation négative du pilote (310) sur un côté négatif et le deuxième noeud (ND32).
  12. Dispositif d'imagerie à semi-conducteurs selon la revendication 11, comprenant en outre un condensateur connecté à la borne de tension de source d'alimentation négative du pilote (310) du côté négatif.
  13. Dispositif d'imagerie à l'état solide selon l'une quelconque des revendications 1 à 12, dans lequel chacun de la pluralité de pixels comprend :
    un élément de conversion photoélectrique (PD21) configuré pour stocker une charge électrique générée par conversion photoélectrique pendant une durée de stockage ;
    un élément de transfert (TG21 -Tr) capable de transférer la charge électrique stockée au niveau de l'élément de conversion photoélectrique, dans une durée de transfert pendant laquelle un signal de commande de pilotage de transfert est appliqué à une première ligne de commande de pilotage ;
    une diffusion flottante (FD21) à laquelle la charge électrique stockée au niveau de l'élément de conversion photoélectrique est transférée à travers l'élément de transfert ;
    un élément suiveur de source (SF21 -Tr) configuré pour convertir la charge électrique au niveau de la diffusion flottante en un signal de tension en fonction de la quantité de charge électrique et délivrer le signal converti à un noeud de sortie ; et
    un élément de réinitialisation (RST21 -Tr) configuré pour réinitialiser la diffusion flottante à un potentiel prédéterminé pendant une durée de réinitialisation pendant laquelle un signal de commande de pilotage de réinitialisation est appliqué à une deuxième ligne de commande de pilotage.
  14. Procédé de pilotage d'un dispositif d'imagerie à semi-conducteurs comprenant :
    une partie de pixel (20) dans laquelle une pluralité de pixels sont disposés dans une matrice ; et un circuit de balayage vertical (30) configuré pour piloter la pluralité de pixels,
    le circuit de balayage vertical (30) comprenant :
    un pilote (310) configuré pour appliquer un signal de commande de pilote à un niveau de tension fourni lors de la réception d'un signal de commande à une ligne de signal de commande correspondant au pilote (310) ;
    une partie d'alimentation en tension (320) agencée dans un substrat semiconducteur, la partie d'alimentation en tension (320) étant configurée pour fournir une tension survoltée différente d'une tension de source d'alimentation positive (vaa) au pilote (310), et
    un condensateur externe (Cext31) disposé à l'extérieur du substrat semiconducteur, le condensateur externe (Cext31) comprenant une première électrode (EL31) et une deuxième électrode (EL32) ;
    la partie d'alimentation en tension (320) comprenant :
    un premier noeud (ND31) connecté à la première électrode du condensateur externe (Cext31) ;
    un deuxième noeud (ND32) connecté à la deuxième électrode du condensateur externe (Cext31) ;
    un potentiel positif de la source d'alimentation (Lvaa);
    un potentiel de masse de la source d'alimentation (Lvgnd) ;
    un premier commutateur (SW31) configuré pour établir une connexion sélective entre le potentiel positif de la source d'alimentation et le premier noeud (ND31) conformément à un premier signal (S31)
    un deuxième commutateur (SW32) configuré pour établir une connexion sélective entre le potentiel de source d'alimentation de masse et le deuxième noeud (ND32) conformément à un deuxième signal (S32) ; et
    un troisième commutateur (SW33) configuré pour établir une connexion sélective entre le potentiel positif de la source d'alimentation et le deuxième noeud (ND32) conformément à un troisième signal (S33), le premier noeud (ND31) étant connecté à une borne de tension positive de la source d'alimentation du pilote (310), un comparateur (CMP31) configuré pour comparer un niveau de potentiel du premier noeud (ND31) à une tension de référence (vref) ; le procédé comprenant :
    dans une première durée, l'étape consistant à établir un potentiel du premier noeud (ND31) pour être le potentiel de source d'alimentation positif et établir un potentiel du deuxième noeud (ND32) pour être le potentiel de tension de masse de la source d'alimentation, en activant les premier et deuxième commutateurs par les premier et deuxième signaux (S31 ; S32) qui sont actifs et en désactivant le troisième commutateur (SW33) par le troisième signal qui est inactif, le premier commutateur étant activé par le premier signal (S31) qui est actif vers le premier commutateur et sortie du comparateur lorsque le niveau de potentiel du premier noeud (ND31) n'a pas atteint la tension de référence, le premier commutateur étant désactivé par le premier signal (S31) qui est inactif vers le premier commutateur et sorti du comparateur lorsque le niveau de potentiel du premier noeud (ND31) a atteint la tension de référence ;
    dans une deuxième durée, les étapes consistant à régler le potentiel du premier noeud (ND31) pour qu'il soit la tension survoltée qui est supérieure au potentiel positif de la source d'alimentation par la tension de référence (vref) en réglant les premier et deuxième signaux (S31 ; S32) sur être inactif pour désactiver les premier et deuxième commutateurs et régler le troisième signal pour qu'il soit actif pour activer le troisième commutateur (SW33); et
    recevoir, par le pilote (310), le signal de commande tout en recevant l'alimentation d'une tension supérieure à la tension de source d'alimentation positive générée au cours de la deuxième durée, et appliquer le signal de commande de pilotage à un niveau de tension supérieur à la tension de source d'alimentation positive à la ligne de signal de commande correspondant au pilote (310),
    où
    le comparateur est mis dans un état opérationnel lorsqu'un signal de validation est actif,
    la partie d'alimentation en tension (320) comprend un cinquième commutateur (SW35) configuré pour se connecter sélectivement entre le premier noeud (ND31) et le deuxième noeud (ND32) conformément à un cinquième signal, et
    dans une durée de réinitialisation (PRST) avant la première durée, tout en établissant le signal de validation pour qu'il soit inactif afin de maintenir la partie comparateur dans un état non opérationnel et en désactivant le premier commutateur (SW31) par le premier signal (S31) qui est inactif, la partie d'alimentation en tension (320) définit les premier et deuxième noeuds (ND32) comme étant le potentiel de source d'alimentation de masse pour la réinitialisation en activant les deuxième et cinquième commutateurs via les deuxième et cinquième signaux qui sont actifs et en désactivant le troisième commutateur (SW33) à travers le troisième signal qui est inactif ; et
    dans la première durée, la partie d'alimentation en tension (320) règle le signal de validation pour qu'il soit actif afin de maintenir le comparateur dans l'état opérationnel et active le premier commutateur (SW31) par l'intermédiaire du premier signal (S31) qui est actif.
EP19189029.2A 2018-07-30 2019-07-30 Dispositif d'imagerie à semi-conducteurs et procédé d'entraînement de dispositif d'imagerie à semi-conducteurs Active EP3606047B1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2018142377 2018-07-30
JP2019116368A JP7514065B2 (ja) 2018-07-30 2019-06-24 固体撮像装置、固体撮像装置の駆動方法、および電子機器

Publications (4)

Publication Number Publication Date
EP3606047A2 EP3606047A2 (fr) 2020-02-05
EP3606047A3 EP3606047A3 (fr) 2020-05-13
EP3606047B1 true EP3606047B1 (fr) 2023-08-30
EP3606047C0 EP3606047C0 (fr) 2023-08-30

Family

ID=67513352

Family Applications (1)

Application Number Title Priority Date Filing Date
EP19189029.2A Active EP3606047B1 (fr) 2018-07-30 2019-07-30 Dispositif d'imagerie à semi-conducteurs et procédé d'entraînement de dispositif d'imagerie à semi-conducteurs

Country Status (4)

Country Link
US (1) US10694133B2 (fr)
EP (1) EP3606047B1 (fr)
CN (1) CN110784670B (fr)
TW (1) TWI753278B (fr)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11070754B1 (en) * 2020-03-24 2021-07-20 Stmicroelectronics Asia Pacific Pte Ltd. Slew rate control circuit for an image sensor
US12034368B1 (en) * 2023-02-24 2024-07-09 Omnivision Technologies, Inc. Image sensors with improved negative pump voltage settling, and circuitry for the same

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6107862A (en) * 1997-02-28 2000-08-22 Seiko Instruments Inc. Charge pump circuit
US7053945B1 (en) * 2000-07-26 2006-05-30 Micron Technolopgy, Inc. Image sensor having boosted reset
JP2002149247A (ja) * 2000-11-07 2002-05-24 Sanyo Electric Co Ltd 昇圧システム及びこれを備えた撮像装置
US20040183932A1 (en) * 2003-01-30 2004-09-23 Matsushita Electric Industrial Co., Ltd. Solid state imaging device
JP4268492B2 (ja) * 2003-10-02 2009-05-27 浜松ホトニクス株式会社 光検出装置
KR100621558B1 (ko) * 2004-11-08 2006-09-19 삼성전자주식회사 Ｃｍｏｓ 이미지 센서 및 그 구동 방법
JP4645294B2 (ja) * 2005-05-13 2011-03-09 ソニー株式会社 撮像装置と撮像装置用の電源供給方法
JP4528221B2 (ja) * 2005-07-14 2010-08-18 本田技研工業株式会社 光センサ回路およびイメージセンサ
US7843502B2 (en) * 2005-08-03 2010-11-30 Avago Technologies General Ip (Singapore) Pte. Ltd. Programmable boost signal generation method and apparatus
JP2007060377A (ja) * 2005-08-25 2007-03-08 Sakaki Horii 固体撮像装置の駆動方法
US8385498B2 (en) * 2006-05-31 2013-02-26 Kenet, Inc. Boosted charge transfer circuit
JP5200761B2 (ja) * 2008-08-22 2013-06-05 ソニー株式会社 昇圧回路、固体撮像素子およびカメラシステム
JP5713651B2 (ja) * 2010-12-10 2015-05-07 キヤノン株式会社 光電変換装置、カメラシステム及び光電変換装置の駆動方法
JP5646420B2 (ja) * 2011-09-14 2014-12-24 株式会社東芝 固体撮像装置
JP6017214B2 (ja) * 2012-07-23 2016-10-26 ソニーセミコンダクタソリューションズ株式会社 撮像装置、撮像装置の駆動方法、および撮像表示システム
US9979912B2 (en) * 2016-09-12 2018-05-22 Semiconductor Components Industries, Llc Image sensors with power supply noise rejection capabilities
CN108306502B (zh) * 2018-02-07 2020-06-05 上海艾为电子技术股份有限公司 电荷泵电路及应用其的电子装置

Also Published As

Publication number Publication date
US10694133B2 (en) 2020-06-23
TW202013948A (zh) 2020-04-01
CN110784670B (zh) 2022-02-08
EP3606047A2 (fr) 2020-02-05
EP3606047C0 (fr) 2023-08-30
US20200036923A1 (en) 2020-01-30
CN110784670A (zh) 2020-02-11
EP3606047A3 (fr) 2020-05-13
TWI753278B (zh) 2022-01-21

Similar Documents

Publication Publication Date Title
KR101705491B1 (ko) 고체 촬상 장치, 고체 촬상 장치의 신호 처리 방법, 및, 전자 기기
TWI719801B (zh) 固態攝像裝置、固態攝像裝置的驅動方法、以及電子設備
CN109769097B (zh) 固体摄像装置、固体摄像装置的驱动方法以及电子设备
US9053993B2 (en) Imaging systems with selectable column power control
US9232165B2 (en) Solid-state imaging apparatus and method for driving solid-state imaging apparatus
US10440302B2 (en) Imaging device including pixel
CN107888807B (zh) 固体摄像装置、固体摄像装置的驱动方法以及电子设备
KR100542691B1 (ko) 필팩터를 증가시킬 수 있는 씨모스 이미지 센서 및 그구동 방법
US8125550B2 (en) Correlation double sampling circuit for image sensor
EP3606048B1 (fr) Appareil d'imagerie à semi-conducteur, procédé de commande de l'appareil d'imagerie à semi-conducteur et appareil électronique
WO2010080096A1 (fr) Capteur d’images à tensions de grille de transfert commandables
EP3606047B1 (fr) Dispositif d'imagerie à semi-conducteurs et procédé d'entraînement de dispositif d'imagerie à semi-conducteurs
CN108600662B (zh) 图像传感器像素电路及成像系统
JP7514065B2 (ja) 固体撮像装置、固体撮像装置の駆動方法、および電子機器
US20170366771A1 (en) Comparing circuit and an image sensor including a current stabilization circuit
US8957953B2 (en) Imaging device and endoscopic device
Cho et al. A micropower self-clocked camera-on-a-chip
KR20100059190A (ko) 이미지 센서 및 그 구동 방법
KR100690883B1 (ko) 이미지 센서

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE APPLICATION HAS BEEN PUBLISHED

AK Designated contracting states

Kind code of ref document: A2

Designated state(s): AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR

AX Request for extension of the european patent

Extension state: BA ME

PUAL Search report despatched

Free format text: ORIGINAL CODE: 0009013

AK Designated contracting states

Kind code of ref document: A3

Designated state(s): AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR

AX Request for extension of the european patent

Extension state: BA ME

RIC1 Information provided on ipc code assigned before grant

Ipc: H02M 3/07 20060101ALI20200408BHEP

Ipc: H04N 5/376 20110101AFI20200408BHEP

Ipc: H04N 5/369 20110101ALI20200408BHEP

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: REQUEST FOR EXAMINATION WAS MADE

17P Request for examination filed

Effective date: 20201113

RBV Designated contracting states (corrected)

Designated state(s): AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: EXAMINATION IS IN PROGRESS

17Q First examination report despatched

Effective date: 20210210

RAP1 Party data changed (applicant data changed or rights of an application transferred)

Owner name: BRILLNICS SINGAPORE PTE. LTD.

REG Reference to a national code

Ref document number: 602019035994

Country of ref document: DE

Ref country code: DE

Ref legal event code: R079

Free format text: PREVIOUS MAIN CLASS: H04N0005376000

Ipc: H04N0025709000

GRAP Despatch of communication of intention to grant a patent

Free format text: ORIGINAL CODE: EPIDOSNIGR1

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: GRANT OF PATENT IS INTENDED

RIC1 Information provided on ipc code assigned before grant

Ipc: H04N 25/71 20230101ALI20230216BHEP

Ipc: H02M 3/07 20060101ALI20230216BHEP

Ipc: H04N 25/709 20230101AFI20230216BHEP

INTG Intention to grant announced

Effective date: 20230322

GRAS Grant fee paid

Free format text: ORIGINAL CODE: EPIDOSNIGR3

GRAA (expected) grant

Free format text: ORIGINAL CODE: 0009210

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE PATENT HAS BEEN GRANTED

AK Designated contracting states

Kind code of ref document: B1

Designated state(s): AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR

REG Reference to a national code

Ref country code: GB

Ref legal event code: FG4D

REG Reference to a national code

Ref country code: CH

Ref legal event code: EP

REG Reference to a national code

Ref country code: DE

Ref legal event code: R096

Ref document number: 602019035994

Country of ref document: DE

REG Reference to a national code

Ref country code: IE

Ref legal event code: FG4D

U01 Request for unitary effect filed

Effective date: 20231002

U07 Unitary effect registered

Designated state(s): AT BE BG DE DK EE FI FR IT LT LU LV MT NL PT SE SI

Effective date: 20231026

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: GR

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20231201

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: IS

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20231230

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: RS

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20230830

Ref country code: NO

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20231130

Ref country code: IS

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20231230

Ref country code: HR

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20230830

Ref country code: GR

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20231201

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: PL

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20230830

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: ES

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20230830

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: SM

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20230830

Ref country code: RO

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20230830

Ref country code: ES

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20230830

Ref country code: CZ

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20230830

Ref country code: SK

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20230830

REG Reference to a national code

Ref country code: DE

Ref legal event code: R097

Ref document number: 602019035994

Country of ref document: DE

PLBE No opposition filed within time limit

Free format text: ORIGINAL CODE: 0009261

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: GB

Payment date: 20240606

Year of fee payment: 6

U20 Renewal fee paid [unitary effect]

Year of fee payment: 6

Effective date: 20240605

26N No opposition filed

Effective date: 20240603