Classifications

• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
  • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
  • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
  • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
  • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
  • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
  • H03M13/1148—Structural properties of the code parity-check or generator matrix
  • H03M13/116—Quasi-cyclic LDPC [QC-LDPC] codes, i.e. the parity-check matrix being composed of permutation or circulant sub-matrices
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
  • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
  • H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
  • H03M13/2906—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes using block codes
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
  • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
  • H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
  • H03M13/2906—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes using block codes
  • H03M13/2927—Decoding strategies
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
  • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
  • H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
  • H03M13/2948—Iterative decoding
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
  • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
  • H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
  • H03M13/3723—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35 using means or methods for the initialisation of the decoder
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
  • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
  • H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
  • H03M13/3746—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35 with iterative decoding
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
  • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
  • H03M13/63—Joint error correction and other techniques
  • H03M13/635—Error control coding in combination with rate matching
  • H03M13/6356—Error control coding in combination with rate matching by repetition or insertion of dummy data, i.e. rate reduction
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
  • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
  • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
  • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
  • H03M13/09—Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
  • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
  • H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
  • H03M13/39—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes
  • H03M13/3994—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using state pinning or decision forcing, i.e. the decoded sequence is forced through a particular trellis state or a particular set of trellis states or a particular decoded symbol

Definitions

• the present invention relates to channel coding, and more particularly to channel coding using block codes with padding bits.
• a channel coding scheme is generally a combination of error detection, error correcting, rate matching, interleaving and transport channel or control information mapping onto/splitting from physical channels. In future wireless communication systems, further increased high data rate transmissions are expected. There is continuous need to further develop also channel coding methods to meet up the higher demands. In some coding schemes a fixed number of information bits are required at the input of the encoder. When the number of actual information bits are smaller than the required information code block size, in many coding schemes additional zero bits are included, known also as zero padding (ZP) .
• ZP zero padding
• a method comprising: receiving a first code block comprising a first information bits section and a first parity bits section for first parity bits based on first information bits of the first code block and first padding bits, the first padding bits being based on second information bits of a second code block; performing a parity check for the first code block; and updating information for decoding a received second code block on the basis of the parity check of the first code block.
• an apparatus comprising at least one processing core, at least one memory including computer program code, the at least one memory and the computer program code being configured to, with the at least one processing core, cause the apparatus at least to: receive a first code block comprising a first information bits section and a first parity bits section for first parity bits based on first information bits of the first code block and first padding bits, the first padding bits being based on second information bits of a second code block; perform a parity check for the first code block; and update information for decoding a received second code block on the basis of the parity check of the first code block.
• a method comprising: defining first padding bits for a first code block comprising a first information bits section to be transmitted over a channel to a decoder, wherein the first padding bits are based on a portion of second information bits of a second code block, and adding to the first code block a first parity bits section comprising first parity bits based on first information bits of the first code block and the first padding bits.
• an apparatus comprising at least one processing core, at least one memory including computer program code, the at least one memory and the computer program code being configured to, with the at least one processing core, cause the apparatus at least to: define first padding bits to a first code block comprising a first information bits section to be transmitted over a channel to a decoder, wherein the first padding bits are based on a portion of second information bits of a second code block, and add to the first code block a first parity bits section comprising first parity bits based on first information bits of the first code block and the first padding bits.
• At least one initial decoder input value representative of an information bit of at least one other code block before or after the first code block is improved on the basis of the outcome of the parity check of the first code block.
• a decoder input value for a portion in the second code block corresponding to the first padding bits is updated to indicate that the values in the portion in the second code bock are known.
• FIGURES 1 and 2 are flow diagrams illustrating methods in accordance with at least some embodiments of the present invention.
• FIGURE 3a illustrates an example encoder and decoder in accordance with at least some embodiments of the present invention
• FIGURE 3b illustrates further blocks for decoding in accordance with at least some embodiments of the present invention
• FIGURE 4 illustrates an example of applying repeat padding in accordance with at least some embodiments of the present invention
• FIGURES 5 and 6 illustrate examples for sequential processing applying repeat padding in accordance with at least some embodiments of the present invention
• FIGURE 7 illustrates an example for parallel processing applying repeat padding in accordance with at least some embodiments of the present invention
• FIGURE 8 illustrates procedure for received code blocks in accordance with at least some embodiments of the present invention
• FIGURE 9 illustrates an example for arranging repeated padding in accordance with at least some embodiments of the present invention.
• FIGURE 10 illustrates simulation results in accordance with at least some embodiments of the present invention.
• FIGURE 11 illustrates an example apparatus capable of supporting at least some embodiments of the present invention.
• Enhanced mobile broadband is one of 5G developments and expected to provide substantial speed and capacity increases.
• Low density parity check is a strong channel coding candidate for eMBB scenario due its superior performance while having efficient implementations to fulfil high throughput requirements.
• LDPC has already adopted by many other standards, and recently replaced LTE turbo codes in the ongoing 5G trials.
• LDPC belongs to the block coding category, where a fixed number of information bits are required at the input of the encoder.
• the transport blocks (TB) get from the upper layers are not exactly integer multiples of the information block sizes.
• LDPC does not support all the block sizes and often limited to a smaller set.
• IEEE 802.1 1n supports three information block sizes, i.e. 324, 648, and 972, for code rate 1/2.
• CB code block
• LDPC code block applied as an example embodiment below
• coded bits are ready for rate matching and transmission.
• Rate matching refers generally to puncturing and repetition schemes used to match the coded block to available resources for transmission.
• LDPC parity check matrix, H is often defined as:
• N*z is the coded block sizes
• K*z is the information block size
• (N-K) *z is the parity size.
• ZP causes rate loss not only in the information bits part but also in the parity bits. That may be a critical issue for lower code rates.
• overall BLER performance can be improved at the expense of rate loss.
• puncturing can start with ZP bits when rate matching is applied while maintaining a similar performance.
• ZP bits do nothing to improve the performance of other CBs.
• a new padding scheme has been developed which can be used instead of ZP to improve decoding system performance.
• Figure 1 illustrates a method according to some example embodiments.
• the method may be applied in an encoder device, such as an LDPC encoder.
• a first information bits section comprising first information bits is defined for a first code block and a second information bits section comprising second information bits is defined 110 for a second code block.
• These information bits sections may be defined by code segmentation of a transport block for transmission over a channel to a receiver and decoder.
• First padding bits are defined 120 for the first code block.
• the first padding bits may be based on a portion of the second information bits of the second code block.
• the padding bits may comprise a copy of a first portion of the second information bits of the second code block.
• Such padding bits may also be referred to as repeated padding RP or repeated (padding) (information) bits.
• a first parity bits section is generated and added 130 for the first code block, comprising parity bits based on first information bits of the first code block and the first padding bits. Similar procedure may be carried out for other code blocks to be transmitted, e.g. by applying third information bits as padding bits for the second code block.
• Figure 2 illustrates a method in accordance with at least some example embodiments.
• the method may be applied in a receiver decoder device, such as an LDPC decoder.
• a first code block comprising at least a first information bits section and a first parity bits section for first parity bits is received 210.
• the first parity bits are based on first information bits of the first code block and first padding bits.
• the first padding bits may be based on a portion of second information bits of a second code block.
• the received code block may comprise a first padding bit section comprising the padding bits.
• parity check is performed 220 for the first code block.
• Parity check herewith refers generally to any suitable syndrome check using parity bits (referring generally to check bits suitable for the applied parity/syndrome check method) to determine if decoding of a code block or another information element is successful or not.
• parity check is an iterative decoding method in which, after each iteration, parity check is performed to detect if a code block is decoded correctly. In general, there is a limit for number of iterations if it is not passing parity check with lower number of iterations. A similar procedure is valid when LDPC is using other syndrome checks to determine the decoder output is correct or not. For example, parity check and cyclic redundancy check (CRC) check may be applied.
• CRC cyclic redundancy check
• Information for decoding a received second code block is updated 230 on the basis of the parity check of the first code block.
• one or more decoder input values may be set or changed on the basis of the outcome or results of the decoding and the parity check, some embodiments being further illustrated below.
• the decoder input information or value is log likelihood ratio (LLR) information or value.
• LLR log likelihood ratio
• the phases of the illustrated methods may be performed in a user communications device, such as the device illustrated in Figure 11, an auxiliary device or a machine-to-machine computer, for example, or in a control device configured to control the functioning thereof, when implanted therein. It will be appreciated that the features in Figures 1 and 2 may be performed in different order and/or there may be further steps.
• the first code block may be generated 110 before the second code block.
• Figures 3a illustrates, in simplified fashion, units associated with transmitting and receiving code blocks according to some example embodiments.
• the units may be implemented in a user communications device, such as the device illustrated in Figure 11, an auxiliary device or a machine-to-machine computer, for example, or in a control device configured to control the functioning thereof, when implanted therein.
• An encoder 310 in a transmitter encodes code blocks 312 by adding parity bits based on the padding bits and information bits of the code blocks.
• the encoder 310 or another unit may define the padding bits before the parity bits generation.
• Encoded code blocks 314 may be further processed, such as rate-matched, by which padding bits may be removed, and then modulated by a modulator 316 for transmission over a wireless channel.
• a demodulator 320 in a receiver performs demodulation and received code blocks are processed for decoding by a functional unit or block 322, which may be referred to as decoder preprocessing or predecoder block, for example.
• This block 322 may prepare decoder input 324 for the decoder 326.
• the decoder input information or value may be an output value of a demodulator or a value derived from the output value of the demodulator. For example, in LPDC and in many other coding embodiments this may involve initializing log-likelihood ratio values for received soft values after demodulation. Such LLR values may be referred to as initial LLR values.
• decoder input values for received soft values may be derived via some other function, instead of using LLR values.
• a received symbol r which can also be referred to as soft value or output of the demodulator 322, derives as the summation of the transmitted symbol and a gaussian noise sample.
• n variance LLR ⁇ can be expressed:
• Figure 3b illustrates an example of decoding and related preprocessing according to at least some embodiments.
• the decoder preprocessing block 322 may perform rate de-matching 330.
• locations of bits punctured by the transmitter may be replaced via matching LLRs or zeros prior decoding.
• the repetition is applied when more resources are available to map the coded bits.
• combining LLRs is performed prior to decoding.
• the rate de-matching may involve addition of padding bits, in some embodiments from another code block. For example, if padding bits used in the transmitter side are, or are based on, a portion of information bits of another code block, the padding bits in the receiver side are generated according to same method, from a portion of information bits of a received code block corresponding to the other code block.
• a decoder input generator defines the decoder input 324 for decoding information bits of received code blocks, i.e. prepares decoding input values for the decoder.
• the decoding comprises checking of parity bits by a parity checker 334.
• the code block may be provided for code block concatenation 336 to form a transport block of the successfully decoded code blocks.
• decoding input values of a code block to be decoded can be updated 338.
• new values may be obtained to be used as decoder input for another code block, or decoding of the code block may be reattempted by the iterative decoding process.
• Such values can be used directly or as modified as updated decoder input value, instead of the initial decoding input values.
• decoder input value obtained from the decoding process may also be referred to as improved decoder input value, replacing an initial decoder input value defined on the basis of the received signal.
• the decoder input value obtained from or derived from the decoding may be first or intermediary phase of the iterative decoding process providing e.g. updated LLR values for the bits, the final outcome of which are the information bits derived.
• an LLR value updated on the basis of the decoding may be referred to as an updated/improved LLR value or an LLR value after decoding, which may replace the initial LLR value of a code block.
• decoder input value representative of an information bit of at least one other code block before or after the first code block may thus be updated 230.
• At least one initial decoder input value of at least one other code block before or after the first code block may be improved on the basis of the outcome of the parity check of the first code block. It is to be noted that in some embodiments the decoder input value of a code block having failed the parity check may be updated 338, e.g. by combining with LLR value of another code block.
• the padding bits addition 130 may be continued for other code blocks such that all blocks of a transport block are repeating as padding bits information bits instead of zero bits.
• the initial LLR for repeat information bits can be exchanged depending on which received block goes through the decoder 326 first and successfully passes the parity check 334. Then, the repeated bits can be used as known bits for the next received block. In this way, the padding bits may be used to improve the performance of all code blocks. There are many options available for further improving correctness or quality of the decoder input values based on use of the padding bits, some example embodiments being illustrated further below.
• Decoder architecture can be sequential or parallel, which may be informed to the transmitter via radio resource control (RRC) signalling.
• RRC radio resource control
• CBs When sequential processing is used at the receiver, CBs have repeat padding as illustrated in Figure 4.
• a TB with cyclic redundancy code CRC 410 is code-segmented 412, which guarantees that almost all the code blocks have a similar number of information bits.
• the difference of CBs can be a single bit when the TB size is not an integer multiple of the number of blocks, L.
• a portion of the CB2 416 is repeated 420 as padding bits 422 of the CB1 414 to fill the required information block size to start encoding process 430 for the first code block, whereby parity bits 432 are added based on the information bits 414 and the padding bits 422.
• the second code block CB2 information bits 416 may be complemented 420 with padding bits 424 comprising a copy of a portion of third information bits 418 of a third code block.
• Encoding 430 of the second code block will generate parity bits 434 for the modified second code block that contain parity for CB2 416 and the portion 424 of the CB3. Similar procedure may continue until the last CB L 426. Padding bits 428 added to the CB L may be copied from the first code block information bits. Hence, in this embodiment the last code block may provide parity for the first code block.
• an initial decoder input value for a portion in the second code block corresponding to the first padding bits may be updated 230 to indicate, instead of calculated value, that the values in the portion in the second code block are known.
• the LLR value of the bits repeated in the padding bits and decoded successfully may thus be set in 230, 338 to minimum or maximum possible LLR values.
• the values may be set in the LLR domain as -Inf/Inf when repeated bits are 0/1.
• the use of the repeat padding bits can be considered as an outer code which is used to help in decoding other received code blocks, i.e. inner code.
• a decoding procedure for sequential processing is illustrated in Figure 5.
• corresponding LLRs of the padding bits RP2 422 in the second received block 520 may be updated. This now provides more reliable information to start the decoding process of the second code block 520. This process continues for all other received blocks.
• a first code block 500 when a first code block 500 does not pass the parity check 610, decoding the received blocks is continued until there is a successful decode 620 of a code block. Then, padding bits may be used 630 as earlier for the rest of the code blocks. As there can be a cyclic nature of the repeated padding on all code blocks, decoding can be reattempted with updated 230 decoder input values for the code blocks that found to be in error. This will provide additional LLR information for the code blocks that are in error and increase the chances of decoding those successfully. After a complete cycle, the first code block can be decoded with the help of more reliable bits. In the example of Figure 6, when code block L 530 is successfully decoded, the padding bits RP1 based on the information bits of the CB1 414 may be used to improve the decoding of the first code block 510.
• decoder input information such as LLR values
• LLR values after decoding of the bits of the next successfully decoded received block used as padding bits in the failed code block may be used for reattempting to decode the failed code block. This will give additional LLR information for the padding bits.
• LLRs corresponding to padding bits RP2 in the second received block 520 can be used to update LLRs for reattempting decoding of the first received block 510, which improves chances of decoding the first code block correctly.
• Figure 7 illustrates an example embodiment for arranging repeated padding when parallel processing is applied at the receiver. Similar procedure as illustrated earlier can be used with slight modifications to assist high throughput parallel processing.
• the transmitter may receive receiver parallel processing capability indication via RRC and adapt encoding 310 accordingly.
• CB1 710 uses bits from code block CBM+1 720 as its padding bits, and similar addition of padding bits is continued for rest of the CBs.
• Decoder input values of two or more code blocks may be combined for a subsequent decoding attempt of the code block that has not passed the parity check. For example, LLR values of padding bits of such failed code block is combined with LLR values of the previous code block after decoding in the previous code block.
• decoder input values of the first block and the second block are combined for a second decoding attempt of the code blocks.
• puncturing when rate matching is applied, puncturing can start with padding bits to satisfy high spectral requirements.
• the transmitter may use padding bits for parity bits generation for a code block but remove padding bits before sending the code block. Puncturing can be started with the padding bits and then continued to parity part. In case of repetition, information bits which are not used as padding bits may be first used.
• the decoder input generator 332 may estimate LLR values for the padding bits at the punctured positions before the decoding process. According to an embodiment, in response to the received first code block lacking a section for the first padding bits, decoder input values of a portion of another code block corresponding to the first padding bits are used for decoding the first code block. Consequently, BLER may be improved.
• received initial LLR values are obtained for each portion of each of the received code blocks by rate de- matching 810 based on the received signal.
• a portion of another code block, such as the second code block 520, corresponding to the first padding bits may be copied 812 as first padding bits RP to the first code block.
• Initial LLR may be set as 0 for the first code block and as -Inf for the last code block of the transport block, for example.
• initial LLR values may then be updated 820 for the portion used corresponding to the padding bits based on the LLR of the previous code block and decoding results. If the repeat padding bits RP in previous code block pass through parity checking, the LLR of the repeated bits of current code block can be set as -Inf/Inf, when the repeated bit is 0/1.
• the initial LLR of padding bits of the current code block is combined with LLR value after decoding of the previous code block.
• the information bits of transmit block can be obtained by combining 840 information bits of code blocks.
• the repeat bits may be picked from the start of the next code block.
• this is only one possible option. Further optimization is possible by enabling to flexibly change the position of the padding bits. This may depend on the exact code construction. For example, when code rate is low, the transmitter and the receiver may be configured to use information bits at the start of the code block to serve as padding bits. Furthermore, the first code block and the second code block associated with the padding bits may be next to each other as in the previous examples, or there may be one or more code blocks in between.
• Figure 9 illustrates an embodiment, in which information bits portions 910, 912, 914 in one code block are repeated in two or more other code blocks as padding bits.
• the code block 920 comprising padding bits of multiple code blocks can serve as an outer code to help correct decoding for the other CBs.
• the padding bits in multiple code blocks may be used to improve performance of the code block 920 with repeat bits of multiple code blocks.
• the code block with good performance can use padding bits to improve the performance of the code block with bad performance. It can equalize the performance difference between code blocks to some extent.
• the LLR value of padding bits can be exchanged between code blocks, i.e. to the next code block and then back to the current code block. This may assist the decoding for the code block which does not pass the parity check.
• Parity checking matrix H with code length 648 and code rate 1/2 is used, which is specified in 802.11n.
• the padding bit number is 48.
• the modulation mode is Quadrature Phase Shift Keying (QPSK) .
• the outer first curve 111 shows the BLER without any prior information for initial LLR (LLR 0) .
• the second curve 112 in the middle shows the BLER when the initial LLR of padding bits are combined with LLR after decoding of the previous block.
• the third curve 113 shows the BLER when the initial LLR of repeated information bits are set as Inf/-Inf for repeated bits 0/1. We can see the performance improvement with LLR updating of the padding bits.
• the performance gain may vary according to padding bit number, code rate, and code length.
• Figure 11 illustrates an example apparatus capable of supporting at least some embodiments of the present invention.
• a device 10 which may be a wireless communication device or terminal, such as a mobile phone, smart phone, PDA or some other type of wireless terminal device.
• the electronic device may be a network element, such a communications device serving as an access point.
• the device may include one or more chips 1 in accordance with at least some of the embodiments illustrated above.
• a processor 111 which may comprise, for example, a single-or multi-core processor wherein a single-core processor comprises one processing core and a multi-core processor comprises more than one processing core.
• the processor 111 may comprise more than one processor.
• the processor may comprise at least one application-specific integrated circuit, ASIC.
• the processor may comprise at least one field-programmable gate array, FPGA.
• the processor may be means for performing method steps in the device.
• the processor may be configured, at least in part by computer instructions, to perform actions.
• the device 10 may comprise memory 112.
• the memory may comprise random-access memory and/or permanent memory.
• the memory may comprise at least one RAM chip.
• the memory may comprise solid-state, magnetic, optical and/or holographic memory, for example.
• the memory may be at least in part accessible to the processor 111.
• the memory may be at least in part comprised in the processor 111.
• the memory 112 may be means for storing information.
• the memory may comprise computer instructions that the processor is configured to execute. When computer instructions configured to cause the processor to perform certain actions are stored in the memory, and the device in overall is configured to run under the direction of the processor using computer instructions from the memory, the processor and/or its at least one processing core may be considered to be configured to perform said certain actions.
• the memory may be at least in part comprised in the processor.
• the memory may be at least in part external to the device 10 but accessible to the device.
• the device 10 may comprise a transmitter 113.
• the device may comprise a receiver 114.
• the transmitter and the receiver may be configured to transmit and receive, respectively, information in accordance with at least one cellular or non-cellular standard.
• the transmitter may comprise more than one transmitter.
• the receiver may comprise more than one receiver.
• the transmitter and/or receiver may be configured to operate in accordance with global system for mobile communication, GSM, wideband code division multiple access, WCDMA, long term evolution, LTE, wireless local area network, WLAN, enhanced mobile broadband (eMBB) , 5G or subsequent generation according to 3GPP, 5GTF, or another standards forum, Ethernet and/or worldwide interoperability for microwave access, WiMAX, standards, for example.
• GSM global system for mobile communication
• WCDMA wideband code division multiple access
• LTE long term evolution
• LTE long term evolution
• WLAN wireless local area network
• eMBB enhanced mobile broadband
• the device 10 may comprise a near-field communication, NFC, transceiver 115.
• the NFC transceiver may support at least one NFC technology, such as NFC, Bluetooth, Wibree or similar technologies.
• the transmitter 113 may be configured to or comprise means for, such as the encoder 310 carry out at least some of the embodiments relating to adding padding bits to a code block based on information bits of another code block.
• the receiver 114 may be configured to or comprise means for, such as the unit 322, to carry out at least some of the embodiments, such as the embodiments illustrated in at least some of Figures 3, 5, 6, or 8, relating to updating decoder input for a code block based on outcome of parity check of another code block applying such padding bits.
• the device 10 may comprise user interface, UI, 116.
• the UI may comprise at least one of a display, a keyboard, a touchscreen, a vibrator arranged to signal to a user by causing the device to vibrate, a speaker and a microphone.
• a user may be able to operate the device via the UI, for example to accept incoming telephone calls, to originate telephone calls or video calls, to browse the Internet, to manage digital files stored in the memory 112 or on a cloud accessible via the transmitter 113 and the receiver 114, or via the NFC transceiver 115, and/or to play games.
• the device 10 may comprise or be arranged to accept a user identity module 117.
• the user identity module may comprise, for example, a subscriber identity module, SIM, card installable in the device 10.
• the user identity module 117 may comprise information identifying a subscription of a user of device 10.
• the user identity module 117 may comprise cryptographic information usable to verify the identity of a user of device 10 and/or to facilitate encryption of communicated information and billing of the user of the device 10 for communication effected via the device 10.
• the processor 111 may be furnished with a transmitter arranged to output information from the processor, via electrical leads internal to the device 10, to other devices comprised in the device.
• a transmitter may comprise a serial bus transmitter arranged to, for example, output information via at least one electrical lead to memory 112 for storage therein.
• the transmitter may comprise a parallel bus transmitter.
• the processor may comprise a receiver arranged to receive information in the processor, via electrical leads internal to the device 10, from other devices comprised in the device 10.
• Such a receiver may comprise a serial bus receiver arranged to, for example, receive information via at least one electrical lead from the receiver 113 for processing in the processor.
• the receiver may comprise a parallel bus receiver.
• the device 10 may comprise further devices not illustrated in Figure 11.
• the device may comprise at least one digital camera.
• Some devices 10 may comprise a back-facing camera and a front-facing camera.
• the device may comprise a fingerprint sensor arranged to authenticate, at 1east in part, a user of the device.
• the device lacks at least one device described above.
• some devices may lack the NFC transceiver 115 and/or the user identity module 117.
• the processor 111, the memory 112, the transmitter 113, the receiver 114, the NFC transceiver 115, the UI 116 and/or the user identity module 117 may be interconnected by electrical leads internal to the device 10 in a multitude of different ways.
• each of the aforementioned devices may be separately connected to a master bus internal to the device, to allow for the devices to exchange information.
• this is only one example and depending on the embodiment various ways of interconnecting at least two of the aforementioned devices may be selected without departing from the scope of the present invention.
• At least some embodiments of the present invention find industrial application in communications.
• GSM Global system for mobile communication

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• Probability & Statistics with Applications (AREA)
• Engineering & Computer Science (AREA)
• Theoretical Computer Science (AREA)
• Mathematical Physics (AREA)
• Error Detection And Correction (AREA)

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• 2016
  • 2016-09-22 EP EP16916483.7A patent/EP3516775A4/de active Pending
  • 2016-09-22 WO PCT/CN2016/099689 patent/WO2018053744A1/en unknown

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