WO2018053744A1

WO2018053744A1 - Channel coding arrangement

Info

Publication number: WO2018053744A1
Application number: PCT/CN2016/099689
Authority: WO
Inventors: Keeth Saliya JAYASINGHE; Yi Zhang; Jingyuan Sun
Original assignee: Nokia Technologies Oy; Nokia Technologies (Beijing) Co., Ltd.
Priority date: 2016-09-22
Filing date: 2016-09-22
Publication date: 2018-03-29
Also published as: EP3516775A1; EP3516775A4

Abstract

According to an example aspect of the present invention, there is provided a method, comprising: receiving a first code block comprising a first information bits section and a first parity bits section for first parity bits based on first information bits of the first code block and first padding bits, the first padding bits being based on second information bits of a second code block; performing a parity check for the first code block; and updating information for decoding a received second code block on the basis of the parity check of the first code block.

Description

CHANNEL CODING ARRANGEMENT

FIELD

The present invention relates to channel coding， and more particularly to channel coding using block codes with padding bits.

BACKGROUND

Data and control streams from/to medium access control (MAC) layer are encoded/decoded to offer transport and control services over the radio transmission link. A channel coding scheme is generally a combination of error detection， error correcting， rate matching， interleaving and transport channel or control information mapping onto/splitting from physical channels. In future wireless communication systems， further increased high data rate transmissions are expected. There is continuous need to further develop also channel coding methods to meet up the higher demands. In some coding schemes a fixed number of information bits are required at the input of the encoder. When the number of actual information bits are smaller than the required information code block size， in many coding schemes additional zero bits are included， known also as zero padding (ZP) .

SUMMARY

The invention is defined by the features of the independent claims. Some specific embodiments are defined in the dependent claims.

According to a first aspect， there is provided a method， comprising： receiving a first code block comprising a first information bits section and a first parity bits section for first parity bits based on first information bits of the first code block and first padding bits， the first padding bits being based on second information bits of a second code block； performing a parity check for the first code block； and updating information for decoding a received second code block on the basis of the parity check of the first code block.

According to a second aspect， there is provided an apparatus， comprising at least one processing core， at least one memory including computer program code， the at least one memory and the computer program code being configured to， with the at least one processing core， cause the apparatus at least to： receive a first code block comprising a first information bits section and a first parity bits section for first parity bits based on first information bits of the first code block and first padding bits， the first padding bits being based on second information bits of a second code block； perform a parity check for the first code block； and update information for decoding a received second code block on the basis of the parity check of the first code block.

According to a third aspect， there is provided a method， comprising： defining first padding bits for a first code block comprising a first information bits section to be transmitted over a channel to a decoder， wherein the first padding bits are based on a portion of second information bits of a second code block， and adding to the first code block a first parity bits section comprising first parity bits based on first information bits of the first code block and the first padding bits.

According to a fourth aspect， there is provided an apparatus， comprising at least one processing core， at least one memory including computer program code， the at least one memory and the computer program code being configured to， with the at least one processing core， cause the apparatus at least to： define first padding bits to a first code block comprising a first information bits section to be transmitted over a channel to a decoder， wherein the first padding bits are based on a portion of second information bits of a second code block， and add to the first code block a first parity bits section comprising first parity bits based on first information bits of the first code block and the first padding bits.

According to an embodiment， at least one initial decoder input value representative of an information bit of at least one other code block before or after the first code block is improved on the basis of the outcome of the parity check of the first code block.

According to an embodiment， in response to successful parity check of the first code block， a decoder input value for a portion in the second code block corresponding to the first padding bits is updated to indicate that the values in the portion in the second code bock are known.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGURES 1 and 2 are flow diagrams illustrating methods in accordance with at least some embodiments of the present invention；

FIGURE 3a illustrates an example encoder and decoder in accordance with at least some embodiments of the present invention；

FIGURE 3b illustrates further blocks for decoding in accordance with at least some embodiments of the present invention；

FIGURE 4 illustrates an example of applying repeat padding in accordance with at least some embodiments of the present invention；

FIGURES 5 and 6 illustrate examples for sequential processing applying repeat padding in accordance with at least some embodiments of the present invention；

FIGURE 7 illustrates an example for parallel processing applying repeat padding in accordance with at least some embodiments of the present invention；

FIGURE 8 illustrates procedure for received code blocks in accordance with at least some embodiments of the present invention；

FIGURE 9 illustrates an example for arranging repeated padding in accordance with at least some embodiments of the present invention；

FIGURE 10 illustrates simulation results in accordance with at least some embodiments of the present invention； and

FIGURE 11 illustrates an example apparatus capable of supporting at least some embodiments of the present invention.

EMBODIMENTS

In next generation mobile communication systems， very high data rate transmissions are expected. Enhanced mobile broadband (eMBB) is one of 5G developments and expected to provide substantial speed and capacity increases. Low density parity check (LDPC) is a strong channel coding candidate for eMBB scenario due its superior performance while having efficient implementations to fulfil high throughput requirements. LDPC has already adopted by many other standards， and recently replaced LTE turbo codes in the ongoing 5G trials. LDPC belongs to the block coding category， where a fixed number of information bits are required at the input of the encoder. In many cases， the transport blocks (TB) get from the upper layers are not exactly integer multiples of the information block sizes. Moreover， LDPC does not support all the block sizes and often limited to a smaller set. For example， IEEE 802.1 1n supports three information block sizes， i.e. 324， 648， and 972， for code rate 1/2.

In many occasions， size of a code block (CB) ， such as LDPC code block applied as an example embodiment below， does not match the required number of bits for encoding. Therefore， zero padding bits are added at the end of each CB to perform encoding process. Finally， coded bits are ready for rate matching and transmission. Rate matching refers generally to puncturing and repetition schemes used to match the coded block to available resources for transmission.

The overall coding rate reduced by adding zero bits at the end of each CB and additional parity bits are generated for these ZP. In general， LDPC codes are constructed for fixed dimensions. LDPC parity check matrix， H， is often defined as：

where P_i， j is a cyclic-permutation matrix obtained from the zero matrix and the z by z cyclically shifted identity matrix to the right， N*z is the coded block sizes， K*z is the information block size， and (N-K) *z is the parity size. The supported information block is often limited to K*z or some other limited set if the z is allowed to adjust. For example， when K ＝ 12 and z ＝ 27， 54， 81， we get 802.11n block sizes (K*z) of 324， 648， and 972 bits. It is expected to have fixed CB sizes for 5G to guarantee lower memory usage and realization complexity. Additionally， the size of the TB and CB will be larger in 5G systems to support higher throughput scenarios. Consequently， this will increase the ZP overhead. ZP causes rate loss not only in the information bits part but also in the parity bits. That may be a critical issue for lower code rates. With ZP， overall BLER performance can be improved at the expense of rate loss. Also， puncturing can start with ZP bits when rate matching is applied while maintaining a similar performance. However， ZP bits do nothing to improve the performance of other CBs.

According to at least some example embodiments， a new padding scheme has been developed which can be used instead of ZP to improve decoding system performance.

Figure 1 illustrates a method according to some example embodiments. The method may be applied in an encoder device， such as an LDPC encoder. A first information bits section comprising first information bits is defined for a first code block and a second information bits section comprising second information bits is defined 110 for a second code block. These information bits sections may be defined by code segmentation of a transport block for transmission over a channel to a receiver and decoder. First padding bits are defined 120 for the first code block. The first padding bits may be based on a portion of the second information bits of the second code block. The padding bits may comprise a copy of a first portion of the second information bits of the second code block. Such padding bits may also be referred to as repeated padding RP or repeated (padding) (information) bits. A first parity bits section is generated and added 130 for the first code block， comprising parity bits based on first information bits of the first code block and the first padding bits. Similar procedure may be carried out for other code blocks to be transmitted， e.g. by applying third information bits as padding bits for the second code block.

Figure 2 illustrates a method in accordance with at least some example embodiments. The method may be applied in a receiver decoder device， such as an LDPC decoder. A first code block comprising at least a first information bits section and a first parity bits section for first parity bits is received 210. The first parity bits are based on first information bits of the first code block and first padding bits. The first padding bits may be based on a portion of second information bits of a second code block. The received code block may comprise a first padding bit section comprising the padding bits.

As part of decoding of the first code block， parity check is performed 220 for the first code block. Parity check herewith refers generally to any suitable syndrome check using parity bits (referring generally to check bits suitable for the applied parity/syndrome check method) to determine if decoding of a code block or another information element is successful or not. For example， LDPC is an iterative decoding method in which， after each iteration， parity check is performed to detect if a code block is decoded correctly. In general， there is a limit for number of iterations if it is not passing parity check with lower number of iterations. A similar procedure is valid when LDPC is using other syndrome checks to determine the decoder output is correct or not. For example， parity check and cyclic redundancy check (CRC) check may be applied.

Information for decoding a received second code block is updated 230 on the basis of the parity check of the first code block. Depending if the code block passes or fails the decoding， thus one or more decoder input values may be set or changed on the basis of the outcome or results of the decoding and the parity check， some embodiments being further illustrated below.

The presently disclosed use of bits of other code blocks as padding enables to improve the performance of the other code blocks. Further improvements on decoding code blocks correctly are available by exchanging decoder input information， as will be illustrated further below. In some embodiments the decoder input information or value is log likelihood ratio (LLR) information or value. However， it is to be appreciated that depending on applied decoding method， various other ways of representation as scaled or non-scaled values， appropriate as input to the decoder， representative of received symbols or bits may instead be used.

The phases of the illustrated methods may be performed in a user communications device， such as the device illustrated in Figure 11， an auxiliary device or a machine-to-machine computer， for example， or in a control device configured to control the functioning thereof， when implanted therein. It will be appreciated that the features in Figures 1 and 2 may be performed in different order and/or there may be further steps. For example， the first code block may be generated 110 before the second code block. Some further embodiments are illustrated below.

Figures 3a illustrates， in simplified fashion， units associated with transmitting and receiving code blocks according to some example embodiments. The units may be implemented in a user communications device， such as the device illustrated in Figure 11， an auxiliary device or a machine-to-machine computer， for example， or in a control device configured to control the functioning thereof， when implanted therein.

An encoder 310 in a transmitter encodes code blocks 312 by adding parity bits based on the padding bits and information bits of the code blocks. The encoder 310 or another unit may define the padding bits before the parity bits generation. Encoded code blocks 314 may be further processed， such as rate-matched， by which padding bits may be removed， and then modulated by a modulator 316 for transmission over a wireless channel.

A demodulator 320 in a receiver performs demodulation and received code blocks are processed for decoding by a functional unit or block 322， which may be referred to as decoder preprocessing or predecoder block， for example. This block 322 may prepare decoder input 324 for the decoder 326. In some embodiments， the decoder input information or value may be an output value of a demodulator or a value derived from the output value of the demodulator. For example， in LPDC and in many other coding embodiments this may involve initializing log-likelihood ratio values for received soft values after demodulation. Such LLR values may be referred to as initial LLR values. In some embodiments， decoder input values for received soft values may be derived via some other function， instead of using LLR values.

For example， in case of Additive White Gaussian Noise (AWGN) channel， as further described in [1] ， a received symbol r， which can also be referred to as soft value or output of the demodulator 322， derives as the summation of the transmitted symbol and a gaussian noise sample. Assuming noice n variance

LLR λ can be expressed：

Figure 3b illustrates an example of decoding and related preprocessing according to at least some embodiments. The decoder preprocessing block 322 may perform rate de-matching 330. Thus， locations of bits punctured by the transmitter may be replaced via matching LLRs or zeros prior decoding. The repetition is applied when more resources are available to map the coded bits. At the receiver， combining LLRs is performed prior to decoding. The rate de-matching may involve addition of padding bits， in some embodiments from another code block. For example， if padding bits used in the transmitter side are， or are based on， a portion of information bits of another code block， the padding bits in the receiver side are generated according to same method， from a portion of information bits of a received code block corresponding to the other code block. A decoder input generator defines the decoder input 324 for decoding information bits of received code blocks， i.e. prepares decoding input values for the decoder. The decoding comprises checking of parity bits by a parity checker 334. In response to successful parity check of a code block， the code block may be provided for code block concatenation 336 to form a transport block of the successfully decoded code blocks.

As further illustrated in Figure 3b， on the basis of the decoding and parity check based on the parity bits based on the padding bits copied from another code block information bits， decoding input values of a code block to be decoded can be updated 338. Based on the successfulness of the parity check of a code block， new values may be obtained to be used as decoder input for another code block， or decoding of the code block may be reattempted by the iterative decoding process. Such values can be used directly or as modified as updated decoder input value， instead of the initial decoding input values. Such decoder input value obtained from the decoding process may also be referred to as improved decoder input value， replacing an initial decoder input value defined on the basis of the received signal. It is to be noted that the decoder input value obtained from or derived from the decoding may be first or intermediary phase of the iterative decoding process providing e.g. updated LLR values for the bits， the final outcome of which are the information bits derived. In case of LDPC， an LLR value updated on the basis of the decoding may be referred to as an updated/improved LLR value or an LLR value after decoding， which may replace the initial LLR value of a code block. With reference to Figure 2， based on of the parity check 220 of the first code block， decoder input value representative of an information bit of at least one other code block before or after the first code block may thus be updated 230.

Hence， at least one initial decoder input value of at least one other code block before or after the first code block may be improved on the basis of the outcome of the parity check of the first code block. It is to be noted that in some embodiments the decoder input value of a code block having failed the parity check may be updated 338， e.g. by combining with LLR value of another code block.

The padding bits addition 130 may be continued for other code blocks such that all blocks of a transport block are repeating as padding bits information bits instead of zero bits. At the receiver， the initial LLR for repeat information bits can be exchanged depending on which received block goes through the decoder 326 first and successfully passes the parity check 334. Then， the repeated bits can be used as known bits for the next received block. In this way， the padding bits may be used to improve the performance of all code blocks. There are many options available for further improving correctness or quality of the decoder input values based on use of the padding bits， some example embodiments being illustrated further below.

The manner of including padding bits depends on the decoding mechanism employed by the receiver. Decoder architecture can be sequential or parallel， which may be informed to the transmitter via radio resource control (RRC) signalling.

When sequential processing is used at the receiver， CBs have repeat padding as illustrated in Figure 4. A TB with cyclic redundancy code CRC 410 is code-segmented 412， which guarantees that almost all the code blocks have a similar number of information bits. The difference of CBs can be a single bit when the TB size is not an integer multiple of the number of blocks， L. Next， a portion of the CB2 416 is repeated 420 as padding bits 422 of the CB1 414 to fill the required information block size to start encoding process 430 for the first code block， whereby parity bits 432 are added based on the information bits 414 and the padding bits 422. Similarly， the second code block CB2 information bits 416 may be complemented 420 with padding bits 424 comprising a copy of a portion of third information bits 418 of a third code block. Encoding 430 of the second code block will generate parity bits 434 for the modified second code block that contain parity for CB2 416 and the portion 424 of the CB3. Similar procedure may continue until the last CB L 426. Padding bits 428 added to the CB L may be copied from the first code block information bits. Hence， in this embodiment the last code block may provide parity for the first code block.

At the receiver， in response to successful parity check 220 of the first code block， an initial decoder input value for a portion in the second code block corresponding to the first padding bits may be updated 230 to indicate， instead of calculated value， that the values in the portion in the second code block are known. The LLR value of the bits repeated in the padding bits and decoded successfully may thus be set in 230， 338 to minimum or maximum possible LLR values. For example， the values may be set in the LLR domain as -Inf/Inf when repeated bits are 0/1. However， depending on the implementation， it is possible to use other representations. This further improves the reliability of the decoding.

Since the channel quality conditions may differ between different code blocks， it is possible to achieve better performance e.g. in fading channel by the presently disclosed use of padding bits. Thus， the use of the repeat padding bits can be considered as an outer code which is used to help in decoding other received code blocks， i.e. inner code.

A decoding procedure for sequential processing is illustrated in Figure 5. When the decoding 510 is successful for the first code block 500， corresponding LLRs of the padding bits RP2 422 in the second received block 520 may be updated. This now provides more reliable information to start the decoding process of the second code block 520. This process continues for all other received blocks.

If a received block does not pass the parity check， there are various options available to utilize decoding results and/or decoding input values of other code blocks to retry decoding of the failed code block with updated code input values 230.

In a first example embodiment illustrated in Figure 6， when a first code block 500 does not pass the parity check 610， decoding the received blocks is continued until there is a successful decode 620 of a code block. Then， padding bits may be used 630 as earlier for the rest of the code blocks. As there can be a cyclic nature of the repeated padding on all code blocks， decoding can be reattempted with updated 230 decoder input values for the code blocks that found to be in error. This will provide additional LLR information for the code blocks that are in error and increase the chances of decoding those successfully. After a complete cycle， the first code block can be decoded with the help of more reliable bits. In the example of Figure 6， when code block L 530 is successfully decoded， the padding bits RP1 based on the information bits of the CB1 414 may be used to improve the decoding of the first code block 510.

In a second example embodiment， decoder input information， such as LLR values， are exchanged between code blocks to improve chances of decoding a code block that failed the parity check. For example， LLR values after decoding of the bits of the next successfully decoded received block used as padding bits in the failed code block may be used for reattempting to decode the failed code block. This will give additional LLR information for the padding bits. Referring to the example of Figure 6， LLRs corresponding to padding bits RP2 in the second received block 520 can be used to update LLRs for reattempting decoding of the first received block 510， which improves chances of decoding the first code block correctly.

Figure 7 illustrates an example embodiment for arranging repeated padding when parallel processing is applied at the receiver. Similar procedure as illustrated earlier can be used with slight modifications to assist high throughput parallel processing. The transmitter may receive receiver parallel processing capability indication via RRC and adapt encoding 310 accordingly. Let us assume M parallel processing code blocks for the example in Figure 7. In this case， CB1 710 uses bits from code block CBM+1 720 as its padding bits， and similar addition of padding bits is continued for rest of the CBs. The last set of CBs (＜＝M) are repeat padded with the first set of CBs.

Decoder input values of two or more code blocks may be combined for a subsequent decoding attempt of the code block that has not passed the parity check. For example， LLR values of padding bits of such failed code block is combined with LLR values of the previous code block after decoding in the previous code block. In another example embodiment， after unsuccessful parity check of at least two code blocks， decoder input values of the first block and the second block are combined for a second decoding attempt of the code blocks.

When many code blocks are in error， retransmission might be the only feasible option to recover the transport block. However， exchanging LLR values of padding bits in both directions (between the code block comprising as padding bits information bits of another code block and the other code block) for updating 230 decoder input information can improve the decoding. Reattempts may be iteratively performed by updated values also while waiting for the retransmission. In some embodiments， decoder input information， such as LLR values， of code blocks may be exchanged between transmissions. This enables to improve performance in situations where also the retransmission includes code blocks which cannot be correctly decoded.

According to some example embodiments， when rate matching is applied， puncturing can start with padding bits to satisfy high spectral requirements. Hence， the transmitter may use padding bits for parity bits generation for a code block but remove padding bits before sending the code block. Puncturing can be started with the padding bits and then continued to parity part. In case of repetition， information bits which are not used as padding bits may be first used.

The decoder input generator 332 may estimate LLR values for the padding bits at the punctured positions before the decoding process. According to an embodiment， in response to the received first code block lacking a section for the first padding bits， decoder input values of a portion of another code block corresponding to the first padding bits are used for decoding the first code block. Consequently， BLER may be improved.

With reference to the example embodiment of Figure 8， received initial LLR values are obtained for each portion of each of the received code blocks by rate de- matching 810 based on the received signal. A portion of another code block， such as the second code block 520， corresponding to the first padding bits may be copied 812 as first padding bits RP to the first code block. Initial LLR may be set as 0 for the first code block and as -Inf for the last code block of the transport block， for example. As part of LLR setting for decoding， initial LLR values may then be updated 820 for the portion used corresponding to the padding bits based on the LLR of the previous code block and decoding results. If the repeat padding bits RP in previous code block pass through parity checking， the LLR of the repeated bits of current code block can be set as -Inf/Inf， when the repeated bit is 0/1.

If the padding bits in previous code block cannot pass through parity checking， decoding may be continued on next code block until parity check passes and use padding bits of the parity-check passing code block for one or more remaining code blocks. In another embodiment， the initial LLR of padding bits of the current code block is combined with LLR value after decoding of the previous code block. After LDPC decoding 830， the information bits of transmit block can be obtained by combining 840 information bits of code blocks.

As in above examples， the repeat bits may be picked from the start of the next code block. However， this is only one possible option. Further optimization is possible by enabling to flexibly change the position of the padding bits. This may depend on the exact code construction. For example， when code rate is low， the transmitter and the receiver may be configured to use information bits at the start of the code block to serve as padding bits. Furthermore， the first code block and the second code block associated with the padding bits may be next to each other as in the previous examples， or there may be one or more code blocks in between.

Figure 9 illustrates an embodiment， in which

information bits portions

910， 912， 914 in one code block are repeated in two or more other code blocks as padding bits. In one embodiment， the code block 920 comprising padding bits of multiple code blocks can serve as an outer code to help correct decoding for the other CBs. In another embodiment， the padding bits in multiple code blocks may be used to improve performance of the code block 920 with repeat bits of multiple code blocks.

When performance difference exists between two code blocks， e.g. different code length for code blocks， the code block with good performance can use padding bits to improve the performance of the code block with bad performance. It can equalize the performance difference between code blocks to some extent. When performance between two code blocks is similar， the LLR value of padding bits can be exchanged between code blocks， i.e. to the next code block and then back to the current code block. This may assist the decoding for the code block which does not pass the parity check.

Simulation results are shown in Figure 10. Parity checking matrix H with code length 648 and code rate 1/2 is used， which is specified in 802.11n. The padding bit number is 48. The modulation mode is Quadrature Phase Shift Keying (QPSK) . The outer first curve 111 shows the BLER without any prior information for initial LLR (LLR 0) . The second curve 112 in the middle shows the BLER when the initial LLR of padding bits are combined with LLR after decoding of the previous block. The third curve 113 shows the BLER when the initial LLR of repeated information bits are set as Inf/-Inf for repeated bits 0/1. We can see the performance improvement with LLR updating of the padding bits. The performance gain may vary according to padding bit number， code rate， and code length.

Figure 11 illustrates an example apparatus capable of supporting at least some embodiments of the present invention. Illustrated is a device 10， which may be a wireless communication device or terminal， such as a mobile phone， smart phone， PDA or some other type of wireless terminal device. The electronic device may be a network element， such a communications device serving as an access point. The device may include one or more chips 1 in accordance with at least some of the embodiments illustrated above.

Comprised in the device 10 is a processor 111， which may comprise， for example， a single-or multi-core processor wherein a single-core processor comprises one processing core and a multi-core processor comprises more than one processing core. The processor 111 may comprise more than one processor. The processor may comprise at least one application-specific integrated circuit， ASIC. The processor may comprise at least one field-programmable gate array， FPGA. The processor may be means for performing method steps in the device. The processor may be configured， at least in part by computer instructions， to perform actions.

The device 10 may comprise memory 112. The memory may comprise random-access memory and/or permanent memory. The memory may comprise at least one RAM chip. The memory may comprise solid-state， magnetic， optical and/or holographic memory， for example. The memory may be at least in part accessible to the processor 111. The memory may be at least in part comprised in the processor 111. The memory 112 may be means for storing information. The memory may comprise computer instructions that the processor is configured to execute. When computer instructions configured to cause the processor to perform certain actions are stored in the memory， and the device in overall is configured to run under the direction of the processor using computer instructions from the memory， the processor and/or its at least one processing core may be considered to be configured to perform said certain actions. The memory may be at least in part comprised in the processor. The memory may be at least in part external to the device 10 but accessible to the device.

The device 10 may comprise a transmitter 113. The device may comprise a receiver 114. The transmitter and the receiver may be configured to transmit and receive， respectively， information in accordance with at least one cellular or non-cellular standard. The transmitter may comprise more than one transmitter. The receiver may comprise more than one receiver. The transmitter and/or receiver may be configured to operate in accordance with global system for mobile communication， GSM， wideband code division multiple access， WCDMA， long term evolution， LTE， wireless local area network， WLAN， enhanced mobile broadband (eMBB) ， 5G or subsequent generation according to 3GPP， 5GTF， or another standards forum， Ethernet and/or worldwide interoperability for microwave access， WiMAX， standards， for example. The device 10 may comprise a near-field communication， NFC， transceiver 115. The NFC transceiver may support at least one NFC technology， such as NFC， Bluetooth， Wibree or similar technologies. The transmitter 113 may be configured to or comprise means for， such as the encoder 310 carry out at least some of the embodiments relating to adding padding bits to a code block based on information bits of another code block. The receiver 114 may be configured to or comprise means for， such as the unit 322， to carry out at least some of the embodiments， such as the embodiments illustrated in at least some of Figures 3， 5， 6， or 8， relating to updating decoder input for a code block based on outcome of parity check of another code block applying such padding bits.

The device 10 may comprise user interface， UI， 116. The UI may comprise at least one of a display， a keyboard， a touchscreen， a vibrator arranged to signal to a user by causing the device to vibrate， a speaker and a microphone. A user may be able to operate the device via the UI， for example to accept incoming telephone calls， to originate telephone calls or video calls， to browse the Internet， to manage digital files stored in the memory 112 or on a cloud accessible via the transmitter 113 and the receiver 114， or via the NFC transceiver 115， and/or to play games.

The device 10 may comprise or be arranged to accept a user identity module 117. The user identity module may comprise， for example， a subscriber identity module， SIM， card installable in the device 10. The user identity module 117 may comprise information identifying a subscription of a user of device 10. The user identity module 117 may comprise cryptographic information usable to verify the identity of a user of device 10 and/or to facilitate encryption of communicated information and billing of the user of the device 10 for communication effected via the device 10.

The processor 111 may be furnished with a transmitter arranged to output information from the processor， via electrical leads internal to the device 10， to other devices comprised in the device. Such a transmitter may comprise a serial bus transmitter arranged to， for example， output information via at least one electrical lead to memory 112 for storage therein. Alternatively to a serial bus， the transmitter may comprise a parallel bus transmitter. Likewise the processor may comprise a receiver arranged to receive information in the processor， via electrical leads internal to the device 10， from other devices comprised in the device 10. Such a receiver may comprise a serial bus receiver arranged to， for example， receive information via at least one electrical lead from the receiver 113 for processing in the processor. Alternatively to a serial bus， the receiver may comprise a parallel bus receiver.

The device 10 may comprise further devices not illustrated in Figure 11. For example， the device may comprise at least one digital camera. Some devices 10 may comprise a back-facing camera and a front-facing camera. The device may comprise a fingerprint sensor arranged to authenticate， at 1east in part， a user of the device. In some embodiments， the device lacks at least one device described above. For example， some devices may lack the NFC transceiver 115 and/or the user identity module 117.

The processor 111， the memory 112， the transmitter 113， the receiver 114， the NFC transceiver 115， the UI 116 and/or the user identity module 117 may be interconnected by electrical leads internal to the device 10 in a multitude of different ways. For example， each of the aforementioned devices may be separately connected to a master bus internal to the device， to allow for the devices to exchange information. However， as the skilled person will appreciate， this is only one example and depending on the embodiment various ways of interconnecting at least two of the aforementioned devices may be selected without departing from the scope of the present invention.

It is to be understood that the embodiments of the invention disclosed are not limited to the particular structures， process steps， or materials disclosed herein， but are extended to equivalents thereof as would be recognized by those ordinarily skilled in the relevant arts. It should also be understood that terminology employed herein is used for the purpose of describing particular embodiments only and is not intended to be limiting.

Reference throughout this specification to one embodiment or an embodiment means that a particular feature， structure， or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus， appearances of the phrases “in one embodiment” or “in an embodiment” in various places throughout this specification are not necessarily all referring to the same embodiment. Where reference is made to a numerical value using a term such as， for example， about or substantially， the exact numerical value is also disclosed.

As used herein， a plurality of items， structural elements， compositional elements， and/or materials may be presented in a common list for convenience. However， these lists should be construed as though each member of the list is individually identified as a separate and unique member. Thus， no individual member of such list should be construed as a de facto equivalent of any other member of the same list solely based on their presentation in a common group without indications to the contrary. In addition， various embodiments and example of the present invention may be referred to herein along with alternatives for the various components thereof. It is understood that such embodiments， examples， and alternatives are not to be construed as de facto equivalents of one another， but are to be considered as separate and autonomous representations of the present invention.

Furthermore， the described features， structures， or characteristics may be combined in any suitable manner in one or more embodiments. In the preceding description， numerous specific details are provided， such as examples of lengths， widths， shapes， etc.， to provide a thorough understanding of embodiments of the invention. One skilled in the relevant art will recognize， however， that the invention can be practiced without one or more of the specific details， or with other methods， components， materials， etc. In other instances， well-known structures， materials， or operations are not shown or described in detail to avoid obscuring aspects of the invention.

While the forgoing examples are illustrative of the principles of the present invention in one or more particular applications， it will be apparent to those of ordinary skill in the art that numerous modifications in form， usage and details of implementation can be made without the exercise of inventive faculty， and without departing from the principles and concepts of the invention. Accordingly， it is not intended that the invention be limited， except as by the claims set forth below.

The verbs “to comprise” and “to include” are used in this document as open limitations that neither exclude nor require the existence of also un-recited features. The features recited in depending claims are mutually freely combinable unless otherwise explicitly stated. Furthermore， it is to be understood that the use of ″a″ or ″an″ ， that is， a singular form， throughout this document does not exclude a plurality.

INDUSTRIAL APPLICABILITY

At least some embodiments of the present invention find industrial application in communications.

ACRONYMS LIST

3GPP Third Generation Partnership Project

5GTF Fifth Generation Technical Forum

ASIC Application-specific integrated circuit

AWGN Additive White Gaussian Noise

BLER Block Error Ratio

CB Code Block

CRC Cyclic redundancy check

DC Direct current

FPGA Field-programmable gate array

GSM Global system for mobile communication

HARQ Hybrid Automatic Repeat Request

Inf. Infinite

LDPC Low Density Parity Check

LLR Log Likelyhood Ratio

LTE Long term evolution

NFC Near-field communication

QPSK Quadrature Phase Shift Keying

RP Repeat Padding

UI User interface

TB Transmit Block

ZP Zero Padding

WCDMA Wideband code division multiple access，

WiMAX Worldwide interoperability for microwave access

WLAN Wireless local area network

CITATION LIST

[1] “IMPACT OF LLR SATURATION AND QUANTIZATION ON LDPC MIN-SUM DECODERS” ， N. Kanistras et al， University of Patras， IEEE 978-1-4244-8933-6/10

Claims

A method comprising：

- receiving a first code block comprising a first information bits section and a first parity bits section for first parity bits based on first information bits of the first code block and first padding bits， the first padding bits being based on second information bits of a second code block；

- performing a parity check for the first code block； and

- updating information for decoding a received second code block on the basis of the parity check of the first code block.
The method of claim 1， wherein at least one initial decoder input value representative of an information bit of at least one other code block before or after the first code block is improved on the basis of the outcome of the parity check of the first code block.
The method of claim 1 or 2， wherein the performing of the parity check comprises decoding of the first code block， and

the first padding bits comprise a copy of a first portion of the second information bits of the second code block.
The method of any preceding claim， wherein in response to successful parity check of the first code block， a decoder input value for a portion in the second code block corresponding to the first padding bits is updated to indicate that the values in the portion in the second code bock are known.
The method of claim 4， wherein the first portion of the second code block corresponding to the first padding bits is replaced with values confirmed as known based on the parity check of the first code block.
The method of any preceding claim， wherein the second code block comprises a second parity bits section for parity bits based on the second information bits of the second code block and second padding bits comprising a portion of third information bits of a third code block； and wherein after unsuccessful parity check of the second code block， a decoder input value of the second block is updated based on decoding result of at least one code block before or after the second block.
The method of claim 6， wherein decoder input values of the first block and the second block are combined for a second decoding attempt of the second code block.
The method of claim 6 or 7， wherein after unsuccessful parity check of the first code block and the second code block， decoder input values of the first block and the second block are combined for a second decoding attempt of the code blocks.
The method of any one of claims 6 to 8， wherein the third code block comprises：

a third padding bits section for a copy of a portion of the first information bits of the first code block， and

a third parity bits section for third parity bits based on third information bits and the third padding bits.
The method of claim 9， wherein in response to successful parity check of the third code block， a decoder input value for the portion in the first code block corresponding to the third padding bits is updated for a second decoding attempt of the first code block.
The method of any preceding claim， wherein the received first code block comprises a first padding bits section for the first padding bits.
The method of any one of claims 1 to 10， further comprising： using， in response to the first code block lacking a section for the first padding bits， decoder input values of a portion of the second code block corresponding to the first padding bits for decoding the first code block.
The method of any one of claims 2 to 12， wherein the decoder input value is a log likelihood ratio value for low-density parity-check decoding.
The method of any preceding claim， wherein the first code block and second code block belong to same transport block.
The method of any preceding claim， wherein the second code block is next to the first code block.
The method of any preceding claim 1 to 14， wherein there is at least one code block between the first code block and second code block.
A method， comprising：

- defining first padding bits for a first code block comprising a first information bits section to be transmitted over a channel to a decoder， wherein the first padding bits are based on a portion of second information bits of a second code block， and

- adding to the first code block a first parity bits section comprising first parity bits based on first information bits of the first code block and the first padding bits.
An apparatus， comprising means for performing the method according to any one of claims 1 to 17.
A decoder， configured to perform the method according to any one of claims 1 to 16.
An apparatus comprising at least one processing core， at least one memory including computer program code， the at least one memory and the computer program code being configured to， with the at least one processing core， cause the apparatus at least to：

- receive a first code block comprising a first information bits section and a first parity bits section for first parity bits based on first information bits of the first code block and first padding bits， the first padding bits being based on second information bits of a second code block；

- perform a parity check for the first code block； and

- update information for decoding a received second code block on the basis of the parity check of the first code block.
The apparatus of claim 20， wherein the apparatus is configured to improve at least one initial decoder input value representative of an information bit of at least one other code block before or after the first code block on the basis of the outcome of the parity check of the first code block.
The apparatus of claim 20 or 21， wherein the performing of the parity check comprises decoding of the first code block， and

the first padding bits comprise a copy of a first portion of the second information bits of the second code block.
The apparatus of any preceding claim 20 to 22， wherein the apparatus is configured， in response to successful parity check of the first code block， to update a decoder input value for a portion in the second code block corresponding to the first padding bits to indicate that the values in the portion in the second code bock are known.
The apparatus of claim 23， wherein the apparatus is configured to replace the first portion of the second code block corresponding to the first padding bits with values confirmed as known based on the parity check of the first code block.
The apparatus of any preceding claim 20 to 24， wherein the second code block comprises a second parity bits section for parity bits based on the second information bits of the second code block and second padding bits comprising a portion of third information bits of a third code block； and

the apparatus is configured， after unsuccessful parity check of the second code block， to update a decoder input value of the second block on the basis of decoding result of at least one code block before or after the second block.
The apparatus of claim 25， wherein the apparatus is configured to combine decoder input values of the first block and the second block for a second decoding attempt of the second code block.
The apparatus of claim 25 or 26， wherein the apparatus is configured， after unsuccessful parity check of the first code block and the second code block， to combine decoder input values of the first block and the second block for a second decoding attempt of the code blocks.
The apparatus of any one of claims 25 to 27， wherein the third code block comprises：

a third padding bits section for a copy of a portion of the first information bits of the first code block， and

a third parity bits section for third parity bits based on third information bits and the third padding bits.
The apparatus of claim 28， wherein the apparatus is configured， in response to successful parity check of the third code block， to update a decoder input value for the portion in the first code block corresponding to the third padding bits for a second decoding attempt of the first code block.
The apparatus of any preceding claim 20 to 29， wherein the received first code block comprises a first padding bits section for the first padding bits.
The apparatus of any preceding claim 20 to 29， wherein the apparatus is configured to use， in response to the first code block lacking a section for the first padding bits， decoder input values of a portion of the second code block corresponding to the first padding bits for decoding the first code block.
The apparatus of any one of claims 21 to 31， wherein the decoder input value is a log likelihood ratio value for low-density parity-check decoding.
The apparatus of any preceding claim 20 to 32， wherein the first code block and second code block belong to same transport block.
The apparatus of any preceding claim 20 to 33， wherein the second code block is next to the first code block.
The apparatus of any preceding claim 20 to 33， wherein there is at least one code block between the first code block and second code block.
An apparatus comprising at least one processing core， at least one memory including computer program code， the at least one memory and the computer program code being configured to， with the at least one processing core， cause the apparatus at least to：

- define first padding bits to a first code block comprising a first information bits section to be transmitted over a channel to a decoder， wherein the first padding bits are based on a portion of second information bits of a second code block， and

- add to the first code block a first parity bits section comprising first parity bits based on first information bits of the first code block and the first padding bits.
A non-transitory computer readable medium having stored thereon a set of computer readable instructions that， when executed by at least one processor， cause an apparatus to perform a method in accordance with at least one of claims 1-17.
A computer program configured to cause a method in accordance with at least one of claims 1-17 to be performed.