EP3389215A1 - Communication system and communication method - Google Patents
Communication system and communication method Download PDFInfo
- Publication number
- EP3389215A1 EP3389215A1 EP16872771.7A EP16872771A EP3389215A1 EP 3389215 A1 EP3389215 A1 EP 3389215A1 EP 16872771 A EP16872771 A EP 16872771A EP 3389215 A1 EP3389215 A1 EP 3389215A1
- Authority
- EP
- European Patent Office
- Prior art keywords
- signal
- data
- transmission
- clock
- data signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 230000006854 communication Effects 0.000 title claims abstract description 161
- 238000004891 communication Methods 0.000 title claims abstract description 161
- 238000000034 method Methods 0.000 title claims description 13
- 230000005540 biological transmission Effects 0.000 claims abstract description 277
- 230000007704 transition Effects 0.000 description 28
- 230000004048 modification Effects 0.000 description 26
- 238000012986 modification Methods 0.000 description 26
- 238000012546 transfer Methods 0.000 description 22
- 238000012545 processing Methods 0.000 description 18
- 230000009467 reduction Effects 0.000 description 17
- 230000000694 effects Effects 0.000 description 16
- 230000008878 coupling Effects 0.000 description 6
- 238000010168 coupling process Methods 0.000 description 6
- 238000005859 coupling reaction Methods 0.000 description 6
- 238000006243 chemical reaction Methods 0.000 description 5
- 230000007175 bidirectional communication Effects 0.000 description 4
- 230000004044 response Effects 0.000 description 4
- 230000008054 signal transmission Effects 0.000 description 4
- 238000001514 detection method Methods 0.000 description 3
- 238000003384 imaging method Methods 0.000 description 3
- 239000000284 extract Substances 0.000 description 2
- 230000010365 information processing Effects 0.000 description 2
- 238000003780 insertion Methods 0.000 description 2
- 230000037431 insertion Effects 0.000 description 2
- 238000009434 installation Methods 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 230000005855 radiation Effects 0.000 description 2
- 230000004075 alteration Effects 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000002457 bidirectional effect Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000013519 translation Methods 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/12—Synchronisation of different clock signals provided by a plurality of clock generators
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L65/00—Network arrangements, protocols or services for supporting real-time applications in data packet communication
- H04L65/40—Support for services or applications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/0008—Synchronisation information channels, e.g. clock distribution lines
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/0008—Synchronisation information channels, e.g. clock distribution lines
- H04L7/0012—Synchronisation information channels, e.g. clock distribution lines by comparing receiver clock with transmitter clock
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/04—Speed or phase control by synchronisation signals
- H04L7/06—Speed or phase control by synchronisation signals the synchronisation signals differing from the information signals in amplitude, polarity or frequency or length
Definitions
- the disclosure relates to a communication system and a communication method that are applied to transmission of a data signal.
- C-PHY specification and D-PHY specification are interface specifications for communication protocol physical layers (physical layer: PHY).
- PHY physical layer: PHY
- DSI display serial interface
- CSI camera serial interface
- PTL 1 proposes a technique that achieves stabilized signal transmission in the D-PHY specification.
- a high speed (High Speed: HS) differential signal is used for substantial transmission of a data signal.
- a low power (Low Power: LP) signal is used in a blanking period of a clock signal and the data signal.
- the HS differential signal and the LP signal are transmitted on a common transmission path.
- one transmission path (clock lane) where the clock signal is transmitted and one or a plurality of transmission paths (data lanes) where the data signal is transmitted are provided.
- a signal transmission period on each of the clock lane and the data lane includes a period in which transmission using the HS differential signal is performed and a period in which transmission using the LP signal is performed.
- the HS differential signal and the LP signal are transmitted on the common transmission path.
- the LP signal differs from the HS differential signal in a voltage value necessary for signal transmission.
- a circuit for transmission and reception of the HS differential signal and a circuit for transmission and reception of the LP signal are necessary independently, thus causing an issue of increased circuit size.
- a communication system includes a transmission device and a reception device.
- the transmission device outputs a clock signal with a clock frequency corresponding to a transmission mode, and outputs a data signal corresponding to the transmission mode.
- the reception device receives the clock signal and the data signal, and determines the transmission mode on a basis of magnitude of the clock frequency of the received clock signal.
- a communication method includes (A) to (D) as follows:
- a clock signal with a clock frequency corresponding to a transmission mode is outputted from the transmission device, and the transmission mode is determined in the reception device on the basis of magnitude of the clock frequency of the received clock signal.
- a clock signal with a clock frequency corresponding to a transmission mode is outputted from the transmission device, and the transmission mode is determined in the reception device on the basis of magnitude of the clock frequency of the received clock signal, thus making it possible to achieve reduction in circuit size in the communication system in which a voltage amplitude value varies depending on transmission modes in transmission of a data signal.
- the effects of the disclosure are not necessarily limited to the effects described above, and may be any of the effects described in the specification.
- FIG. 1 illustrates an overview of the communication system 1.
- the communication system 1 is applied to transmission of a data signal and a clock signal, and includes a transmitter 10 (a transmission device) and a receiver 20 (a reception device).
- the communication system 1 includes a clock lane CL that straddles the transmitter 10 and the receiver 20 to transmit the clock signal and a data lane DL that straddles the transmitter 10 and the receiver 20 to transmit the data signal such as image data.
- FIG. 1 illustrates an example in which one data lane DL is provided, a plurality of data lanes DL may be provided.
- the transmitter 10 includes a digital transmitter circuit and an analog transmitter circuit.
- the receiver 20 includes a digital receiver circuit and an analog receiver circuit.
- a 16-bit or 8-bit parallel signal is transmitted between the digital transmitter circuit and the analog transmitter circuit.
- the 16-bit or 8-bit parallel signal is transmitted between the digital receiver circuit and the analog receiver circuit.
- the clock lane CL the analog transmitter circuit and the analog receiver circuit are coupled to each other by a clock signal line that transmits a differential clock signal.
- the analog transmitter circuit and the analog receiver circuit are coupled to each other by a data signal line that transmits a differential data signal.
- the clock signal line and the data signal line each include a pair of positive signal line Dp and a negative signal line Dn that transmit a differential signal.
- a 1-bit serial signal is transmitted to each of the clock signal line and the data signal line.
- the transmitter 10 includes a clock transmitter circuit 110 and a data transmitter circuit 120.
- the receiver 20 includes a clock receiver circuit 210 and a data receiver circuit 220.
- the clock transmitter circuit 110 and the clock receiver circuit 210 are coupled to each other by the above-described clock signal line.
- the data transmitter circuit 120 and the data receiver circuit 220 are coupled to each other by the above-described clock signal line.
- the clock transmitter circuit 110 is a differential signal transmitter circuit that generates a differential clock signal as the clock signal and outputs the generated differential clock signal to the clock signal line. It is to be noted that the clock transmitter circuit 110 may be a ternary signal transmitter circuit that outputs a ternary level signal.
- the data transmitter circuit 120 is a differential signal transmitter circuit that generates a differential data signal as the data signal and outputs the generated differential data signal to the data signal line. It is to be noted that the data transmitter circuit 120 may be the ternary signal transmitter circuit that outputs a ternary level signal.
- the clock receiver circuit 210 is a differential signal receiver circuit that receives the differential clock signal as the clock signal via the clock signal line and performs a predetermined processing on the received differential clock signal. It is to be noted that the clock receiver circuit 210 may be a ternary signal receiver circuit that receives a ternary level signal.
- the data receiver circuit 220 is a differential signal receiver circuit that receives the differential data signal as the data signal via the data signal line and performs a predetermined processing on the received differential data signal. It is to be noted that the data receiver circuit 220 may be the ternary signal receiver circuit that receives a ternary level signal.
- FIG. 2 illustrates an example of a configuration of the communication system 1.
- the communication system 1 illustrated in FIG. 2 represents the communication system 1 illustrated in FIG. 1 by a functional block.
- the transmitter 10 includes, in the clock lane CL, a transmission mode controller 11, a clock generator 12, and a clock transmitter 13.
- the transmitter 10 includes, in the data lane DL, a transmission data generator 14 and a data transmitter 15.
- the transmission mode controller 11 decides a transmission mode in accordance with an instruction from an upper layer (e.g., a high-speed transmission control signal HS-TxCnt or a low-speed transmission control signal LS-TxCnt).
- the transmission mode controller 11 further performs a control corresponding to the decided transmission mode, on the clock generator 12 and the transmission data generator 14.
- the clock generator 12 generates a clock signal with a clock frequency Fc corresponding to a transmission mode in accordance with an instruction of the transmission mode controller 11.
- the clock generator 12 outputs the generated clock signal to the clock transmitter 13 and the transmission data generator 14.
- the clock transmitter 13 outputs the clock signal generated by the clock generator 12 to the clock signal line.
- the clock transmitter 13 outputs the clock signal generated by the clock generator 12 to a clock receiver 21 via the clock signal line.
- the transmission data generator 14 performs, in accordance with the instruction of the transmission mode controller 11, various processings such as communication protocol control, decoding of data inputted from an upper layer, insertion of a control command, and parallel serial conversion, on an inputted data signal (e.g., high-speed transmission data HS-TxData or low-speed transmission data LS-TxData), thereby generating a data signal.
- the transmission data generator 14 outputs the generated data signal to the data transmitter 15.
- the transmission data generator 14 switches the above-described various processings in accordance with the instruction of the transmission mode controller 11.
- the data transmitter 15 outputs the data signal generated by the transmission data generator 14 to a data signal line. In other words, the data transmitter 15 outputs the data signal generated by the transmission data generator 14 to a data receiver 24 via the data signal line.
- the reception mode controller 23 determines a transmission mode on the basis of a result of comparison between the received clock frequency Fc and one or a plurality of reference frequencies Fth.
- a circuit that performs determination of the transmission mode is configured by a typical pulse counter, etc., for example.
- a high-speed mode having a relatively fast transmission speed and a low-speed mode having a relatively slow transmission speed are set as the transmission modes.
- the reception mode controller 23 determines that the transmission mode is in the high-speed mode.
- the reception mode controller 23 determines that the transmission mode is in the low-speed mode.
- the reception mode controller 23 outputs information on the transmission mode obtained through the determination to the received data interpreter 25.
- the data receiver 24 receives the data signal outputted from the data transmitter 15 via the data signal line.
- the data receiver 24 outputs the received data signal to the received data interpreter 25.
- the received data interpreter 25 performs various processings such as serial parallel conversion, detection of a control command, decoding of signal data, and communication protocol control, on an inputted data signal on the basis of an inputted clock signal and inputted information on the transmission mode, thereby generating a data signal and a reception state notification signal that are to be provided to a subsequent stage.
- the received data interpreter 25 switches the above-described various processings in accordance with an instruction (transmission mode, etc.) from the reception mode controller 23.
- the received data interpreter 25 outputs the generated data signal (e.g., high-speed reception data HS-RxData or low-speed reception data LS-RxData) and the generated reception state notification signal (a high-speed reception state notification signal HS-RxState or a low-speed reception state notification signal LS-RxState) to a circuit of a subsequent stage.
- the generated data signal e.g., high-speed reception data HS-RxData or low-speed reception data LS-RxData
- the generated reception state notification signal a high-speed reception state notification signal HS-RxState or a low-speed reception state notification signal LS-RxState
- FIG. 3 illustrates an example of high-speed data transfer in the communication system 1.
- the clock frequency determiner 22 detects (or determines) that the clock frequency Fc is lower than the reference frequency Fth or that the clock signal is stopped.
- the reception mode controller 23 determines that the transmission mode is in the "low-speed mode".
- the transmission mode is in the "low-speed mode”
- the received data interpreter 25 outputs no data signal to the data lane DL.
- the clock frequency determiner 22 detects (or determines) that the clock frequency Fc becomes higher than the reference frequency Fth.
- the reception mode controller 23 determines that the transmission mode is making a transition from the "low-speed mode” to the "high-speed mode". It is to be noted that the transmission mode in this situation is handled as the "high-speed mode".
- the received data interpreter 25 observes the transition of the transmission mode on the basis of the clock signal from the clock receiver 21 and the data signal from the data receiver 24.
- the received data interpreter 25 determines, on the basis of transition of a combination of the clock signal from the clock receiver 21 and the data signal from the data receiver 24, whether the transmission mode is in the middle of actually making a transition from the "low-speed mode” to the "high-speed mode", or the transition from the "low-speed mode” to the "high-speed mode” has been completed to cause the transmission mode to be shifted to the "high-speed mode".
- the received data interpreter 25 determines that the transmission mode is in the "high-speed mode". In this situation, when a data signal is inputted from the data receiver 24, the received data interpreter 25 transfers, on the data lane DL, the inputted data signal at the "high-speed mode".
- the clock frequency determiner 22 detects (or determines) that the clock frequency Fc becomes lower than the reference frequency Fth.
- the reception mode controller 23 determines that the transmission mode is making a transition from the "high-speed mode” to the "low-speed mode". It is to be noted that the transmission mode in this situation is handled as the "low-speed mode".
- the received data interpreter 25 observes the transition of the transmission mode on the basis of the clock signal from the clock receiver 21 and the data signal from the data receiver 24.
- FIG. 4 illustrates an example of low-speed data transfer in the communication system 1.
- the clock frequency determiner 22 detects (or determines) that the clock frequency Fc is lower than the reference frequency Fth or that the clock signal is stopped.
- the reception mode controller 23 determines that the transmission mode is in the "low-speed mode".
- the transmission mode is in the "low-speed mode”
- the received data interpreter 25 outputs no data signal to the data lane DL.
- the received data interpreter 25 transfers, on the data lane DL, the inputted data signal at the "low-speed mode”.
- a communication system in which a voltage amplitude value varies depending on transmission modes in transmission of a data signal has been utilized.
- types of transmission modes have been determined by detecting the voltage amplitude value.
- a determination method involves preparing a driver circuit or a receiver circuit for each magnitude of amplitude voltage values, causing an issue in which a circuit size is likely to be increased.
- a clock signal with the clock frequency Fc corresponding to a transmission mode is outputted from the transmitter 10, and the transmission mode is determined in the receiver 20 on the basis of magnitude of the clock frequency Fc of the received clock signal.
- the transmission mode is determined in the receiver 20 on the basis of the result of the comparison between the clock frequency Fc and the one or a plurality of reference frequencies Fth.
- a circuit that performs such a determination may be configured by a typical pulse counter, etc. Accordingly, separately providing the circuit that performs such a determination does not prevent the reduction in circuit size.
- the communication system 1 of the present embodiment is also applicable to the high-speed interface specifications (e.g., the C-PHY specification and the D-PHY specification). Accordingly, it is also possible, in such high-speed interface specifications, to achieve the reduction in circuit size.
- the high-speed interface specifications e.g., the C-PHY specification and the D-PHY specification. Accordingly, it is also possible, in such high-speed interface specifications, to achieve the reduction in circuit size.
- FIG. 5 illustrates a modification example of the configuration of the communication system 1 of the foregoing embodiment.
- the communication system 1 illustrated in FIG. 5 neither the low-speed transmission control signal LS-TxCnt nor the low-speed transmission data LS-TxData is inputted to the transmitter 10. That is, the communication system 1 of the present modification example differs from the configuration of the communication system 1 of the foregoing embodiment in that neither the low-speed transmission control signal LS-TxCnt nor the low-speed transmission data LS-TxData is inputted from the upper layer. Further, in the communication system illustrated in FIG. 5 , neither the low-speed reception state notification signal LS-RxState nor the low-speed reception data LS-RxData is outputted from the receiver 20.
- the communication system 1 of the present modification example differs from the configuration of the communication system 1 of the foregoing embodiment in that neither the low-speed reception state notification signal LS-RxState nor the low-speed reception data LS-RxData is outputted to a subsequent stage of the communication system 1. Therefore, in the following, the low-speed data transfer is mainly described.
- FIG. 6 illustrates an example of low-speed data transfer in the communication system 1 of the present modification example.
- the clock frequency determiner 22 detects (or determines) that the clock frequency Fc is lower than the reference frequency Fth or that the clock signal is stopped.
- the reception mode controller 23 determines that the transmission mode is in the "low-speed mode".
- the transmission mode is in the "low-speed mode"
- the received data interpreter 25 outputs no data signal to the data lane DL.
- the transmission mode is in the "low-speed mode"
- the received data interpreter 25 transfers, on the data lane DL, the control command included in the inputted data signal at the "low-speed mode". It is to be noted that the control command is generated at the transmission data generator 14 in the receiver 10, and is not inputted from the upper layer.
- a clock signal with the clock frequency Fc corresponding to a transmission mode is outputted from the transmitter 10, and the transmission mode is determined in the receiver 20 on the basis of magnitude of the clock frequency Fc of the received clock signal.
- FIG. 7 illustrates a modification example of the configuration of the communication system 1 of the foregoing embodiment.
- the communication system 1 illustrated in FIG. 7 includes a plurality of data lanes LD.
- the communication system 1 of the present modification example differs from the configuration of the communication system 1 of the foregoing embodiment in that the plurality of data lanes LD are provided.
- a clock signal with the clock frequency Fc corresponding to a transmission mode is outputted from the transmitter 10, and the transmission mode is determined in the receiver 20 on the basis of magnitude of the clock frequency Fc of the received clock signal, in each of the data lanes DL. This therefore makes it possible to achieve reduction in circuit size in the communication system in which the voltage amplitude value varies depending on transmission modes in the transmission of the data signal.
- FIG. 8 illustrates a modification example of the configuration of the communication system 1 of the foregoing embodiment.
- the communication system 1 illustrated in FIG. 8 includes, in the data lane LD, a plurality of data signal lines that each couple the transmitter 10 and the receiver 20 together and are each provided therebetween. Accordingly, the communication system 1 of the present modification example differs from the configuration of the communication system 1 of the foregoing embodiment in that it is possible to perform parallel transmission in the data lane LD.
- the transmission mode is determined in the receiver 20 on the basis of the result of the comparison between the clock frequency Fc and the one or a plurality of reference frequencies Fth.
- a circuit that performs such a determination may be configured by a typical pulse counter, etc. Accordingly, separately providing the circuit that performs such a determination does not prevent the reduction in circuit size.
- the communication system 1 of the present embodiment is also applicable to the high-speed interface specifications (e.g., the C-PHY specification and the D-PHY specification). Accordingly, it is also possible, in such high-speed interface specifications, to achieve the reduction in circuit size.
- the high-speed interface specifications e.g., the C-PHY specification and the D-PHY specification. Accordingly, it is also possible, in such high-speed interface specifications, to achieve the reduction in circuit size.
- the reception mode controller 23 turns ON the terminating resistance Rt (the first terminating resistance) and the terminating resistance Rt (the second terminating resistance). Specifically, in a case where the transmission mode is in the "low-speed mode", when there is an input of a control command that turns ON the terminating resistance Rt (the first terminating resistance) and the terminating resistance Rt (the second terminating resistance), as the received control command RxCom, the reception mode controller 23 turns ON the terminating resistance Rt (the first terminating resistance) and the terminating resistance Rt (the second terminating resistance).
- the clock frequency determiner 22 detects (or determines) that the clock frequency Fc is lower than the reference frequency Fth. Further, suppose that there has been an input of the control command (the control command RxCom) that turns ON the terminating resistance Rt (the first terminating resistance) and the terminating resistance Rt (the second terminating resistance), as the received control command RxCom. In this situation, the reception mode controller 23 determines that the transmission mode is making a transition from the "low-speed mode" to the "high-speed mode". It is to be noted that the transmission mode in this situation is handled as the "low-speed mode”. Further, the reception mode controller 23 causes the terminating resistance Rt (the first terminating resistance) and the terminating resistance Rt (the second terminating resistance) to be shifted from OFF to ON.
- the control command the control command RxCom
- the clock frequency determiner 22 detects (or determines) that the clock frequency Fc becomes higher than the reference frequency Fth.
- the reception mode controller 23 determines that the transmission mode is in the "high-speed mode".
- the transmission mode is in the "high-speed mode”
- the received data interpreter 25 transfers, on the data lane DL, the inputted data signal at the "high-speed mode”.
- the communication system 3 of the present embodiment is also applicable to the high-speed interface specifications (e.g., the C-PHY specification and the D-PHY specification). Accordingly, separately providing the circuit that performs such a determination does not prevent the reduction in circuit size.
- the high-speed interface specifications e.g., the C-PHY specification and the D-PHY specification. Accordingly, separately providing the circuit that performs such a determination does not prevent the reduction in circuit size.
- the received data interpreter 17 Upon extracting the transmission direction switch signal TraChan included in the inputted data signal, the received data interpreter 17 outputs, to the transmission mode controller 11, the extracted transmission direction switch signal TraChan as the received control command RxCom.
- the transmission mode controller 11 When the transmission direction switch signal TraChan is inputted as the control command RxCom, the transmission mode controller 11 outputs, to the upper layer on side of the master 30, the transmission direction switch signal TraChan as the transmission direction notification signal TraAna.
- the transmission mode controller 11 outputs to the transmission data generator 14 a response to the effect that an input of the transmission direction switch signal TraChan has been accepted.
- the reception mode controller 23 outputs to the transmission data generator 14 a signal indicating that the input of the transmission direction switch signal TraChan has been accepted (hereinafter, referred to as an "acceptance signal"), as the control command TxCom to be transmitted.
- the transmission data generator 14 generates a data signal including the inputted acceptance signal, and outputs the generated data signal to the data transmitter 15.
- the data transmitter 15 outputs the inputted data signal to the data receiver 24 via the data signal line at the "low-speed mode".
- the data receiver 24 outputs the inputted data signal to the received data interpreter 25.
- a clock signal with the clock frequency Fc corresponding to a transmission mode is outputted from the master 30, and the transmission mode is determined in the slave 40 on the basis of magnitude of the clock frequency Fc of the received clock signal.
- the communication system 4 of the present embodiment is also applicable to the high-speed interface specifications (e.g., the C-PHY specification and the D-PHY specification). Accordingly, it is possible, even in such high-speed interface specifications, to achieve the reduction in circuit size.
- the high-speed interface specifications e.g., the C-PHY specification and the D-PHY specification. Accordingly, it is possible, even in such high-speed interface specifications, to achieve the reduction in circuit size.
- FIG. 16 illustrates an example of application of the communication systems 1, 2, 3, and 4 according to the foregoing respective embodiments and modification examples thereof.
- the communication systems 1, 2, 3, and 4 according to the foregoing respective embodiments and modification examples thereof are applicable to data transmission from an image sensor IS to an application processor AP, as illustrated in Fig. 16 .
- the transmitter 1B is provided in the image sensor IS.
- the transmitter 1B corresponds to each of the transmitters 10 of the communication systems 1, 2, 3, and 4 according to the foregoing respective embodiments and modification examples thereof.
- the receiver 2B is provided in the application processor AP.
- the receiver 2B corresponds to each of the receivers 20 of the communication systems 1, 2, 3, and 4 according to the foregoing respective embodiments and modification examples thereof.
- the image sensor IS and the application processor AP are coupled to each other by the clock signal line 31 and the data signal line 32, or are coupled to each other only by the data signal line 32. Signal transmission via the clock signal line 31 and the data signal line 32 is made unidirectional.
- the image sensor IS and the application processor AP are coupled to each other by a bidirectional control bus 33.
- the control bus 33 may use an I 2 C (Inter-Integrated Circuit) interface or an I 3 C interface that is an extension version of the I 2 C interface.
- the application processor AP outputs, to the image sensor IS, a signal instructing transmission start with use of the control bus 35 (step S107).
- the application processor AP considers the image sensor IS to be in a mode in which communication is performed using both the LP signal and the HS differential signal to output the signal instructing transmission start to the image sensor IS with use of the control bus 35 (step S107).
- the image sensor IS starts transmitting the data signal upon reception of the signal instructing transmission start (step S108).
- FIG. 18 illustrates an appearance of a smartphone 300 (a multifunctional mobile phone) to which any of the communication systems according to the foregoing respective embodiments is applied.
- Various devices are mounted in the smartphone 300. Any of the communication systems according to the foregoing respective embodiments is applied to a communication system in which data are exchanged among these devices.
- the CPU 311 processes various pieces of information handled in the smartphone 300 in accordance with a program.
- the memory controller 312 controls a memory 501 to be used when the CPU 311 performs an information processing.
- the power source controller 313 controls a power source of the smartphone 300.
- the MIPI interface 318 transmits an image signal to the display 504.
- the image signal for example, a YUV-format signal, an RGB-format signal, or any other format signal is used.
- any of the communication systems according to the foregoing respective embodiments is applied to a communication system between the MIPI interface 318 and the display 504.
- vehicle-mounted cameras 401, 402, 403, and 404 are respectively mounted on the front (front), left, right, and rear (rear) of a vehicle 301, as illustrated in FIG. 21 .
- the vehicle-mounted cameras 401 to 404 are each coupled to an electrical control unit (ECU) 302 via an in-vehicle network.
- ECU electrical control unit
- An image capturing angle of the vehicle-mounted camera 401 mounted on the front of the vehicle 301 is within a range indicated by "a” in FIG. 21 , for example.
- An image capturing angle of the vehicle-mounted camera 402 is within a range indicated by "b” in FIG. 21 , for example.
- An image capturing angle of the vehicle-mounted camera 403 is within a range indicated by “c” in FIG. 21 , for example.
- An image capturing angle of the vehicle-mounted camera 404 is within a range indicated by "d” in FIG. 21 , for example.
- Each of the vehicle-mounted cameras 401 to 404 outputs a captured image to the ECU 302. This consequently makes it possible to capture a 360-degree (omnidirectional) image on the front, right, left, and rear of the vehicle 301 in the ECU 302.
- the DSP circuit 432 performs various image signal processings on an imaging signal outputted from the image sensor 431.
- the SerDes circuit 434 performs serial-parallel conversion of a signal, and includes, for example, a vehicle-mounted interface chip such as FPD-Link III.
- any of the communication systems according to the foregoing respective embodiments is applicable to, for example, a coupling interface 441 between the image sensor 431 and the DSP circuit 432. Moreover, any of the communication systems according to the foregoing respective embodiments is applicable to, for example, a coupling interface 442 between the image sensor 431 and the selector 433.
- the disclosure may have the following configurations.
Abstract
Description
- The disclosure relates to a communication system and a communication method that are applied to transmission of a data signal.
- In recent years, in association with increasing capacity of image data handled by mobile devices such as smartphones and camera devices, higher speed and lower power consumption of data transmission in a device or between different devices have been in demand. In order to meet such demands, standardization of high-speed interface specifications has been promoted, such as C-PHY specification and D-PHY specification that have been developed as coupling interface specifications for mobile devices and camera devices by the mobile industry processor interface (MIPI) alliance. The C-PHY specification and the D-PHY specification are interface specifications for communication protocol physical layers (physical layer: PHY). Moreover, a display serial interface (DSI) for a mobile device display or a camera serial interface (CSI) for a camera device is provided as an upper protocol layer of the C-PHY specification or the D-PHY specification.
PTL 1 proposes a technique that achieves stabilized signal transmission in the D-PHY specification. - PTL 1: Japanese Unexamined Patent Application Publication (Published Japanese Translation of
PCT Application) No. JP2014-522204 - In the C-PHY specification and the D-PHY specification described above, a high speed (High Speed: HS) differential signal is used for substantial transmission of a data signal. Further, a low power (Low Power: LP) signal is used in a blanking period of a clock signal and the data signal. The HS differential signal and the LP signal are transmitted on a common transmission path. For example, in the D-PHY specification, one transmission path (clock lane) where the clock signal is transmitted and one or a plurality of transmission paths (data lanes) where the data signal is transmitted are provided. A signal transmission period on each of the clock lane and the data lane includes a period in which transmission using the HS differential signal is performed and a period in which transmission using the LP signal is performed. On each of the clock lane and the data lane, the HS differential signal and the LP signal are transmitted on the common transmission path. However, the LP signal differs from the HS differential signal in a voltage value necessary for signal transmission. Hence, a circuit for transmission and reception of the HS differential signal and a circuit for transmission and reception of the LP signal are necessary independently, thus causing an issue of increased circuit size.
- Further, such an issue may also occur similarly in a communication system in which a voltage amplitude value varies depending on transmission modes in the transmission of a data signal.
- It is therefore desirable to provide a communication system and a communication method that make it possible to achieve reduction in circuit size, in the communication system in which a voltage amplitude value varies depending on transmission modes in transmission of a data signal.
- A communication system according to an embodiment of the disclosure includes a transmission device and a reception device. The transmission device outputs a clock signal with a clock frequency corresponding to a transmission mode, and outputs a data signal corresponding to the transmission mode. The reception device receives the clock signal and the data signal, and determines the transmission mode on a basis of magnitude of the clock frequency of the received clock signal.
- A communication method according to an embodiment of the disclosure includes (A) to (D) as follows:
- (A) outputting a clock signal with a clock frequency corresponding to a transmission mode;
- (B) outputting a data signal corresponding to the transmission mode;
- (C) receiving the clock signal and the data signal; and
- (D) determining the transmission mode on a basis of magnitude of the clock frequency of the received clock signal.
- In the communication system and the communication method according to the respective embodiments of the disclosure, a clock signal with a clock frequency corresponding to a transmission mode is outputted from the transmission device, and the transmission mode is determined in the reception device on the basis of magnitude of the clock frequency of the received clock signal. This eliminates necessity of preparing a driver circuit or a receiver circuit for each magnitude of amplitude voltage values as in the case of determining the transmission mode on the basis of the amplitude voltage values of the data signal.
- According to the communication system and the communication method of the respective embodiments of the disclosure, a clock signal with a clock frequency corresponding to a transmission mode is outputted from the transmission device, and the transmission mode is determined in the reception device on the basis of magnitude of the clock frequency of the received clock signal, thus making it possible to achieve reduction in circuit size in the communication system in which a voltage amplitude value varies depending on transmission modes in transmission of a data signal. It is to be noted that the effects of the disclosure are not necessarily limited to the effects described above, and may be any of the effects described in the specification.
-
- [
FIG. 1] FIG. 1 illustrates an overview of a communication system according to a first embodiment of the disclosure. - [
FIG. 2] FIG. 2 illustrates an example of a configuration of the communication system ofFIG. 1 . - [
FIG. 3] FIG. 3 illustrates an example of high-speed data transfer in a communication system ofFIG. 2 . - [
FIG. 4] FIG. 4 illustrates an example of low-speed data transfer in the communication system ofFIG. 2 . - [
FIG. 5] FIG. 5 illustrates a modification example of the configuration of the communication system ofFIG. 1 . - [
FIG. 6] FIG. 6 illustrates an example of low-speed data transfer in the communication system ofFIG. 5 . - [
FIG. 7] FIG. 7 illustrates a modification example of the configuration of the communication system ofFIG. 1 . - [
FIG. 8] FIG. 8 illustrates a modification example of the configuration of the communication system ofFIG. 1 . - [
FIG. 9] FIG. 9 illustrates an overview of a communication system according to a second embodiment of the disclosure. - [
FIG. 10] FIG. 10 illustrates an overview of a communication system according to a third embodiment of the disclosure. - [
FIG. 11] FIG. 11 illustrates an example of high-speed data transfer in the communication system ofFIG. 10 . - [
FIG. 12] FIG. 12 illustrates an example of low-speed data transfer in the communication system ofFIG. 10 . - [
FIG. 13] FIG. 13 illustrates an overview of a communication system according to a fourth embodiment of the disclosure. - [
FIG. 14] FIG. 14 illustrates an example of bidirectional communication in the communication system ofFIG. 10 . - [
FIG. 15] FIG. 15 illustrates an example of the bidirectional communication subsequent toFIG. 13 . - [
FIG. 16] FIG. 16 illustrates an application example of the above-described communication system. - [
FIG. 17] FIG. 17 illustrates an example of a data transmission processing in the application example illustrated inFIG. 16 . - [
FIG. 18] FIG. 18 illustrates an example of an appearance configuration of a smartphone to which the above-described communication system is applied. - [
FIG. 19] FIG. 19 illustrates a configuration example of an application processor to which the above-described communication system is applied. - [
FIG. 20] FIG. 20 illustrates a configuration example of an image sensor to which the above-described communication system is applied. - [
FIG. 21] FIG. 21 illustrates an installation example of a vehicle-mounted camera to which the above-described communication system is applied. - [
FIG. 22] FIG. 22 illustrates a configuration example in which the above-described communication system is applied to the vehicle-mounted camera. - Hereinafter, some embodiments of the disclosure are described in detail with reference to drawings. It is to be noted that the description is given in the following order.
- 1. First Embodiment
- 2. Modification Examples of First Embodiment
- 3. Second Embodiment
- 4. Third Embodiment
- 5. Fourth Embodiment
- 6. Application Examples
- First, description is given of a
communication system 1 according to a first embodiment of the disclosure.FIG. 1 illustrates an overview of thecommunication system 1. Thecommunication system 1 is applied to transmission of a data signal and a clock signal, and includes a transmitter 10 (a transmission device) and a receiver 20 (a reception device). Thecommunication system 1 includes a clock lane CL that straddles thetransmitter 10 and thereceiver 20 to transmit the clock signal and a data lane DL that straddles thetransmitter 10 and thereceiver 20 to transmit the data signal such as image data. It is to be noted that, whileFIG. 1 illustrates an example in which one data lane DL is provided, a plurality of data lanes DL may be provided. - The
transmitter 10 includes a digital transmitter circuit and an analog transmitter circuit. Thereceiver 20 includes a digital receiver circuit and an analog receiver circuit. For example, a 16-bit or 8-bit parallel signal is transmitted between the digital transmitter circuit and the analog transmitter circuit. Further, the 16-bit or 8-bit parallel signal is transmitted between the digital receiver circuit and the analog receiver circuit. In the clock lane CL, the analog transmitter circuit and the analog receiver circuit are coupled to each other by a clock signal line that transmits a differential clock signal. In the data lane DL, the analog transmitter circuit and the analog receiver circuit are coupled to each other by a data signal line that transmits a differential data signal. The clock signal line and the data signal line each include a pair of positive signal line Dp and a negative signal line Dn that transmit a differential signal. For example, a 1-bit serial signal is transmitted to each of the clock signal line and the data signal line. - The
transmitter 10 includes aclock transmitter circuit 110 and adata transmitter circuit 120. Thereceiver 20 includes aclock receiver circuit 210 and adata receiver circuit 220. In the clock lane CL, theclock transmitter circuit 110 and theclock receiver circuit 210 are coupled to each other by the above-described clock signal line. In the data lane DL, thedata transmitter circuit 120 and thedata receiver circuit 220 are coupled to each other by the above-described clock signal line. Theclock transmitter circuit 110 is a differential signal transmitter circuit that generates a differential clock signal as the clock signal and outputs the generated differential clock signal to the clock signal line. It is to be noted that theclock transmitter circuit 110 may be a ternary signal transmitter circuit that outputs a ternary level signal. Thedata transmitter circuit 120 is a differential signal transmitter circuit that generates a differential data signal as the data signal and outputs the generated differential data signal to the data signal line. It is to be noted that thedata transmitter circuit 120 may be the ternary signal transmitter circuit that outputs a ternary level signal. Theclock receiver circuit 210 is a differential signal receiver circuit that receives the differential clock signal as the clock signal via the clock signal line and performs a predetermined processing on the received differential clock signal. It is to be noted that theclock receiver circuit 210 may be a ternary signal receiver circuit that receives a ternary level signal. Thedata receiver circuit 220 is a differential signal receiver circuit that receives the differential data signal as the data signal via the data signal line and performs a predetermined processing on the received differential data signal. It is to be noted that thedata receiver circuit 220 may be the ternary signal receiver circuit that receives a ternary level signal. -
FIG. 2 illustrates an example of a configuration of thecommunication system 1. Thecommunication system 1 illustrated inFIG. 2 represents thecommunication system 1 illustrated inFIG. 1 by a functional block. - The
transmitter 10 includes, in the clock lane CL, atransmission mode controller 11, aclock generator 12, and aclock transmitter 13. Thetransmitter 10 includes, in the data lane DL, atransmission data generator 14 and adata transmitter 15. Thetransmission mode controller 11 decides a transmission mode in accordance with an instruction from an upper layer (e.g., a high-speed transmission control signal HS-TxCnt or a low-speed transmission control signal LS-TxCnt). Thetransmission mode controller 11 further performs a control corresponding to the decided transmission mode, on theclock generator 12 and thetransmission data generator 14. Theclock generator 12 generates a clock signal with a clock frequency Fc corresponding to a transmission mode in accordance with an instruction of thetransmission mode controller 11. Theclock generator 12 outputs the generated clock signal to theclock transmitter 13 and thetransmission data generator 14. Theclock transmitter 13 outputs the clock signal generated by theclock generator 12 to the clock signal line. In other words, theclock transmitter 13 outputs the clock signal generated by theclock generator 12 to aclock receiver 21 via the clock signal line. - The
transmission data generator 14 performs, in accordance with the instruction of thetransmission mode controller 11, various processings such as communication protocol control, decoding of data inputted from an upper layer, insertion of a control command, and parallel serial conversion, on an inputted data signal (e.g., high-speed transmission data HS-TxData or low-speed transmission data LS-TxData), thereby generating a data signal. Thetransmission data generator 14 outputs the generated data signal to thedata transmitter 15. Thetransmission data generator 14 switches the above-described various processings in accordance with the instruction of thetransmission mode controller 11. Thedata transmitter 15 outputs the data signal generated by thetransmission data generator 14 to a data signal line. In other words, thedata transmitter 15 outputs the data signal generated by thetransmission data generator 14 to adata receiver 24 via the data signal line. - The
receiver 20 includes, in the clock lane CL, theclock receiver 21, aclock frequency determiner 22, and areception mode controller 23. Thereceiver 20 includes, in the data lane DL, thedata receiver 24 and a receiveddata interpreter 25. Theclock receiver 21 receives the clock signal outputted by theclock transmitter 13 via the clock signal line. Theclock receiver 21 outputs the received clock signal to theclock frequency determiner 22 and the receiveddata interpreter 25. Theclock frequency determiner 22 detects (or determines) the clock frequency Fc from the inputted clock signal. Theclock frequency determiner 22 outputs the clock frequency Fc obtained from the detection (or the determination) to thereception mode controller 23. Thereception mode controller 23 determines a transmission mode on the basis of a result of comparison between the received clock frequency Fc and one or a plurality of reference frequencies Fth. A circuit that performs determination of the transmission mode is configured by a typical pulse counter, etc., for example. Here, suppose that a high-speed mode having a relatively fast transmission speed and a low-speed mode having a relatively slow transmission speed are set as the transmission modes. In this situation, when the clock frequency Fc is higher than the predetermined reference frequency Fth, thereception mode controller 23 determines that the transmission mode is in the high-speed mode. When the clock frequency Fc is lower than the predetermined reference frequency Fth, thereception mode controller 23 determines that the transmission mode is in the low-speed mode. Thereception mode controller 23 outputs information on the transmission mode obtained through the determination to the receiveddata interpreter 25. - The
data receiver 24 receives the data signal outputted from thedata transmitter 15 via the data signal line. Thedata receiver 24 outputs the received data signal to the receiveddata interpreter 25. The receiveddata interpreter 25 performs various processings such as serial parallel conversion, detection of a control command, decoding of signal data, and communication protocol control, on an inputted data signal on the basis of an inputted clock signal and inputted information on the transmission mode, thereby generating a data signal and a reception state notification signal that are to be provided to a subsequent stage. The receiveddata interpreter 25 switches the above-described various processings in accordance with an instruction (transmission mode, etc.) from thereception mode controller 23. The receiveddata interpreter 25 outputs the generated data signal (e.g., high-speed reception data HS-RxData or low-speed reception data LS-RxData) and the generated reception state notification signal (a high-speed reception state notification signal HS-RxState or a low-speed reception state notification signal LS-RxState) to a circuit of a subsequent stage. -
FIG. 3 illustrates an example of high-speed data transfer in thecommunication system 1. Suppose that theclock frequency determiner 22 detects (or determines) that the clock frequency Fc is lower than the reference frequency Fth or that the clock signal is stopped. In this situation, thereception mode controller 23 determines that the transmission mode is in the "low-speed mode". In a case where the transmission mode is in the "low-speed mode", when there is no input of a data signal from thedata receiver 24, the receiveddata interpreter 25 outputs no data signal to the data lane DL. - Suppose that the
clock frequency determiner 22 detects (or determines) that the clock frequency Fc becomes higher than the reference frequency Fth. In this situation, thereception mode controller 23 determines that the transmission mode is making a transition from the "low-speed mode" to the "high-speed mode". It is to be noted that the transmission mode in this situation is handled as the "high-speed mode". In a case where the transmission mode is making a transition from the "low-speed mode" to the "high-speed mode", the receiveddata interpreter 25 observes the transition of the transmission mode on the basis of the clock signal from theclock receiver 21 and the data signal from thedata receiver 24. Specifically, the receiveddata interpreter 25 determines, on the basis of transition of a combination of the clock signal from theclock receiver 21 and the data signal from thedata receiver 24, whether the transmission mode is in the middle of actually making a transition from the "low-speed mode" to the "high-speed mode", or the transition from the "low-speed mode" to the "high-speed mode" has been completed to cause the transmission mode to be shifted to the "high-speed mode". In a case where the above-described transition of the combination indicates that the transmission mode has been shifted to the "high-speed mode" as a result, the receiveddata interpreter 25 determines that the transmission mode is in the "high-speed mode". In this situation, when a data signal is inputted from thedata receiver 24, the receiveddata interpreter 25 transfers, on the data lane DL, the inputted data signal at the "high-speed mode". - Suppose that the
clock frequency determiner 22 detects (or determines) that the clock frequency Fc becomes lower than the reference frequency Fth. In this situation, thereception mode controller 23 determines that the transmission mode is making a transition from the "high-speed mode" to the "low-speed mode". It is to be noted that the transmission mode in this situation is handled as the "low-speed mode". In a case where the transmission mode is making a transition from the "high-speed mode" to the "low-speed mode", the receiveddata interpreter 25 observes the transition of the transmission mode on the basis of the clock signal from theclock receiver 21 and the data signal from thedata receiver 24. Specifically, the receiveddata interpreter 25 determines, on the basis of the transition of the combination of the clock signal from theclock receiver 21 and the data signal from thedata receiver 24, whether the transmission mode is in the middle of actually making a transition from the "high-speed mode" to the "low-speed mode", or the transition from the "high-speed mode" to the "low-speed mode" has been completed to cause the transmission mode to be shifted to the "low-speed mode". In a case where the above-described transition of the combination indicates that the transmission mode has been shifted to the "low-speed mode" as a result, the receiveddata interpreter 25 determines that the transmission mode is in the "low-speed mode". In this situation, when there is no input of a data signal from thedata receiver 24, the receiveddata interpreter 25 outputs no data signal to the data lane DL. -
FIG. 4 illustrates an example of low-speed data transfer in thecommunication system 1. Suppose that theclock frequency determiner 22 detects (or determines) that the clock frequency Fc is lower than the reference frequency Fth or that the clock signal is stopped. In this situation, thereception mode controller 23 determines that the transmission mode is in the "low-speed mode". In a case where the transmission mode is in the "low-speed mode", when there is no input of a data signal from thedata receiver 24, the receiveddata interpreter 25 outputs no data signal to the data lane DL. In a case where the transmission mode is in the "low-speed mode", when there is an input of a data signal from thedata receiver 24, the receiveddata interpreter 25 transfers, on the data lane DL, the inputted data signal at the "low-speed mode". - Description is given next of effects of the
communication system 1 of the present embodiment. - A communication system in which a voltage amplitude value varies depending on transmission modes in transmission of a data signal has been utilized. In such a communication system, types of transmission modes have been determined by detecting the voltage amplitude value. However, such a determination method involves preparing a driver circuit or a receiver circuit for each magnitude of amplitude voltage values, causing an issue in which a circuit size is likely to be increased.
- In the
communication system 1 of the present embodiment, however, a clock signal with the clock frequency Fc corresponding to a transmission mode is outputted from thetransmitter 10, and the transmission mode is determined in thereceiver 20 on the basis of magnitude of the clock frequency Fc of the received clock signal. This eliminates the necessity of preparing a circuit that detects the amplitude voltage value for each magnitude of the amplitude voltage values as in the case of determining the transmission mode on the basis of the amplitude voltage values of the data signal. This therefore makes it possible to achieve reduction in circuit size in the communication system in which the voltage amplitude value varies depending on transmission modes in the transmission of the data signal. - Further, in the present embodiment, the transmission mode is determined in the
receiver 20 on the basis of the result of the comparison between the clock frequency Fc and the one or a plurality of reference frequencies Fth. A circuit that performs such a determination may be configured by a typical pulse counter, etc. Accordingly, separately providing the circuit that performs such a determination does not prevent the reduction in circuit size. - Further, the
communication system 1 of the present embodiment is also applicable to the high-speed interface specifications (e.g., the C-PHY specification and the D-PHY specification). Accordingly, it is also possible, in such high-speed interface specifications, to achieve the reduction in circuit size. -
FIG. 5 illustrates a modification example of the configuration of thecommunication system 1 of the foregoing embodiment. In thecommunication system 1 illustrated inFIG. 5 , neither the low-speed transmission control signal LS-TxCnt nor the low-speed transmission data LS-TxData is inputted to thetransmitter 10. That is, thecommunication system 1 of the present modification example differs from the configuration of thecommunication system 1 of the foregoing embodiment in that neither the low-speed transmission control signal LS-TxCnt nor the low-speed transmission data LS-TxData is inputted from the upper layer. Further, in the communication system illustrated inFIG. 5 , neither the low-speed reception state notification signal LS-RxState nor the low-speed reception data LS-RxData is outputted from thereceiver 20. That is, thecommunication system 1 of the present modification example differs from the configuration of thecommunication system 1 of the foregoing embodiment in that neither the low-speed reception state notification signal LS-RxState nor the low-speed reception data LS-RxData is outputted to a subsequent stage of thecommunication system 1. Therefore, in the following, the low-speed data transfer is mainly described. -
FIG. 6 illustrates an example of low-speed data transfer in thecommunication system 1 of the present modification example. Suppose that theclock frequency determiner 22 detects (or determines) that the clock frequency Fc is lower than the reference frequency Fth or that the clock signal is stopped. In this situation, thereception mode controller 23 determines that the transmission mode is in the "low-speed mode". In a case where the transmission mode is in the "low-speed mode", when there is no input of a data signal from thedata receiver 24, the receiveddata interpreter 25 outputs no data signal to the data lane DL. In a case where the transmission mode is in the "low-speed mode", when there is an input of a data signal including a control command from thedata receiver 24, the receiveddata interpreter 25 transfers, on the data lane DL, the control command included in the inputted data signal at the "low-speed mode". It is to be noted that the control command is generated at thetransmission data generator 14 in thereceiver 10, and is not inputted from the upper layer. - Similarly to the foregoing embodiment, in the
communication system 1 of the present modification example, a clock signal with the clock frequency Fc corresponding to a transmission mode is outputted from thetransmitter 10, and the transmission mode is determined in thereceiver 20 on the basis of magnitude of the clock frequency Fc of the received clock signal. This therefore makes it possible to achieve reduction in circuit size in the communication system in which the voltage amplitude value varies depending on transmission modes in the transmission of the data signal. -
FIG. 7 illustrates a modification example of the configuration of thecommunication system 1 of the foregoing embodiment. Thecommunication system 1 illustrated inFIG. 7 includes a plurality of data lanes LD. Accordingly, thecommunication system 1 of the present modification example differs from the configuration of thecommunication system 1 of the foregoing embodiment in that the plurality of data lanes LD are provided. However, similarly to the foregoing embodiment, in thecommunication system 1 of the present modification example, a clock signal with the clock frequency Fc corresponding to a transmission mode is outputted from thetransmitter 10, and the transmission mode is determined in thereceiver 20 on the basis of magnitude of the clock frequency Fc of the received clock signal, in each of the data lanes DL. This therefore makes it possible to achieve reduction in circuit size in the communication system in which the voltage amplitude value varies depending on transmission modes in the transmission of the data signal. -
FIG. 8 illustrates a modification example of the configuration of thecommunication system 1 of the foregoing embodiment. Thecommunication system 1 illustrated inFIG. 8 includes, in the data lane LD, a plurality of data signal lines that each couple thetransmitter 10 and thereceiver 20 together and are each provided therebetween. Accordingly, thecommunication system 1 of the present modification example differs from the configuration of thecommunication system 1 of the foregoing embodiment in that it is possible to perform parallel transmission in the data lane LD. However, similarly to the foregoing embodiment, in thecommunication system 1 of the present modification example, a clock signal with the clock frequency Fc corresponding to a transmission mode is outputted from thetransmitter 10, and the transmission mode is determined in thereceiver 20 on the basis of magnitude of the clock frequency Fc of the received clock signal, in the data lane DL. This therefore makes it possible to achieve reduction in circuit size in the communication system in which the voltage amplitude value varies depending on transmission modes in the transmission of the data signal. - Description is given next of a
communication system 2 according to a second embodiment of the disclosure.FIG. 9 illustrates an overview of thecommunication system 2. Thecommunication system 2 is applied to transmission of the data signal and the clock signal, and includes the transmitter 10 (the transmission device) and the receiver 20 (the reception device). Thecommunication system 2 includes the data lane DL that straddles thetransmitter 10 and thereceiver 20 to transmit a superimposed signal in which the clock signal is superimposed on the data signal. That is, an embedded clock type serial IF is used in thecommunication system 2. - In the
communication system 2, thetransmitter 10 outputs to the data signal line the superimposed signal in which the clock signal is superimposed on the data signal. Thereceiver 20 receives the superimposed signal via the data signal line. Thetransmitter 10 is the differential signal transmitter circuit that outputs as the superimposed signal a differential superimposed signal, or the ternary signal transmitter circuit that outputs as the superimposed signal the ternary level signal. Thereceiver 20 is the differential signal receiver circuit that receives as the superimposed signal the differential superimposed signal, or the ternary signal receiver circuit that outputs as the superimposed signal the ternary level signal. - In the present embodiment, the
clock generator 12 outputs generated clock signal to thetransmission data generator 14. In accordance with the instruction of thetransmission mode controller 11, thetransmission data generator 14 superimposes the clock signal inputted from theclock generator 12 on inputted data signal (e.g., the high-speed transmission data HS-TxData or the low-speed transmission data LS-TxData) to thereby generate the superimposed signal. - Further, in the present embodiment, the
receiver 20 includes aclock extractor 26 instead of theclock receiver 21. Theclock extractor 26 accepts the superimposed signal from thedata receiver 24, and extracts the clock signal or clock information related to the clock signal out of the accepted superimposed signal. Theclock extractor 26 outputs the extracted clock signal or clock information to theclock frequency determiner 22. Theclock frequency determiner 22 detects (or determines) a clock frequency out of the inputted clock signal or clock information. - In the
communication system 2 of the present embodiment, the superimposed signal in which the clock signal with the clock frequency Fc corresponding to a transmission mode is superimposed on the signal data is outputted from thetransmitter 10, and the transmission mode is determined in thereceiver 20 on the basis of magnitude of the clock frequency Fc of the clock signal extracted from the received superimposed signal, in the data lane DL. This therefore makes it possible to achieve reduction in circuit size in the communication system in which the voltage amplitude value varies depending on transmission modes in the transmission of the data signal. - Further, in the present embodiment, the transmission mode is determined in the
receiver 20 on the basis of the result of the comparison between the clock frequency Fc and the one or a plurality of reference frequencies Fth. A circuit that performs such a determination may be configured by a typical pulse counter, etc. Accordingly, separately providing the circuit that performs such a determination does not prevent the reduction in circuit size. - Further, the
communication system 1 of the present embodiment is also applicable to the high-speed interface specifications (e.g., the C-PHY specification and the D-PHY specification). Accordingly, it is also possible, in such high-speed interface specifications, to achieve the reduction in circuit size. - Next, description is given of a
communication system 3 according to a third embodiment of the disclosure.FIG. 10 illustrates an overview of thecommunication system 3. Thecommunication system 3 is applied to transmission of the data signal and the clock signal, and includes the transmitter 10 (the transmission device) and the receiver 20 (the reception device). Thecommunication system 3 includes the clock lane CL that straddles thetransmitter 10 and thereceiver 20 to transmit the clock signal, and the data lane DL that straddles thetransmitter 10 and thereceiver 20 to transmit the data signal such as image data. It is to be noted that, whileFIG. 10 illustrates an example in which one data lane DL is provided, a plurality of data lanes DL may be provided. - In the present embodiment, the
clock receiver 21 includes a terminating resistance Rt (a second terminating resistance) coupled to the clock signal line, and a switching element that is able to turn ON/OFF coupling between the clock signal line and the terminating resistance Rt by a control signal Ter. Further, thedata receiver 24 includes a terminating resistance Rt (a first terminating resistance) coupled to the data signal, and a switching element that is able to turn ON/OFF coupling between the data signal line and the terminating resistance Rt by the control signal Ter. In a case where a predetermined command is included in the data signal, the receiveddata interpreter 25 outputs, as a received control command RxCom, the command to themode controller 23. In a case where the transmission mode is in the "low-speed mode", when the predetermined command is included in the data signal, thereception mode controller 23 turns ON the terminating resistance Rt (the first terminating resistance) and the terminating resistance Rt (the second terminating resistance). Specifically, in a case where the transmission mode is in the "low-speed mode", when there is an input of a control command that turns ON the terminating resistance Rt (the first terminating resistance) and the terminating resistance Rt (the second terminating resistance), as the received control command RxCom, thereception mode controller 23 turns ON the terminating resistance Rt (the first terminating resistance) and the terminating resistance Rt (the second terminating resistance). Further, in a case where the transmission mode is in the "low-speed mode", when a predetermined command is included in the data signal, thereception mode controller 23 turns OFF the terminating resistance Rt (the first terminating resistance) and the terminating resistance Rt (the second terminating resistance). Specifically, in a case where the transmission mode is in the "low-speed mode", when there is an input of a control command that turns OFF the terminating resistance Rt (the first terminating resistance) and the terminating resistance Rt (the second terminating resistance), as the received control command RxCom, thereception mode controller 23 turns OFF the terminating resistance Rt (the first terminating resistance) and the terminating resistance Rt (the second terminating resistance). -
FIG. 11 illustrates an example of high-speed data transfer in thecommunication system 3. Suppose that theclock frequency determiner 22 detects (or determines) that the clock frequency Fc is lower than the reference frequency Fth or that the clock signal is stopped. In this situation, thereception mode controller 23 determines that the transmission mode is in the "low-speed mode". In a case where the transmission mode is in the "low-speed mode", when there is no input of a data signal from thedata receiver 24, the receiveddata interpreter 25 outputs no data signal to the data lane DL. - Suppose that the
clock frequency determiner 22 detects (or determines) that the clock frequency Fc is lower than the reference frequency Fth. Further, suppose that there has been an input of the control command (the control command RxCom) that turns ON the terminating resistance Rt (the first terminating resistance) and the terminating resistance Rt (the second terminating resistance), as the received control command RxCom. In this situation, thereception mode controller 23 determines that the transmission mode is making a transition from the "low-speed mode" to the "high-speed mode". It is to be noted that the transmission mode in this situation is handled as the "low-speed mode". Further, thereception mode controller 23 causes the terminating resistance Rt (the first terminating resistance) and the terminating resistance Rt (the second terminating resistance) to be shifted from OFF to ON. - Suppose that the
clock frequency determiner 22 detects (or determines) that the clock frequency Fc becomes higher than the reference frequency Fth. In this situation, thereception mode controller 23 determines that the transmission mode is in the "high-speed mode". In a case where the transmission mode is in the "high-speed mode", when the data signal is inputted from thedata receiver 24, the receiveddata interpreter 25 transfers, on the data lane DL, the inputted data signal at the "high-speed mode". - Suppose that the
clock frequency determiner 22 detects (or determines) that the clock frequency Fc becomes lower than the reference frequency Fth. In this situation, thereception mode controller 23 determines that the transmission mode is making a transition from the "high-speed mode" to the "low-speed mode". It is to be noted that the transmission mode in this situation is handled as the "low-speed mode". In a case where the transmission mode is making a transition from the "high-speed mode" to the "low-speed mode", the receiveddata interpreter 25 observes the transition of the transmission mode on the basis of the clock signal from theclock receiver 21 and the data signal from thedata receiver 24. Specifically, the receiveddata interpreter 25 determines, on the basis of transition of a combination of the clock signal from theclock receiver 21 and the data signal from thedata receiver 24, whether the transmission mode is in the middle of actually making a transition from the "high-speed mode" to the "low-speed mode", or the transition from the "high-speed mode" to the "low-speed mode" has been completed to cause the transmission mode to be shifted to the "low-speed mode". - In a case where the above-described transition of the combination indicates that the transmission mode is in the middle of actually making a transition from the "high-speed mode" to the "low-speed mode" as a result, the received
data interpreter 25 determines that the transmission mode is in the middle of making the transition from the "high-speed mode" to the "low-speed mode". In this situation, suppose that there has been an input of the control command (the control command RxCom) that turns OFF the terminating resistance Rt (the first terminating resistance) and the terminating resistance Rt (the second terminating resistance). In this case, thereception mode controller 23 causes the terminating resistance Rt (the first terminating resistance) and the terminating resistance Rt (the second terminating resistance) to be shifted from ON to OFF. Meanwhile, in a case where the above-described transition of the combination indicates that the transmission mode has been shifted to the "low-speed mode", the receiveddata interpreter 25 determines that the transmission mode is in the "low-speed mode". In this situation, when there is no input of a data signal from thedata receiver 24, the receiveddata interpreter 25 outputs no data signal to the data lane DL. -
FIG. 12 illustrates an example of low-speed data transfer in thecommunication system 3. Suppose that theclock frequency determiner 22 detects (or determines) that the clock frequency Fc is lower than the reference frequency Fth or that the clock signal is stopped. In this situation, thereception mode controller 23 determines that the transmission mode is in the "low-speed mode". In a case where the transmission mode is in the "low-speed mode", when there is no input of a data signal from thedata receiver 24, the receiveddata interpreter 25 outputs no data signal to the data lane DL. - In a case where the transmission mode is in the "low-speed mode", when there is an input of a data signal including a control command from the
data receiver 24, the receiveddata interpreter 25 extracts the control command from the inputted data signal, and transfers, on the data lane DL, the extracted control command at the "low-speed mode. Further, in a case where the transmission mode is in the "low-speed mode", when there is an input of a data signal from thedata receiver 24, the receiveddata interpreter 25 transfers, on the data lane DL, the inputted data signal at the "low-speed mode". - Next, description is given of effects of the
communication system 3 of the present embodiment. In thecommunication system 3 of the present embodiment, a clock signal with the clock frequency Fc corresponding to a transmission mode is outputted from thetransmitter 10, and the transmission mode is determined in thereceiver 20 on the basis of magnitude of the clock frequency Fc of the received clock signal. This eliminates the necessity of preparing a driver circuit or a receiver circuit for each magnitude of amplitude voltage values as in the case of determining the transmission mode on the basis of the amplitude voltage values of the data signal. This therefore makes it possible to achieve reduction in circuit size in the communication system in which the voltage amplitude value varies depending on transmission modes in the transmission of the data signal. - Further, in the present embodiment, the transmission mode is determined in the
receiver 20 on the basis of the result of the comparison between the clock frequency Fc and the one or a plurality of reference frequencies Fth. A circuit that performs such a determination may be configured by a typical pulse counter, etc. Accordingly, even in a case of separately providing the circuit that performs such a determination, the reduction in circuit size is not prevented. - Further, the
communication system 3 of the present embodiment is also applicable to the high-speed interface specifications (e.g., the C-PHY specification and the D-PHY specification). Accordingly, separately providing the circuit that performs such a determination does not prevent the reduction in circuit size. - Further, in the present embodiment, in a case where the transmission mode is in the middle of making a transition from the "low-speed mode" to the "high-speed mode" (the transmission mode is handled as the "low-speed mode"), when a predetermined command is included in the data signal, the terminating resistance Rt (the first terminating resistance) and the terminating resistance Rt (the second terminating resistance) are turned ON. This causes a high-speed clock signal or data signal to be transmitted in such a state that the terminating resistance Rt (the first terminating resistance) and the terminating resistance Rt (the second terminating resistance) are turned ON. Hence, it is possible to suppress generation of unnecessary radiation.
- It is to be noted that, in the
communication system 2 of the foregoing second embodiment, thedata receiver 24 may include the terminating resistance Rt (the first terminating resistance) coupled to the data signal line, and the switching element that is able to turn ON/OFF coupling between the data signal line and the terminating resistance Rt by the control signal Ter. Further, in a case where the transmission mode is in the middle of making a transition from the "low-speed mode" to the "high-speed mode", when a predetermined command is included in the data signal, thereception mode controller 23 may turn ON the terminating resistance Rt (the first terminating resistance). Furthermore, in a case where the transmission mode is in the middle of making a transition from the "high-speed mode" to the "low-speed mode", when a predetermined command is included in the data signal, thereception mode controller 23 may turn OFF the terminating resistance Rt (the first terminating resistance). Even in this case, it is possible to suppress generation of unnecessary radiation. - Next, description is given of a
communication system 4 according to a fourth embodiment of the disclosure.FIG. 13 illustrates an overview of thecommunication system 4. Thecommunication system 4 is applied to transmission of the data signal and the clock signal, and includes a master 30 (a transmission device) and a slave 40 (a reception device). Thecommunication system 4 includes the clock lane CL that straddles themaster 30 and theslave 40 to transmit the clock signal, and the data lane DL that straddles themaster 30 and theslave 40 to transmit the data signal such as image data. It is to be noted that, whileFIG. 13 illustrates an example in which one data lane DL is provided, a plurality of data lanes DL may be provided. - In the present embodiment, the
master 30 is provided instead of thetransmitter 10 and theslave 40 is provided instead of thereceiver 20 in thecommunication system 3 of the foregoing third embodiment. Themaster 30 corresponds to thetransmitter 10 of the foregoing third embodiment that further includes adata receiver 16 and a receiveddata interpreter 17. In themaster 30, thetransmission mode controller 11 exchanges, with an upper layer, signals (a transmission direction notification signal TraAna and a transmission direction switch signal TraChan) that control a communication direction. Further, thetransmission mode controller 11 outputs, to thetransmission data generator 14, a control command TxCom to be transmitted. - The
data receiver 16 receives a data signal outputted from adata transmitter 28 via the data signal line. Thedata receiver 16 outputs the received data signal to the receiveddata interpreter 17. The receiveddata interpreter 17 performs various processings such as serial parallel conversion, detection of a control command, decoding of signal data, and communication protocol control, on an inputted data signal on the basis of an inputted clock signal and inputted information on the transmission mode, thereby generating a data signal (the low-speed reception data LS-RxData) and the control command RxCom that are to be provided to a preceding stage. The receiveddata interpreter 17 outputs the generated data signal (e.g., the low-speed reception data LS-RxData) to a circuit of a preceding stage, and outputs the control command RxCom to thetransmission mode controller 11. - The
slave 40 corresponds to thereceiver 20 of the foregoing third embodiment that further includes atransmission data generator 27 and thedata transmitter 28. In theslave 40, thereception mode controller 23 exchanges, with an upper layer, signals (the transmission direction notification signal TraAna and the transmission direction switch signal TrChan) that control a communication direction. Further, thereception mode controller 23 outputs, to thetransmission data generator 27, the control command TxCom to be transmitted. - The
transmission data generator 27 performs, in accordance with an instruction of thereception mode controller 23, various processings such as communication protocol control, decoding of data inputted from an upper layer, insertion of a control command, and parallel serial conversion, on an inputted data signal (the low-speed transmission data LS-TxData), thereby generating a data signal. Thetransmission data generator 27 outputs the generated data signal to thedata transmitter 28. Thedata transmitter 28 outputs the data signal generated by thetransmission data generator 27 to the data signal line. In other words, thedata transmitter 28 outputs the data signal generated by thetransmission data generator 27 to thedata receiver 16 via the data signal line. -
FIGs. 14 and15 illustrate an example of bidirectional communication in thecommunication system 4.FIG. 15 illustrates an example of the communication subsequent toFIG. 14 . Suppose that the transmission direction switch signal TraChan is inputted from an upper layer on side of themaster 30. Thetransmission mode controller 11 then outputs, to thetransmission data generator 14, the transmission direction switch signal TraChan as the control command TxCom to be transmitted. Thetransmission data generator 14 generates a data signal including the inputted transmission direction switch signal TraChan, and outputs the generated data signal to thedata transmitter 15. Thedata transmitter 15 outputs the inputted data signal to thedata receiver 24 via the data signal line at the "low-speed mode". Thedata receiver 24 outputs the inputted data signal to the receiveddata interpreter 25. Upon extracting the transmission direction switch signal TraChan included in the inputted data signal, the receiveddata interpreter 25 outputs, to thereception mode controller 23, the extracted transmission direction switch signal TraChan as the received control command RxCom. When the transmission direction switch signal TraChan is inputted as the control command RxCom, thereception mode controller 23 outputs, to an upper layer on side of theslave 40, the transmission direction switch signal TraChan as the transmission direction notification signal TraAna. - Further, the
reception mode controller 23 outputs to the transmission data generator 27 a response to the effect that an input of the transmission direction switch signal TraChan has been accepted. Specifically, thereception mode controller 23 outputs to the transmission data generator 27 a signal (hereinafter, referred to as an "acceptance signal") indicating that the input of the transmission direction switch signal TraChan has been accepted, as the control command TxCom to be transmitted. Thetransmission data generator 27 generates a data signal including the inputted acceptance signal, and outputs the generated data signal to thedata transmitter 28. Thedata transmitter 28 outputs the inputted data signal to thedata receiver 16 via the data signal line at the "low-speed mode". Thedata receiver 16 outputs the inputted data signal to the receiveddata interpreter 17. Upon extracting the acceptance signal included in the inputted data signal, the receiveddata interpreter 17 outputs, to thetransmission mode controller 11, the extracted acceptance signal as the received control command RxCom. When the acceptance signal is inputted as the control command RxCom, thetransmission mode controller 11 outputs, to the upper layer on side of themaster 30, the acceptance signal as a response to the effect that transmission direction switching has been completed and as the transmission direction notification signal TraAna. In this manner, the transmission direction switching is performed. - Thereafter, when the data signal (the low-speed transmission data LS-TxData) is inputted from the upper layer, etc., the
transmission data generator 27 performs a predetermined processing on the data signal to thereby generate a data signal to be transmitted. Thetransmission data generator 27 outputs the generated data signal to thedata transmitter 28. Thedata transmitter 28 outputs the inputted data signal to thedata receiver 16 via the data signal line at the "low-speed mode". Thedata receiver 16 outputs the inputted data signal to the receiveddata interpreter 17. The receiveddata interpreter 17 outputs, to the upper layer, the inputted data signal as the low-speed reception data LS-RxData. In this manner, data transmission from theslave 40 to themaster 30 is performed. - After the data transmission from the
slave 40 to themaster 30 has been completed, transmission direction switching (TurnAround processing) is performed through a procedure reverse to that of the foregoing. Suppose that the transmission direction switch signal TraChan is inputted from the upper layer on side of theslave 40. Thereception mode controller 23 then outputs, to thetransmission data generator 27, the transmission direction switch signal TraChan as the control command TxCom to be transmitted. Thetransmission data generator 27 generates a data signal including the inputted transmission direction switch signal TraChan, and outputs the generated data signal to thedata transmitter 28. Thedata transmitter 28 outputs the inputted data signal to thedata receiver 16 via the data signal line at the "low-speed mode". Thedata receiver 16 outputs the inputted data signal to the receiveddata interpreter 17. Upon extracting the transmission direction switch signal TraChan included in the inputted data signal, the receiveddata interpreter 17 outputs, to thetransmission mode controller 11, the extracted transmission direction switch signal TraChan as the received control command RxCom. When the transmission direction switch signal TraChan is inputted as the control command RxCom, thetransmission mode controller 11 outputs, to the upper layer on side of themaster 30, the transmission direction switch signal TraChan as the transmission direction notification signal TraAna. - Further, the
transmission mode controller 11 outputs to the transmission data generator 14 a response to the effect that an input of the transmission direction switch signal TraChan has been accepted. Specifically, thereception mode controller 23 outputs to the transmission data generator 14 a signal indicating that the input of the transmission direction switch signal TraChan has been accepted (hereinafter, referred to as an "acceptance signal"), as the control command TxCom to be transmitted. Thetransmission data generator 14 generates a data signal including the inputted acceptance signal, and outputs the generated data signal to thedata transmitter 15. Thedata transmitter 15 outputs the inputted data signal to thedata receiver 24 via the data signal line at the "low-speed mode". Thedata receiver 24 outputs the inputted data signal to the receiveddata interpreter 25. Upon extracting the acceptance signal included in the inputted data signal, the receiveddata interpreter 25 outputs, to thereception mode controller 23, the extracted acceptance signal as the received control command RxCom. When the acceptance signal is inputted as the control command RxCom, thereception mode controller 23 outputs, to the upper layer on side of theslave 40, the acceptance signal as a response to the effect that the transmission direction switching has been completed and as the transmission direction notification signal TraAna. In this manner, the transmission direction is returned to the original direction. - In the
communication system 4 of the present embodiment, similarly to the foregoing embodiments, a clock signal with the clock frequency Fc corresponding to a transmission mode is outputted from themaster 30, and the transmission mode is determined in theslave 40 on the basis of magnitude of the clock frequency Fc of the received clock signal. This eliminates the necessity of preparing a driver circuit or a receiver circuit for each magnitude of amplitude voltage values as in the case of determining the transmission mode on the basis of the amplitude voltage values of the data signal. This therefore makes it possible to achieve reduction in circuit size in the communication system in which the voltage amplitude value varies depending on transmission modes in the transmission of the data signal. - Further, in the present embodiment, the transmission mode is determined in the
slave 40 on the basis of the result of the comparison between the clock frequency Fc and the one or a plurality of reference frequencies Fth. A circuit that performs such a determination may be configured by a typical pulse counter, etc. Accordingly, even in a case of separately providing the circuit that performs such a determination, the reduction in circuit size is not prevented. - Further, the
communication system 4 of the present embodiment is also applicable to the high-speed interface specifications (e.g., the C-PHY specification and the D-PHY specification). Accordingly, it is possible, even in such high-speed interface specifications, to achieve the reduction in circuit size. - In the following, description is given of application examples of the
communication systems -
FIG. 16 illustrates an example of application of thecommunication systems communication systems Fig. 16 . Thetransmitter 1B is provided in the image sensor IS. Thetransmitter 1B corresponds to each of thetransmitters 10 of thecommunication systems receiver 2B is provided in the application processor AP. Thereceiver 2B corresponds to each of thereceivers 20 of thecommunication systems - The image sensor IS and the application processor AP are coupled to each other by a
bidirectional control bus 33. Thecontrol bus 33 may use an I2C (Inter-Integrated Circuit) interface or an I3C interface that is an extension version of the I2C interface. -
FIG. 17 illustrates an example of a data transmission processing in a device including the image sensor IS and the application processor AP illustrated inFIG. 16 . - When the device including the image sensor IS and the application processor AP is powered on (step S101), the application processor AP reads a register setting of the image sensor IS with use of the control bus 33 (step S102). This allows the application processor AP to determine whether the image sensor IS corresponds to communication without an LP signal (step S103). In other words, determination is made whether the image sensor IS corresponds to a mode in which communication using only an HS differential signal without using the LP signal is performed or a mode in which communication using both the LP signal and the HS differential signal is performed. In a case where determination is made that the image sensor IS corresponds to communication without the LP signal (step S103; Y), the application processor AP transmits a setting for validating communication without the LP signal to the image sensor IS with use of the control bus 35 (step S104).
- Next, the application processor AP determines whether the application processor AP corresponds to a new LPDT communication (step S105). In a case where determination is made that the application processor AP corresponds to the new LPDT communication (e.g., the communication according to an embodiment of the disclosure) (step S105; Y), the application processor AP transmits a setting for validating the new LPDT communication to the image sensor IS with use of the control bus 35 (step S106).
- Next, the application processor AP outputs, to the image sensor IS, a signal instructing transmission start with use of the control bus 35 (step S107). In a case where determination is made that the image sensor IS does not correspond to the communication without the LP signal (step S103; N), the application processor AP considers the image sensor IS to be in a mode in which communication is performed using both the LP signal and the HS differential signal to output the signal instructing transmission start to the image sensor IS with use of the control bus 35 (step S107). Next, the image sensor IS starts transmitting the data signal upon reception of the signal instructing transmission start (step S108).
-
FIG. 18 illustrates an appearance of a smartphone 300 (a multifunctional mobile phone) to which any of the communication systems according to the foregoing respective embodiments is applied. Various devices are mounted in the smartphone 300. Any of the communication systems according to the foregoing respective embodiments is applied to a communication system in which data are exchanged among these devices. -
FIG. 19 illustrates a configuration example of anapplication processor 310 to be used in the smartphone 300. Theapplication processor 310 includes a central processing unit (CPU) 311, amemory controller 312, apower source controller 313, anexternal interface 314, a graphics processing unit (GPU) 315, amedia processor 316, adisplay controller 317, and anMIPI interface 318. In this example, theCPU 311, thememory controller 312, thepower source controller 313, theexternal interface 314, theGPU 315, themedia processor 316, and thedisplay controller 317 are each coupled to asystem bus 319 to allow for data exchange with one another via thesystem bus 319. - The
CPU 311 processes various pieces of information handled in the smartphone 300 in accordance with a program. Thememory controller 312 controls amemory 501 to be used when theCPU 311 performs an information processing. Thepower source controller 313 controls a power source of the smartphone 300. - The
external interface 314 is an interface for communication with external devices. In this example, theexternal interface 314 is coupled to awireless communication section 502 and to animage sensor 410. Thewireless communication section 502 performs wireless communication with mobile phone base stations. Thewireless communication section 502 includes, for example, a baseband section, a radio frequency (RF) front end section, and other components. Theimage sensor 410 acquires an image, and includes, for example, a CMOS sensor. - The
GPU 315 performs an image processing. Themedia processor 316 processes information such as voice, characters, and graphics. Thedisplay controller 317 controls adisplay 504 via theMIPI interface 318. - The
MIPI interface 318 transmits an image signal to thedisplay 504. As the image signal, for example, a YUV-format signal, an RGB-format signal, or any other format signal is used. For example, any of the communication systems according to the foregoing respective embodiments is applied to a communication system between theMIPI interface 318 and thedisplay 504. -
FIG. 20 illustrates a configuration example of theimage sensor 410. Theimage sensor 410 includes asensor section 411, an image signal processor (ISP) 412, a joint photographic experts group (JPEG)encoder 413, aCPU 414, a random access memory (RAM) 415, a read only memory (ROM) 416, apower source controller 417, an inter-integrated circuit (I2C)interface 418, and anMIPI interface 419. In this example, these blocks are coupled to asystem bus 420 to allow for data exchange with one another via thesystem bus 420. - The
sensor section 411 acquires an image, and includes, for example, a CMOS sensor. TheISP 412 performs a predetermined processing on the image acquired by thesensor section 411. TheJPEG encoder 413 encodes the image processed by theISP 412 to generate a JPEG-format image. TheCPU 414 controls respective blocks of theimage sensor 410 in accordance with a program. TheRAM 415 is a memory to be used when theCPU 414 performs an information processing. TheROM 416 stores a program to be executed in theCPU 414. Thepower source controller 417 controls a power source of theimage sensor 410. The I2C interface 418 receives a control signal from theapplication processor 310. Although not illustrated, theimage sensor 410 also receives a clock signal from theapplication processor 310, in addition to the control signal. Specifically, theimage sensor 410 is configured to be operable on the basis of clock signals with various frequencies. - The
MIPI interface 419 transmits an image signal to theapplication processor 310. As the image signal, for example, a YUV-format signal, an RGB-format signal, or any other format signal is used. For example, any of the communication systems according to the foregoing respective embodiments is applied to a communication system between theMIPI interface 419 and theapplication processor 310. -
FIG. 21 and FIG. 22 each illustrate a configuration example of a vehicle-mounted camera as an application example to an imaging device.FIG. 21 illustrates an installation example of the vehicle-mounted camera, andFIG. 22 illustrates an internal configuration example of the vehicle-mounted camera. - For example, vehicle-mounted
cameras vehicle 301, as illustrated inFIG. 21 . The vehicle-mountedcameras 401 to 404 are each coupled to an electrical control unit (ECU) 302 via an in-vehicle network. - An image capturing angle of the vehicle-mounted
camera 401 mounted on the front of thevehicle 301 is within a range indicated by "a" inFIG. 21 , for example. An image capturing angle of the vehicle-mountedcamera 402 is within a range indicated by "b" inFIG. 21 , for example. An image capturing angle of the vehicle-mountedcamera 403 is within a range indicated by "c" inFIG. 21 , for example. An image capturing angle of the vehicle-mountedcamera 404 is within a range indicated by "d" inFIG. 21 , for example. Each of the vehicle-mountedcameras 401 to 404 outputs a captured image to theECU 302. This consequently makes it possible to capture a 360-degree (omnidirectional) image on the front, right, left, and rear of thevehicle 301 in theECU 302. - For example, each of the vehicle-mounted
cameras 401 to 404 includes animage sensor 431, a digital signal processing (DSP)circuit 432, aselector 433, and a serializer-deserializer (SerDes)circuit 434, as illustrated inFIG. 22 . - The
DSP circuit 432 performs various image signal processings on an imaging signal outputted from theimage sensor 431. TheSerDes circuit 434 performs serial-parallel conversion of a signal, and includes, for example, a vehicle-mounted interface chip such as FPD-Link III. - The
selector 433 selects whether to output the imaging signal outputted from theimage sensor 431 via theDSP circuit 432 or not via theDSP circuit 432. - Any of the communication systems according to the foregoing respective embodiments is applicable to, for example, a
coupling interface 441 between theimage sensor 431 and theDSP circuit 432. Moreover, any of the communication systems according to the foregoing respective embodiments is applicable to, for example, acoupling interface 442 between theimage sensor 431 and theselector 433. - Although the disclosure has been described above referring to the plurality of embodiments and the modification examples thereof, the disclosure is not limited to the foregoing embodiments, etc., and may be modified in a variety of ways. It is to be noted that effects described herein are merely illustrative. The effects of the disclosure are not limited to those described in the specification. The disclosure may have effects other than those described in the specification.
- Further, for example, the disclosure may have the following configurations.
- (1) A communication system including:
- a transmission device that outputs a clock signal with a clock frequency corresponding to a transmission mode, and outputs a data signal corresponding to the transmission mode; and
- a reception device that receives the clock signal and the data signal, and determines the transmission mode on a basis of magnitude of the clock frequency of the received clock signal.
- (2) The communication system according to (1), in which the reception device determines the transmission mode on a basis of a result of comparison between the clock frequency and one or a plurality of reference frequencies.
- (3) The communication system according to (1) or (2), in which the reception device determines the transmission mode to be in a high-speed mode when the clock frequency is higher than a predetermined one of the one or a plurality of reference frequencies, and determines the transmission mode to be in a low-speed mode when the clock frequency is lower than the predetermined one of the one or a plurality of reference frequencies.
- (4) The communication system according to any one of (1) to (3), in which
the transmission device outputs the clock signal to a clock signal line and outputs the data signal to a data signal line, and
the reception device receives the clock signal via the clock signal line and receives the data signal via the data signal line. - (5) The communication system according to any one of (1) to (4), in which
the transmission device includes a differential signal transmitter circuit that outputs a differential clock signal as the clock signal and outputs a differential data signal as the data signal, and
the reception device includes a differential signal receiver circuit that receives the differential clock signal as the clock signal and receives a differential data signal as the data signal. - (6) The communication system according to (4) or (5), in which
the reception device includes a first terminating resistance coupled to the data signal line and a second terminating resistance coupled to the clock signal line, and
the reception device turns ON the first terminating resistance and the second terminating resistance when a predetermined command is included in the data signal in a case where the transmission mode is in the low-speed mode. - (7) The communication system according to any one of (1) to (3), in which
the transmission device outputs to a data signal line a superimposed signal in which the clock signal is superimposed on the data signal, and
the reception device receives the superimposed signal via the data signal line. - (8) The communication system according to (7), in which
the transmission device includes a differential signal transmitter circuit that outputs a differential superimposed signal as the superimposed signal, and
the reception device includes a differential signal receiver circuit that receives the differential superimposed signal as the superimposed signal. - (9) The communication system according to (7) or (8), in which
the reception device includes a terminating resistance coupled to the data signal line, and
the reception device turns ON the terminating resistance when a predetermined command is included in the superimposed signal. - (10) A communication method including:
- outputting a clock signal with a clock frequency corresponding to a transmission mode,
- outputting a data signal corresponding to the transmission mode;
- receiving the clock signal and the data signal; and
- This application claims the benefit of Japanese Priority Patent Application
JP2015-242503 - It should be understood by those skilled in the art that various modifications, combinations, sub-combinations, and alterations may occur depending on design requirements and other factors insofar as they are within the scope of the appended claims or the equivalents thereof.
Claims (10)
- A communication system comprising:a transmission device that outputs a clock signal with a clock frequency corresponding to a transmission mode, and outputs a data signal corresponding to the transmission mode; anda reception device that receives the clock signal and the data signal, and determines the transmission mode on a basis of magnitude of the clock frequency of the received clock signal.
- The communication system according to claim 1, wherein the reception device determines the transmission mode on a basis of a result of comparison between the clock frequency and one or a plurality of reference frequencies.
- The communication system according to claim 2, wherein the reception device determines the transmission mode to be in a high-speed mode when the clock frequency is higher than a predetermined one of the one or a plurality of reference frequencies, and determines the transmission mode to be in a low-speed mode when the clock frequency is lower than the predetermined one of the one or a plurality of reference frequencies.
- The communication system according to claim 3, wherein
the transmission device outputs the clock signal to a clock signal line and outputs the data signal to a data signal line, and
the reception device receives the clock signal via the clock signal line and receives the data signal via the data signal line. - The communication system according to claim 4, wherein
the transmission device comprises a differential signal transmitter circuit that outputs a differential clock signal as the clock signal and outputs a differential data signal as the data signal, and
the reception device comprises a differential signal receiver circuit that receives the differential clock signal as the clock signal and receives a differential data signal as the data signal. - The communication system according to claim 4, wherein
the reception device includes a first terminating resistance coupled to the data signal line and a second terminating resistance coupled to the clock signal line, and
the reception device turns ON the first terminating resistance and the second terminating resistance when a predetermined command is included in the data signal in a case where the transmission mode is in the low-speed mode. - The communication system according to claim 3, wherein
the transmission device outputs to a data signal line a superimposed signal in which the clock signal is superimposed on the data signal, and
the reception device receives the superimposed signal via the data signal line. - The communication system according to claim 7, wherein
the transmission device comprises a differential signal transmitter circuit that outputs a differential superimposed signal as the superimposed signal, and
the reception device comprises a differential signal receiver circuit that receives the differential superimposed signal as the superimposed signal. - The communication system according to claim 7, wherein
the reception device includes a terminating resistance coupled to the data signal line, and
the reception device turns ON the terminating resistance when a predetermined command is included in the superimposed signal. - A communication method comprising:outputting a clock signal with a clock frequency corresponding to a transmission mode,outputting a data signal corresponding to the transmission mode;receiving the clock signal and the data signal; anddetermining the transmission mode on a basis of magnitude of the clock frequency of the received clock signal.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2015242503 | 2015-12-11 | ||
PCT/JP2016/083911 WO2017098871A1 (en) | 2015-12-11 | 2016-11-16 | Communication system and communication method |
Publications (2)
Publication Number | Publication Date |
---|---|
EP3389215A4 EP3389215A4 (en) | 2018-10-17 |
EP3389215A1 true EP3389215A1 (en) | 2018-10-17 |
Family
ID=59014014
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP16872771.7A Withdrawn EP3389215A1 (en) | 2015-12-11 | 2016-11-16 | Communication system and communication method |
Country Status (5)
Country | Link |
---|---|
US (1) | US10739812B2 (en) |
EP (1) | EP3389215A1 (en) |
JP (1) | JP6763398B2 (en) |
CN (1) | CN108292990B (en) |
WO (1) | WO2017098871A1 (en) |
Families Citing this family (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI705666B (en) * | 2015-06-15 | 2020-09-21 | 日商新力股份有限公司 | Transmission device, receiving device, communication system |
US11038665B2 (en) * | 2017-08-02 | 2021-06-15 | Sony Semiconductor Solutions Corporation | Transmission apparatus and communication system |
DE102017217051A1 (en) * | 2017-09-26 | 2019-03-28 | Spinner Gmbh | Apparatus and method for transferring data between two physical interfaces |
US10715389B2 (en) * | 2018-08-29 | 2020-07-14 | Dell Products L.P. | Automatic controller configuration system |
CN113348654A (en) * | 2019-01-28 | 2021-09-03 | 索尼半导体解决方案公司 | Transmission device, transmission method, reception device, reception method, and transmission/reception device |
CN110334044B (en) * | 2019-05-29 | 2022-05-20 | 深圳市紫光同创电子有限公司 | MIPI DPHY transmitting circuit and equipment |
JP6896030B2 (en) * | 2019-08-20 | 2021-06-30 | 三菱電機株式会社 | In-vehicle camera device |
US11023409B2 (en) * | 2019-10-03 | 2021-06-01 | Qualcomm Incorporated | MIPI D-PHY receiver auto rate detection and high-speed settle time control |
CN113345359A (en) * | 2020-03-03 | 2021-09-03 | 硅工厂股份有限公司 | Data processing apparatus for driving display apparatus, data driving apparatus and system |
US20230336323A1 (en) * | 2020-09-04 | 2023-10-19 | Sony Semiconductor Solutions Corporation | Sensor device, reception device, and transmission/reception system |
CN112291126A (en) * | 2020-10-23 | 2021-01-29 | 成都天锐星通科技有限公司 | Bus communication system, data transmission method and data reception method |
CN114286034A (en) * | 2021-12-23 | 2022-04-05 | 南昌虚拟现实研究院股份有限公司 | MIPI resistor network system and method |
Family Cites Families (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001308940A (en) | 2000-04-26 | 2001-11-02 | Sharp Corp | Communication speed changeover device |
JP2005354271A (en) | 2004-06-09 | 2005-12-22 | Seiko Epson Corp | Semiconductor device, clock phase adjustment circuit, transmission circuit, and reception circuit |
US20060120296A1 (en) * | 2004-12-02 | 2006-06-08 | Goh Ban H | Auto mode detection for a switch |
JP2007049217A (en) | 2005-08-05 | 2007-02-22 | Matsushita Electric Ind Co Ltd | Network system |
JP5019419B2 (en) * | 2006-07-07 | 2012-09-05 | ルネサスエレクトロニクス株式会社 | Display data receiving circuit and display panel driver |
US8279769B2 (en) * | 2006-09-18 | 2012-10-02 | St-Ericsson Sa | Mode switching of a data communications link |
US8107575B2 (en) * | 2007-05-03 | 2012-01-31 | Fairchild Semiconductor Corporation | Method and circuit for changing modes without dedicated control pin |
US8149972B2 (en) * | 2007-05-30 | 2012-04-03 | Rambus Inc. | Signaling with superimposed clock and data signals |
WO2009058790A1 (en) * | 2007-10-30 | 2009-05-07 | Rambus Inc. | Signaling with superimposed differential-mode and common-mode signals |
ATE478474T1 (en) * | 2007-12-11 | 2010-09-15 | Swatch Group Res & Dev Ltd | DUAL MODE COUNTER DISTRIBUTION CIRCUIT FOR HIGH FREQUENCY OPERATION |
JPWO2009118851A1 (en) * | 2008-03-27 | 2011-07-21 | パイオニア株式会社 | Content transmission device |
JP4666030B2 (en) | 2008-09-03 | 2011-04-06 | ソニー株式会社 | Information processing apparatus and signal determination method |
JP6126600B2 (en) | 2011-08-16 | 2017-05-10 | シリコン・ライン・ゲー・エム・ベー・ハー | Circuit apparatus and method for transmitting signals |
US9755818B2 (en) * | 2013-10-03 | 2017-09-05 | Qualcomm Incorporated | Method to enhance MIPI D-PHY link rate with minimal PHY changes and no protocol changes |
JP6298629B2 (en) | 2013-12-24 | 2018-03-20 | 株式会社メガチップス | Data receiver |
US9606954B2 (en) * | 2014-01-10 | 2017-03-28 | Lattice Semiconductor Corporation | Communicating with MIPI-compliant devices using non-MIPI interfaces |
JP2015177364A (en) * | 2014-03-14 | 2015-10-05 | シナプティクス・ディスプレイ・デバイス合同会社 | Receiver circuit, display panel driver, display device, and operation method of receiver circuit |
-
2016
- 2016-11-16 CN CN201680070597.4A patent/CN108292990B/en not_active Expired - Fee Related
- 2016-11-16 US US15/772,253 patent/US10739812B2/en active Active
- 2016-11-16 WO PCT/JP2016/083911 patent/WO2017098871A1/en active Application Filing
- 2016-11-16 EP EP16872771.7A patent/EP3389215A1/en not_active Withdrawn
- 2016-11-16 JP JP2017554989A patent/JP6763398B2/en active Active
Also Published As
Publication number | Publication date |
---|---|
CN108292990B (en) | 2021-06-08 |
WO2017098871A1 (en) | 2017-06-15 |
US20180321705A1 (en) | 2018-11-08 |
JPWO2017098871A1 (en) | 2018-09-27 |
US10739812B2 (en) | 2020-08-11 |
EP3389215A4 (en) | 2018-10-17 |
JP6763398B2 (en) | 2020-09-30 |
CN108292990A (en) | 2018-07-17 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US10739812B2 (en) | Communication system and communication method | |
US10944536B2 (en) | Transmission device, reception device, communication system, signal transmission method, signal reception method, and communication method | |
US11063737B2 (en) | Reception device, transmission device, communication system, signal reception method, signal transmission method, and communication method | |
JPWO2020129685A1 (en) | Communication equipment and communication methods, and programs | |
CN116054870B (en) | Wireless communication circuit, bluetooth communication switching method and electronic equipment | |
KR102599684B1 (en) | Communication systems and communication methods | |
WO2019198434A1 (en) | Impedance adjustment method and semiconductor device | |
CN103678227A (en) | Sharing USB interface circuit and method for USB function and network function | |
JP2016005115A (en) | Serial communication circuit and serial communication device | |
KR20070041857A (en) | Camera sensor module, mobile phone used it, and encoding data transmission method by the camera sensor |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: THE INTERNATIONAL PUBLICATION HAS BEEN MADE |
|
PUAI | Public reference made under article 153(3) epc to a published international application that has entered the european phase |
Free format text: ORIGINAL CODE: 0009012 |
|
STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: REQUEST FOR EXAMINATION WAS MADE |
|
17P | Request for examination filed |
Effective date: 20180704 |
|
A4 | Supplementary search report drawn up and despatched |
Effective date: 20180910 |
|
AK | Designated contracting states |
Kind code of ref document: A1 Designated state(s): AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR |
|
AX | Request for extension of the european patent |
Extension state: BA ME |
|
DAV | Request for validation of the european patent (deleted) | ||
DAX | Request for extension of the european patent (deleted) | ||
STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: EXAMINATION IS IN PROGRESS |
|
17Q | First examination report despatched |
Effective date: 20200723 |
|
STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: EXAMINATION IS IN PROGRESS |
|
RAP3 | Party data changed (applicant data changed or rights of an application transferred) |
Owner name: SONY GROUP CORPORATION |
|
RIC1 | Information provided on ipc code assigned before grant |
Ipc: H04L 65/40 20220101ALI20220601BHEP Ipc: G06F 13/42 20060101ALI20220601BHEP Ipc: G06F 1/12 20060101ALI20220601BHEP Ipc: H04L 7/00 20060101AFI20220601BHEP |
|
GRAP | Despatch of communication of intention to grant a patent |
Free format text: ORIGINAL CODE: EPIDOSNIGR1 |
|
STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: GRANT OF PATENT IS INTENDED |
|
INTG | Intention to grant announced |
Effective date: 20220728 |
|
STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: THE APPLICATION IS DEEMED TO BE WITHDRAWN |
|
18D | Application deemed to be withdrawn |
Effective date: 20221208 |