EP3365974A1 - Dispositif de generation de signaux analogiques et utilisation associée - Google Patents
Dispositif de generation de signaux analogiques et utilisation associéeInfo
- Publication number
- EP3365974A1 EP3365974A1 EP16778817.3A EP16778817A EP3365974A1 EP 3365974 A1 EP3365974 A1 EP 3365974A1 EP 16778817 A EP16778817 A EP 16778817A EP 3365974 A1 EP3365974 A1 EP 3365974A1
- Authority
- EP
- European Patent Office
- Prior art keywords
- signal
- generator
- group
- input
- switching means
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Ceased
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M3/00—Conversion of analogue values to or from differential modulation
- H03M3/30—Delta-sigma modulation
- H03M3/50—Digital/analogue converters using delta-sigma modulation as an intermediate step
- H03M3/502—Details of the final digital/analogue conversion following the digital delta-sigma modulation
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/124—Sampling or signal conditioning arrangements specially adapted for A/D converters
- H03M1/1245—Details of sampling arrangements or methods
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/66—Digital/analogue converters
- H03M1/74—Simultaneous conversion
- H03M1/742—Simultaneous conversion using current sources as quantisation value generators
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K4/00—Generating pulses having essentially a finite slope or stepped portions
- H03K4/02—Generating pulses having essentially a finite slope or stepped portions having stepped portions, e.g. staircase waveform
- H03K4/023—Generating pulses having essentially a finite slope or stepped portions having stepped portions, e.g. staircase waveform by repetitive charge or discharge of a capacitor, analogue generators
Definitions
- the present invention relates to the field of signal generation.
- the present invention more particularly relates to a device for generating analog signals and its associated use.
- a particular application of the device according to the invention relates to the transmission of analog signals in the context of software radio, and more particularly for the fifth generation of standards for mobile telephony (5G).
- 5G mobile telephony
- the signal generation device can find its application in all domains implementing the generation of analog signals from a digital code, such as the generation of radar signals, jamming signals, signals telecommunication, the generation of nested signals, etc.
- the radio signals were generated in baseband in the digital domain, converted into the analog domain and then carried radiofrequency by multiplication by a carrier signal to arrive at an amplifier.
- a disadvantage of this method is that it integrates the part of frequency rise in the analog domain, the nonlinearities of the amplifier can not be compensated in digital since the signal once converted into analog is then mixed with another analog signal. With this method, only baseband errors can be compensated. Moreover this method is not very flexible and not reconfigurable.
- Another method is to operate the increase in frequency in the digital domain by direct digital synthesis (or DDS for "Direct Digital Synthesis" according to English terminology).
- This second method also lacks flexibility since the frequency increase operation implements a carrier frequency which is a multiple of the frequency of which limits the range of carrier frequencies that can be generated.
- An object of the invention is in particular to correct all or part of the disadvantages of the prior art by proposing a reconfigurable solution for generating any analog signals from a digital coding, limiting disturbances and consuming little energy.
- the subject of the invention is an analogue signal generating device comprising a current pump controlled by a digital control code generated by a module for calculating the digital code with noise shaping, said module for calculating the noise.
- digital code with noise shaping comprising at least one quantizer and receiving as input a digital signal representative of the analog signal to be generated,
- said noise-shaping numerical code calculation module comprising a quantization error compensation stage
- said current pump comprising:
- each generator of the first group being complementary to a generator of the second group, two complementary generators delivering currents of opposite amplitude
- the first group of switching means independently controlling the electric current delivered by each generator of the first group of at least one electric current generator is to the first input, or to the second input of the differential amplifier and the second group of switching means independently directing the electric current from either the first input, or from the second input of the differential amplifier to each generator of the second group of at least one electric current generator, the inputs of said differential amplifier being connected in series between the two groups of switching means.
- the current pump comprises a regulation module configured to regulate the average amplitude of the voltage on one of the inputs of the differential amplifier, said regulation module receiving as input a signal representative of the amplitude of the voltage at said differential amplifier input and a reference voltage of predetermined amplitude and outputting a control signal to each generator of one of the two generator sets, said signal control circuit being configured to change the amplitude of the output currents of the generators so as to compensate for the possible imbalance between the current amplitudes delivered by the complementary generators.
- the device for generating analog signals comprises a predistortion module connected between the calculation module of the digital code with noise shaping and the current pump, said predistortion module being configured to modify the digital code. to create pre-distortion and compensate for nonlinearities of the differential amplifier.
- the device for generating analog signals comprises two groups of at least two electric current generators and two groups of at least two switching means. According to one embodiment, the device for generating analog signals is integrated on the same integrated circuit.
- the subject of the invention is also the use of the device for generating analog signals previously described in a Delta modulator.
- FIG. 1 represents an exemplary embodiment of an analog signal generator according to the invention
- FIG. 1 illustrates the principle of error compensation
- FIGS. 3a and 3b are examples of block diagrams illustrating the calculation of the Riemann code
- FIGS. 4a and 4b are examples of block diagrams illustrating the principle of noise shaping according to the invention.
- FIG. 5 represents an exemplary embodiment of a current pump according to the invention
- Figure 6 illustrates the principle of the construction of an analog signal according to the invention
- FIG. 7 represents an example of use of the signal generation device according to the invention.
- FIG. 8 represents an exemplary embodiment of a quantizer.
- FIG. 1 represents an exemplary embodiment of a device 10 for generating analog signals according to the invention.
- the device 10 for generating arbitrary signals allows the construction of any analog signals by a digital coding of the temporal variations of the desired signal.
- the device comprises a digital part (not entirely represented) implementing the digital coding of the signal which generates bitstreams, and which controls a current pump 12 for constructing the analog signal by time integration of switched currents in a capacitive load.
- the digital part comprises a module 11 for calculating the digital code with noise shaping making it possible to push back part of the quantization noise outside the frequency band of the generated analog signal, and thus improves its quality while maintaining a number of bits restricted.
- This module 11 corresponds to the last stage of said digital part.
- the module 11 for calculating the digital code with noise shaping is connected in series with the current pump 12 via an N-bit digital bus (with N an integer).
- the module for calculating the digital code with noise shaping receives as input a digital signal In corresponding to a digital representation on w bits (with w an integer strictly greater than N) of the desired analog signal at the output of said generation device 10.
- analog signal The function of this module 11 is to calculate the discrete derivative on N bits of the analog signal to be generated.
- the module for calculating the digital code with noise shaping may comprise one or more microprocessors, processors, computers or any other equivalent means programmed in a timely manner.
- Figure 2 illustrates the principle of error compensation in the time domain.
- y be the analog signal that it is desired to generate at the output of the device 10 for generating analog signals.
- y s (k) the k th sample of the analog signal y that is to be generated sampled at a frequency f s respecting the Nyquist criterion.
- yR (k) represents the k th sample of the signal signal calculated with the Riemann formulation.
- the quantization error of the k ' th sample is denoted e q (k) and is defined by:
- the target sample at the next iteration would be y s (k + 1).
- the principle of the noise shaping code is to take into account the error made at iteration k to calculate the sample yR (k + 1) at the next iteration k + 1.
- the code will aim for a corrected value y s _corr (k + 1) of this sample integrating the error e q (k) of the previous iteration and defined by:
- y s _corr (k + 1) y s (k + 1) - e q (k)
- the code adds to the value of the sample y R (k) the quantization error e q (k) of the current iteration before the calculation of the next iteration.
- the sample yR (k + 1) is calculated, the average error between two samples is lowered.
- FIG. 3 illustrates, with the aid of a block diagram, the principle of calculating the Riemann code without error compensation.
- the input digital signal In sampled on w bits (with w an integer), is injected into a register 30.
- the resulting signal 31 is then quantized on N bits (with N an integer less than w) across a quantizer 32.
- FIG. 4 illustrates, using an example block diagram, the principle of error compensation according to the invention. This scheme corresponds to the previously presented scheme in which a quantization error compensation stage 1 15 has been added. This compensation stage 1 is configured to add the quantization error to the reconstructed signal.
- the block diagram comprises a register 40, a first summer 41 and a quantizer 42.
- the first summer 41 is configured to form the difference between the signal 405 of the current iteration obtained at the output of the register 40 and that 475 of the previous iteration after compensation.
- the quantizer 42 makes it possible to quantify this difference of signals 41 over N bits.
- the block diagram also comprises a loop 11 2 for reconstructing the signal of the current iteration comprising an adder 43 and a delay block 44.
- the adder 43 is configured to add to a portion of the output signal 425 a part of the signal 445 obtained at the previous iteration.
- Delay block 44 is configured to delay reconstructed signal 435 and thereby synchronize it with that of the next iteration.
- the quantization error compensation stage 1 1 5 comprises two summers 45, 47 and a delay block 46.
- the first summator 45 is connected between the input and the output of the quantizer 42. This summator 45 is configured to subtract at the output signal 425 of said quantizer 42 the signal 41 present at its input to calculate the quantization error 455 made by said quantizer 42.
- the delay block 46 is configured to delay the signal 455 corresponding to the quantization error in order to synchronize it with the signal of the next iteration.
- the second adder 47 is configured to add the signal 455 corresponding to the quantization error and the reconstructed signal 445 to form the compensated signal.
- the output signal is coded on N bits and the calculation of the error is carried out on w bits with w an integer greater than N.
- the quantization error being smaller than the least significant bit (or LSB for "Less meaning Bit” according to the Anglo-Saxon terminology) coded on N bits, the computation of the said quantization error must be carried out with a better resolution thus coded on a number of bits w greater than N.
- the greater the difference between w and N is the more the calculations are precise but in practice one or two more bits are enough.
- the quantizer is modeled by an additional noise E (z).
- the output signal Y can be written in the form:
- the signal X and the quantization error E are multiplied by z "1 and are therefore delayed, but the quantization error is also multiplied by (1 -z ⁇ 1 ), which corresponds to a high-pass type filtering.
- the quantization error compensation stage 1 15 in the calculation module of the digital code with noise shaping 11 makes it possible to reject a part of the quantization noise outside the frequency band of the generated analog signal.
- FIG. 5 represents an exemplary embodiment of a current pump 1 2 according to the invention.
- This current pump includes first order current blockers.
- This circuit has the role of constructing the desired analog signal from the numerical code or digital control signal cmd encoded on N bits and delivered by the module 1 1 of error compensation previously described.
- the current pump 12 comprises two groups G1, G2 of at least one generator 51 of electric current, two groups C1, C2 of at least one switching means 52 and a differential amplifier having an input impedance to capacitive predominance.
- the invention employs a complementary system of two groups G1, G2 of at least one generator 51 of electric current with a capacitive load constituted by the input stage of the amplifier connected in series between these two groups G1, G2.
- Each generator of electric current 51 of a generator group G1 delivers a current of adjustable amplitude while the amplitude of the generator or generators of the other group G2 is fixed.
- Each generator 51 of electric current of the first generator group G1 is complementary to a generator 51 of the second generator group G2.
- Two complementary electric current generators 51 deliver currents of the same amplitude but of opposite sign.
- a first generator group G1 51 pushes the current and a second group G2 pulls it.
- Each generator 51 of electric current delivers a current amplitude +/- 2 n "1 l 0 wherein n is an integer representing the rank of the current generator and varying from 1 to N and 0 the value of an amplitude of predetermined current.
- a first group C1 of switching means 52 independently directs the electric current delivered by each generator 51 of the first group G1 of at least one generator 51 of electric current to either the first input e1, or to the second input e2 of the amplifier differential 55.
- a second group C2 of switching means 52 independently directs the electric current from either the first input e1 or the second input e2 of the differential amplifier 55 to each generator 51 of the second group G2 of at least one generator 51 of electric current.
- Each switching means 52 is activated or deactivated by the control signal.
- the switching means of the first group C1 are controlled by the control signal cmd and the second group C2 is controlled by its complementary signal cmd.
- a module 53 is connected to the input of the current pump 1 2. This module 53 receives as input the control signal cmd and outputs said control signal cmd and its complementary cmd.
- Each group C1, C2 of switching means 52 and each group G1, G2 of current generator 51 comprise as many switching means as of electric current generator.
- Each of the switching means 52 is connected in series between a current generator 51 and an input e1, e2 of the differential amplifier 55.
- the amplitude of the current flowing through each input e1, e2 of the differential amplifier 55 is therefore a function of the number and the rank of the activated switching means.
- each generator group G1, G2 of electrical current 51 and each group C1, C2 of switching means 52 comprise at least two elements
- the electric current generators connected in series with their respective switching means are connected to each other in parallel.
- the differential amplifier 55 is connected in series between the two groups C1, C2 of switching means 52.
- the amplifier 55 is supplied with a differential, which makes it possible to reduce its consumption with respect to an asymmetrical power supply.
- the current sources are extinguished. Indeed, the capacitive load being connected in series with the current sources, there can be no direct current through this load, and therefore no DC power of the current sources.
- the association of the current sources with the capacitor connected in series is self-polarizing in its operating zone. The consumption of the signal generation device 1 0 is therefore reduced compared to a conventional architecture since the system is automatically switched off when there is no need to generate a signal.
- the construction of the analog signal to be generated is based on the decomposition of this signal into piecewise linear functions. In this figure, there is the graphical representation of the analog signal as a function of time.
- the objective is to generate a piecewise linear function using the various predetermined linear functions, which will approximate the desired signal y.
- a linear function will be chosen from the set of predetermined functions so as to minimize the error eq (i) between the value ys (i) of the amplitude of the signal y to l moment x (i) and the value yr (i) of the linear function chosen at this same instant.
- the current flowing through the input impedance of the differential amplifier 55 is greater or smaller.
- the principle of the current pump 12 is based on the integration of constant currents into the predominantly capacitive input impedance of the differential amplifier 55 to generate a piecewise analog signal.
- the input impedance of the amplifier 55 can be likened to an RC circuit (in which R represents a resistance and C a capacitance) which is charged more or less rapidly depending on the current flowing through it and the time during which this current flows.
- R represents a resistance and C a capacitance
- several predefined linear functions having different steering coefficients and therefore different slopes can be generated in order to approximate the analog signal to be generated.
- two groups G1, G2 of N generators 51 of electric current 2 N different linear functions can be defined.
- the current pump 1 2 comprises a regulation module 54 configured to regulate the average value of the amplitude of the voltage on one of the terminals of the differential amplifier, between an input e1 or e2 of the differential amplifier 55 and the ground.
- the regulation module 54 is connected to one of the two current generator groups G1, G2 and receives as input a signal representative of the amplitude of the voltage at said terminal or input e1, e2 of the differential amplifier 55 and a reference voltage of predetermined amplitude.
- the regulation module 54 compares the mean value of the voltage between an input of the differential amplifier 55 and ground with the reference signal and outputs a control signal towards each generator 51 of one of the two groups G1. , Generator G2 51 electric current.
- This control signal is configured to modify the amplitude of the output currents of the generators 51 so as to compensate for the possible imbalance with the current amplitudes delivered by the complementary generators 51. Since the current delivered by the current generators 51 is balanced in a balanced manner, either on one or the other of the two inputs of the differential amplifier 55, no DC voltage is established between these two branches. It is therefore possible to regulate the common mode by controlling the average voltage between one of the two input branches of the differential amplifier and the ground.
- the purpose of the regulation module 54 is to balance the two generator groups G1, G2 of the electric current so as to prevent the average voltage from drifting in particular.
- the regulation module 54 can output a control signal towards each of the generators 51 of the two groups G1, G2 of the electric power generator 51.
- the regulation module 54 regulates only one of the two current generator groups so as to balance it with respect to the second.
- the signal generation device 1 0 can comprise a pre-distortion module 1 3 in series between the module for calculating the digital code with noise shaping and the current pump 1 2.
- preistortion 13 is configured to generate a digital signal capable of compensating for any non-linearities of the differential amplifier 55.
- the compensation of the non-linearities of an amplifier is a well-known technique and can be carried out by any known method of the skilled person. It can be done, for example, by modifying the numerical code to create pre-distortion.
- the signal generation device 1 0 can be integrated on the same chip, an integrated circuit or an integrated circuit specific to an application (or ASIC for "Application Specifies Integrated Circuit” according to the English terminology).
- the device 10 for generating analog signals according to the invention makes it possible to produce a digital-analog converter having a power consumption much lower than that of a conventional converter at the same speed.
- the device 1 0 makes it possible to generate analog signals of good performance with moderate complexity. Indeed the device 1 0 requires only a small component which reduces the cost and especially its very low energy consumption minimizes its impact on autonomy. This last point is very advantageous for use in mobile telephony, in the wireless domain or in a drone where autonomy is a key parameter.
- FIG. 7 shows an example of possible use of the signal generation device 10 in a Delta modulator.
- This Delta modulator comprises an adder 71, a quantizer 72, a module 73 for reshaping the clocks (or DFF for "Delay Flip Flop" according to the Anglo-Saxon terminology) and a device 10 for generating analog signals as previously described.
- the input signal Si n of the modulator Delta is subtracted from the reconstructed value of this signal after quantization via an adder 71.
- the output signal 715 of said summator 71 is then quantized on N levels by means of a quantizer 72.
- the output signal 725 on N levels is then digitized through a module 73 for reshaping the clocks in order to synchronize the different levels compared to a dock clock signal.
- a portion of the quantizer output signal 725 is directed to an analog signal generating device 10 for reconstructing the input signal after quantization.
- FIG. 8 presents an exemplary embodiment of a quantizer 72 using N comparator 80.
- Each comparator 80 compares the voltage of the signal 71 at the output of the adder 71 with a reference voltage. characteristic of a reference level.
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Power Engineering (AREA)
- Compression, Expansion, Code Conversion, And Decoders (AREA)
- Analogue/Digital Conversion (AREA)
- Amplifiers (AREA)
Abstract
Description
Claims
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR1502229A FR3042928B1 (fr) | 2015-10-21 | 2015-10-21 | Dispositif de generation de signaux analogiques et utilisation associee |
PCT/EP2016/074148 WO2017067804A1 (fr) | 2015-10-21 | 2016-10-10 | Dispositif de generation de signaux analogiques et utilisation associee |
Publications (1)
Publication Number | Publication Date |
---|---|
EP3365974A1 true EP3365974A1 (fr) | 2018-08-29 |
Family
ID=55542708
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP16778817.3A Ceased EP3365974A1 (fr) | 2015-10-21 | 2016-10-10 | Dispositif de generation de signaux analogiques et utilisation associée |
Country Status (7)
Country | Link |
---|---|
US (1) | US10340942B2 (fr) |
EP (1) | EP3365974A1 (fr) |
JP (1) | JP2018533302A (fr) |
KR (1) | KR20180071342A (fr) |
CN (1) | CN108292915A (fr) |
FR (1) | FR3042928B1 (fr) |
WO (1) | WO2017067804A1 (fr) |
Family Cites Families (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR1301142A (fr) | 1961-09-08 | 1962-08-10 | Perfectionnement aux dispositifs d'affichage et similaires | |
US5977899A (en) * | 1997-09-25 | 1999-11-02 | Analog Devices, Inc. | Digital-to-analog converter using noise-shaped segmentation |
DE10038372C2 (de) * | 2000-08-07 | 2003-03-13 | Infineon Technologies Ag | Differentieller Digital/Analog-Wandler |
US7421037B2 (en) * | 2003-11-20 | 2008-09-02 | Nokia Corporation | Reconfigurable transmitter with direct digital to RF modulator |
US7173554B2 (en) * | 2004-11-17 | 2007-02-06 | Analog Devices, Inc. | Method and a digital-to-analog converter for converting a time varying digital input signal |
US7307568B1 (en) * | 2004-11-19 | 2007-12-11 | Analog Devices, Inc. | Return-to-hold switching scheme for DAC output stage |
EP1966894B1 (fr) * | 2005-12-28 | 2010-02-10 | Analog Devices, Inc. | Architecture combinant un etage de temps continu et un etage de condensateur commute pour convertisseurs numerique vers analogique et filtres passe-bas |
DE102007056732B4 (de) * | 2007-11-26 | 2012-10-25 | Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. | Vorrichtung und Verfahren zur effizienten Analog-zu-Digital-Wandlung |
US7956782B2 (en) * | 2009-06-11 | 2011-06-07 | Honeywell International Inc. | Current-mode sigma-delta digital-to-analog converter |
US7969340B2 (en) * | 2009-07-22 | 2011-06-28 | Mediatek Inc. | Noise-shaped segmented digital-to-analog converter |
CN101621298A (zh) * | 2009-08-03 | 2010-01-06 | 和芯微电子(四川)有限公司 | 一种能提高信噪比的δ-σ调制器 |
US7986255B2 (en) * | 2009-11-24 | 2011-07-26 | Nxp B.V. | High resolution overlapping bit segmented DAC |
US8519877B1 (en) * | 2012-03-28 | 2013-08-27 | Texas Instruments Incorporated | Low noise and low power arrangement for playing audio signals |
FR3005815B1 (fr) | 2013-05-17 | 2019-09-20 | Thales | Systeme de generation d'un signal analogique |
CN104980159B (zh) * | 2015-06-29 | 2017-11-28 | 清华大学深圳研究生院 | 一种基于电荷泵和压控振荡器的过采样模数转换器 |
US9397676B1 (en) * | 2015-09-29 | 2016-07-19 | Analog Devices, Inc. | Low power switching techniques for digital-to-analog converters |
-
2015
- 2015-10-21 FR FR1502229A patent/FR3042928B1/fr active Active
-
2016
- 2016-10-10 JP JP2018520418A patent/JP2018533302A/ja active Pending
- 2016-10-10 CN CN201680060942.6A patent/CN108292915A/zh active Pending
- 2016-10-10 WO PCT/EP2016/074148 patent/WO2017067804A1/fr active Application Filing
- 2016-10-10 EP EP16778817.3A patent/EP3365974A1/fr not_active Ceased
- 2016-10-10 US US15/768,815 patent/US10340942B2/en active Active
- 2016-10-10 KR KR1020187014296A patent/KR20180071342A/ko unknown
Also Published As
Publication number | Publication date |
---|---|
US20180287627A1 (en) | 2018-10-04 |
JP2018533302A (ja) | 2018-11-08 |
FR3042928B1 (fr) | 2018-11-30 |
CN108292915A (zh) | 2018-07-17 |
FR3042928A1 (fr) | 2017-04-28 |
WO2017067804A1 (fr) | 2017-04-27 |
KR20180071342A (ko) | 2018-06-27 |
US10340942B2 (en) | 2019-07-02 |
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