EP3347985B1 - Integrierte schaltung, schaltungsanordnung und verfahren zum betrieb davon - Google Patents

Integrierte schaltung, schaltungsanordnung und verfahren zum betrieb davon Download PDF

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Publication number
EP3347985B1
EP3347985B1 EP15759808.7A EP15759808A EP3347985B1 EP 3347985 B1 EP3347985 B1 EP 3347985B1 EP 15759808 A EP15759808 A EP 15759808A EP 3347985 B1 EP3347985 B1 EP 3347985B1
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EP
European Patent Office
Prior art keywords
signal
circuit
amplifier circuit
amplification setting
amplifier
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
EP15759808.7A
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English (en)
French (fr)
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EP3347985A1 (de
Inventor
Pirmin Hermann Otto Rombach
Gino Rocca
Anton Leidl
Armin Schober
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TDK Corp
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TDK Corp
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Publication date
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Priority to EP18166857.5A priority Critical patent/EP3367565B9/de
Publication of EP3347985A1 publication Critical patent/EP3347985A1/de
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Publication of EP3347985B1 publication Critical patent/EP3347985B1/de
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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03G—CONTROL OF AMPLIFICATION
    • H03G3/00—Gain control in amplifiers or frequency changers
    • H03G3/20—Automatic control
    • H03G3/30—Automatic control in amplifiers having semiconductor devices
    • H03G3/3005—Automatic control in amplifiers having semiconductor devices in amplifiers suitable for low-frequencies, e.g. audio amplifiers
    • H03G3/3026—Automatic control in amplifiers having semiconductor devices in amplifiers suitable for low-frequencies, e.g. audio amplifiers the gain being discontinuously variable, e.g. controlled by switching
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/181—Low-frequency amplifiers, e.g. audio preamplifiers
    • H03F3/183—Low-frequency amplifiers, e.g. audio preamplifiers with semiconductor devices only
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03G—CONTROL OF AMPLIFICATION
    • H03G3/00—Gain control in amplifiers or frequency changers
    • H03G3/20—Automatic control
    • H03G3/30—Automatic control in amplifiers having semiconductor devices
    • H03G3/3005—Automatic control in amplifiers having semiconductor devices in amplifiers suitable for low-frequencies, e.g. audio amplifiers
    • H03G3/301—Automatic control in amplifiers having semiconductor devices in amplifiers suitable for low-frequencies, e.g. audio amplifiers the gain being continuously variable
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03G—CONTROL OF AMPLIFICATION
    • H03G5/00—Tone control or bandwidth control in amplifiers
    • H03G5/16—Automatic control
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04R—LOUDSPEAKERS, MICROPHONES, GRAMOPHONE PICK-UPS OR LIKE ACOUSTIC ELECTROMECHANICAL TRANSDUCERS; DEAF-AID SETS; PUBLIC ADDRESS SYSTEMS
    • H04R1/00—Details of transducers, loudspeakers or microphones
    • H04R1/02—Casings; Cabinets ; Supports therefor; Mountings therein
    • H04R1/04—Structural association of microphone with electric circuitry therefor
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04R—LOUDSPEAKERS, MICROPHONES, GRAMOPHONE PICK-UPS OR LIKE ACOUSTIC ELECTROMECHANICAL TRANSDUCERS; DEAF-AID SETS; PUBLIC ADDRESS SYSTEMS
    • H04R3/00—Circuits for transducers, loudspeakers or microphones
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/03—Indexing scheme relating to amplifiers the amplifier being designed for audio applications
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04R—LOUDSPEAKERS, MICROPHONES, GRAMOPHONE PICK-UPS OR LIKE ACOUSTIC ELECTROMECHANICAL TRANSDUCERS; DEAF-AID SETS; PUBLIC ADDRESS SYSTEMS
    • H04R2410/00—Microphones

Definitions

  • An integrated circuit comprises at least one supply voltage terminal, at least one input terminal configured to receive an analog input signal corresponding to an audio signal, and at least one output terminal, wherein the integrated circuit is configured to amplify the audio signal received from the input terminal and to output a corresponding amplified signal at the at least one output terminal.
  • a circuit assembly is described that comprises a signal source, a signal processing device and an amplifier circuit arranged in a signal path between the signal source and the signal processing device.
  • a method for operating a circuit assembly is described that comprises a signal source, an amplifier circuit, and a signal processing device.
  • circuits, circuit assemblies and corresponding methods for their operation are known from the field of signal processing in general.
  • circuit arrangements can be used at an analog stage for amplifying a signal provided by a microphone or similar transducer.
  • processing of signals having a high dynamic range is desirable.
  • both quiet and loud passages of the performance should be recorded with high-fidelity.
  • the dynamic range of a processing device is often limited.
  • the dynamic range of an analog-to-digital converter used to convert an analog audio signal for a subsequent digital signal processing device may be restricted by the supply voltage available from the battery.
  • some form of signal preconditioning may be used.
  • an analog signal provided by a microphone may be preamplified using an amplifier having an automatic gain control circuit. In this way, quieter passages of the performance can be amplified using a higher amplification setting, resulting in a greater signal amplitude, while louder parts of the performance can be amplified using a lower amplification setting.
  • US 2014/0185832 A1 discloses an assembly including the signal processing unit SPU shown in Figure 4 .
  • a signal path SL guides from an analog signal input IN A to an analog signal output OUT A .
  • an amplifier LNA is arranged to amplify the useful analog signal fed to the analog signal input IN A and guides the amplified signal to the analog signal output OUT A .
  • an automatic gain control AGC controlling the gain of the amplifier LNA.
  • Gain information about the current gain is provided by the automatic gain control AGC as a digital or analog signal which is delivered to a gain information output DGI.
  • the signal processing unit SPU comprises an analog signal output OUT A and further the gain information output DGI.
  • the information provided at the gain information output DGI may be useful for further processing the amplified analog signal where information about the sensitivity of the signal processing unit SPU is needed.
  • the circuit assembly disclosed in US 2014/0185832 A1 requires the provision of an additional terminal for providing the gain information.
  • the provision of an additional terminal may be problematic.
  • such a circuit assembly may not be used in existing chip packages or circuit arrangements, which do not allow the provision of an additional terminal to supply the required gain information.
  • Prior art document EP 2890155 A1 describes a hearing instrument, in which a microphone amplification circuit has a switchable power supply with two different voltages. The level of a microphone signal is detected with a level detector causing one or the other power supply voltage being connected.
  • Prior art document US 2007/184796 A1 describes a power amplifier controller circuit which controls a power amplifier based upon an amplitude correction signal indicating an amplitude difference between an amplitude of an input signal and an attenuated amplitude of an output signal.
  • the power amplifier controller circuit comprises an amplitude control loop and a phase control loop. The control loop adjusts the supply voltage to the power amplifier based upon the amplitude correction signal.
  • an integrated amplifier circuit hereinafter referred to as integrated circuit.
  • the integrated circuit comprises at least one supply voltage terminal configured to receive a supply voltage for operation of the integrated circuit.
  • the integrated circuit further comprises at least one input terminal configured to receive an analog input signal corresponding to an audio signal and at least one output terminal configured to provide an analog output signal.
  • the integrated circuit further comprises a signal strength detector configured to detect a signal strength of the analog input signal provided at the at least one input terminal.
  • the integrated circuit is configured to amplify the audio signal based on the detected signal strength and to output a corresponding amplified signal at the at least one output terminal.
  • the integrated circuit further comprises a signaling circuit configured to indicate an amplification setting of the integrated circuit at the at least one supply voltage terminal or the at least one output terminal.
  • an integrated circuit used for amplifying an audio signal By detecting a signal strength using a signal strength detector an integrated circuit used for amplifying an audio signal can be configured in accordance with the signal strength of an input signal.
  • the internal configuration of the integrated circuit can be signaled to external entities, such as a signal processing device, by means of a signaling circuit using an existing terminal of the integrated circuit, in particular the output terminal or the supply voltage terminal. In this way, provision of an addition terminal can be prevented, while allowing for a high dynamic range of the audio signal.
  • the analog input signal received at the at least one first input terminal has a predetermined signal bandwidth and the predetermined first frequency signal has a frequency outside the predetermined signal bandwidth, in particular above an upper limit of the predetermined signal bandwidth.
  • the first predetermined signal may be an audio signal in the ultrasonic range, i.e. above 20 kHz.
  • the signaling circuit comprises at least one electrical load and is connected to the at least one supply voltage terminal.
  • the signaling circuit is configured to activate a predetermined first electrical load if the integrated circuit is operating in a first amplification setting, and not to activate a predetermined first electrical load or to activate a predetermined second load if the integrated circuit is operating in a second amplification setting.
  • the amplification setting of the integrated circuit can be signaled by means of a decreased impedance or drop in the supply voltage supplied to the integrated circuit.
  • the signaling circuit comprises an offset generator and is connected to the at least one signal output terminal.
  • the signaling circuit is configured to generate a predetermined first offset voltage and to superimpose the amplified signal with the predetermined first offset voltage if the integrated circuit is operating in a first amplification setting. If the integrated circuit is operating in the second amplification setting, the amplified signal is not superimposed with the predetermined first offset voltage or is superimposed with a predetermined second offset voltage.
  • An offset voltage provided via the at least one output terminal can easily be detected and filtered by a high pass filter. As such, signaling of the amplification setting of the integrated circuit is enabled without significantly disturbing the amplified analog output signal.
  • the signaling circuit is configured to provide a first control signal to indicate a first amplification setting for a first predetermined time period when the integrated circuit is switched into an operating mode using the first amplification setting, and to provide a second control signal to indicate a second amplification setting for a second predetermined time period when the integrated circuit is switched into an operating mode using the second amplification setting.
  • the signaling circuit is configured to provide a first control signal to indicate a first amplification setting as long as the integrated circuit is operating using the first amplification setting, and not to provide the first control signal or to provide a second control signal to indicate a second amplification setting as long as the integrated circuit is operating using the second amplification setting.
  • a first and, optionally, a second control signal By generating a first and, optionally, a second control signal as long as the integrated circuit is operating using a first or second amplification setting, the current amplification setting of the integrated circuit can be detected at any time.
  • a first or a second control signal may only be activated when the operating mode of the integrated circuit has previously changed.
  • the integrated circuit may be operated in one of two predetermined operating modes.
  • the integrated circuit may be operated with one of a plurality of different gain settings of an adjustable amplifier and/or one of a plurality of different microphone bias voltage settings of a bias voltage generator in order to achieve a yet higher dynamic range.
  • the signal strength detector may be configured to determine a sound pressure level of the audio signal.
  • the integrated circuit may comprise a first input terminal and a second input terminal being configured as an input for a differential signal source.
  • the integrated circuit may further comprise a first signal output terminal and a second signal output terminal being configured as a signal output for a differential signal processing device.
  • a circuit assembly comprising a signal source providing a first analog signal, a signal processing device configured to process a second analog signal and an amplifier circuit comprising a signal strength detector and a signaling circuit.
  • the amplifier circuit is arranged in a signal path between the signal source and the signal processing device.
  • the signal strength detector is configured to detect a signal strength of the first analog signal.
  • the amplifier circuit is configured to amplify the first analog signal based on the detected signal strength and to output an amplified version of the first analog signal comprised in the second analog signal.
  • the signaling circuit is configured to indicate an amplification setting of the amplifier circuit by providing a control signal comprised the second analog signal or by modifying a power consumption of the amplifier circuit.
  • the circuit assembly according to the second aspect allows the indication of an amplifier setting to a signal processing device without the provision of an additional terminal at an amplifier circuit or an additional connection between the amplifier circuit and a signal processing device.
  • the circuit assembly further comprises a load detection circuit, the load detection circuit being connected externally to the at least one supply voltage terminal of the amplifier circuit.
  • the load detection circuit is configured to provide a control signal indicative of the amplification setting of the amplifier circuit to the signal processing device.
  • a drop in the supply voltage of the amplifier circuit can be detected. In this way, an appropriate control signal indicative of the amplification setting may be provided to other parts of the circuit assembly.
  • the signal source comprises a high dynamic range analog microphone.
  • the signal processing device comprises at least one of an analog-to-digital converter, an analog signal processor, a microcontroller, a digital signal processor, an audio CODEC and a power amplifier.
  • a method for operating a circuit assembly comprising a signal source, an amplifier circuit, and a signal processing device is provided in accordance with claim 10.
  • an amplification setting of an amplifier circuit can be signaled to a signal processing device without the provision of an additional terminal.
  • an additional high frequency signal is superimposed on an output signal of an amplifier circuit.
  • Figure 1A shows a circuit assembly 100 comprising a signal source 110, an application specific integrated circuit (ASIC) 120 implementing an amplifier circuit, and a signal processing device 190.
  • the signaling source 110 comprises a differential microphone 112.
  • the microphone 112 is connected to the ASIC 120 by means of two input terminals 122 and 124.
  • the first input terminal 122 may be a positive input terminal
  • the second input terminal 124 may be a negative input terminal of a differential signal line.
  • the analog signal provided via the input terminals 122 and 124 is amplified by an amplifier 126 and the output signal of the amplifier 126 is provided at two output terminals 132 and 134 of a differential signal output.
  • the amplifier 126 is a preamplifier with two different gain settings.
  • the gain setting is selected based on a control signal High_SPL generated by signal strength detector in the form of a sound pressure monitor 136. If the detected sound pressure at the input terminals 122 and 124 exceeds a predetermined threshold, the control signal High_SPL is provided to the amplifier 126. If the sound pressure level lies below the predetermined threshold level, the corresponding control signal is not provided.
  • the control signal High_SPL is also provided to a logic circuit 138 and used as a mask signal to mask a high frequency clock signal which is provided by a clock generator 140.
  • the clock generator 140 may provide a fixed frequency signal with a frequency of 25 kHz.
  • the signal generated by the clock generator 140 is used to operate a switch 142.
  • the switch 142 connects the negative output terminal 134 over an internal resistor R with a terminal 144 for connecting the ASIC 120 to an electrical ground potential 146. In this way, an additional signal with a frequency of the clock signal generated by the clock generator 140 is superimposed onto the output signal provided by the ASIC 120.
  • the signal processing device 190 comprises an analog-to-digital converter 192 as well as a digital CODEC 194. Based on a frequency spectrum analysis performed by the CODEC 194, the additional signal generated by the signaling circuit of the ASIC 120 can be detected. Accordingly, the signal processing device 190 can be made aware of the amplification setting of the amplifier 126 and process the amplified signal accordingly.
  • Figure 1B shows a signal level of the control signal High_SPL over time together with a frequency response of the ASIC 120.
  • an additional high frequency signal with a frequency f1 is provided in the time period between t 1 and t 2 , in which a high sound pressure level is detected by the sound pressure monitor 136.
  • the additional signal is provided as long as the control signal High_SPL is high.
  • the frequency f1 of the provided signal lies above the bandwidth of an audio signal provided by the microphone 112, which is amplified by the ASIC 190. In this way, the provision of the additional signal does not interfere with the useful signal provided to the signal processing device 190.
  • Figure 1C shows an alternative signaling scheme according to another embodiment.
  • the control signal High_SPL is also provided to the clock generator 140.
  • the clock generator 140 According to the control signal High_SPL, the clock generator 140 generates a clock frequency with either a first frequency or a second, different frequency, resulting in an additional signal tone with a first frequency f1 or a second frequency f2, respectively.
  • the logic circuit 138 according to this embodiment is configured to pass the clock signal only for a predetermined period of time after the control signal High_SPL has changed. Accordingly, after switching to a low gain setting for a high sound pressure at time t 2 , a signal tone with a frequency f1 is superimposed on the output signal for a predetermined time period.
  • a second signal tone with the same frequency as used before is superimposed on the output signal after switching the amplifier 126 back to the a high gain setting.
  • the ASIC 120 starts in a predefined normal mode on activation, e.g. with a high gain setting, and then, on each toggling of the amplification setting, superimposes a signal tone with the same frequency, e.g. frequency f1, on the output signal.
  • a current signal is superimposed on a normal current consumption of an amplifier circuit.
  • an adjustable bias voltage generator is used to change an amplification ratio of the amplifier circuit.
  • FIG. 2A shows a circuit assembly 200 comprising an application specific integrated circuit (ASIC) 220 implementing an amplifier circuit and a load detection circuit 280. Its intended function and use is similar to that of the ASIC 120 according to the first embodiment. However, in the embodiment shown in Figure 2A , a signal provided by a single ended transducer (not shown) is provided at a single input terminal 222, amplified by an amplifier 126 and provided as an amplified signal at a single output terminal 232 for a subsequent signal processing device (not shown).
  • ASIC application specific integrated circuit
  • the ASIC 220 further comprises a bias voltage generator 228 for generating a bias voltage for a microphone (not shown in Figure 2A ) connected to the input terminal 224.
  • the bias voltage may be provided separately by means of a bias voltage terminal 230 as shown in Figure 2A or may be superimposed on the input signal and provided over the input terminal 222.
  • the bias voltage provided by the bias voltage generator 228 is modified in accordance with a control signal High_SPL indicating a high sound pressure level. If a high sound pressure level is detected, a low bias voltage is supplied to the microphone resulting in a low amplification setting, and vice versa.
  • a supply voltage Vdd is provided to the ASIC 220 by means of a supply voltage terminal 262.
  • the supply voltage Vdd supplied at supply voltage terminal 262 is used, among others, to power the bias voltage generator 228, the amplifier 126, a logic circuit 264, and a sound pressure monitor 136.
  • the control signal High_SPL determined by the sound pressure monitor 136 is provided to the bias voltage generator 228 and the logic circuit 264.
  • the logic circuit 264 selectively closes a first switch 266 or a second switch 268. By closing the first switch 266, a first internal load R1 is connected to the supply voltage terminal 262. By closing the second switch 268, a second internal load R2 is connected to the supply voltage terminal 262.
  • the load detection circuit 280 comprises a detection resistor Rext. Based on the voltage drop across the detection resistor Rext, a current Idd through the ASIC 220 can be determined. Moreover, if the current consumption Idd0 of the ASIC 220 without activated loads R1 and R2 is known, based on the detected current Idd, activation of the loads R1 and R2 can be detected by the load detection circuit 280. Although not shown in Figure 2A , the load detection circuit 280 provides a corresponding control signal to any subsequent processing device which requires knowledge about the amplification setting of the ASIC 220.
  • circuit assembly 200 can best be understood with reference to the signal diagram of Figure 2B .
  • a transition from a mode with high amplification to a mode with low amplification i.e. a transition of the control signal High_SPL from a low state to a high state
  • a first peak on the input current signature of the ASIC 220 to an operating current Idd1 corresponding to the activation of the first load R1 can be observed for a predetermined period of time.
  • the first load R1 is disconnected by the logic circuit 264 using the first switch 266 and the current of the ASIC 220 returns to its nominal current Idd0.
  • a second peak is imprinted on the current signature of the ASIC 220.
  • the peak current consumption in this period corresponds to Idd2.
  • an absolute amplification setting may be communicated to the load detection circuit 280.
  • the second peak may have the same amplitude as the first peak in order to encode a cyclic mode change or mode toggling as described above with respect to the first embodiment. Since the additional loads R1 and R2 are only activated for relatively short periods, they do not significantly affect the energy efficiency of the circuit assembly 200.
  • the additional load R1 may also be activated for the entire duration in which the amplifier 126 is operated in the first amplification setting. In this case, no additional load may be necessary to indicate the second amplification signal.
  • the additional load is activated in the operation mode of the amplifier that is used less in order to improve the energy efficiency of the ASIC 220.
  • FIG. 3A A further illustrative example that is not covered by the claims is shown in Figure 3A , in which a DC shift is applied to the output signal of an amplifier circuit.
  • FIG. 3A shows a circuit assembly 300 comprising a signal source 110, an application specific integrated circuit (ASIC) 320 implementing an amplifier circuit and a signal processing device 390. Its intended function and use is similar to that of the ASIC 120 according to the first embodiment.
  • ASIC application specific integrated circuit
  • the ASIC 320 shown in Figure 3A is connected to a differential microphone 112.
  • a DC shift is forced to the common mode output voltage at output terminals 132 and 134 of the ASIC 320.
  • the output voltage of an amplifier circuit is centered on a mid-rail voltage, for example around 0.9 V for an ASIC 320 having a supply voltage Vdd of 1.8 V.
  • the sound pressure monitor 136 provides a control signal High_SPL to a DC shifter 372.
  • a bias voltage of for example 0.4 V is superimposed on the amplified output signal at the output terminals 132 and 134.
  • a DC detector 396 may be used to detect the DC shift. Moreover, a subsequent subtraction unit 398 will automatically cancel out any DC component provided by the DC shifter 372, such that the signal provided at the output tunnels 132 and 134 can be processed in the same way as in a conventional system.
  • the DC shift may only be provided for a short period after the transition from one amplification setting to another amplification setting.
  • a negative DC shift to voltage level Vo1 may be provided for a predetermined period of time.
  • a DC voltage shift to the voltage potential of Vo2 may be provided.
  • a "toggle" signal may be provided using only a positive or negative offset at changes of the amplification setting, or a corresponding signaling may be applied as long as a particular amplification setting is used by the amplifier 126.
  • each amplification setting could be communicated by use of a tone with a corresponding frequency, a corresponding current signal or a corresponding DC shift.
  • an analog gain setting or microphone bias voltage change may be indicated based on a corresponding frequency of the superimposed control signal, a corresponding current signal or a corresponding DC offset.
  • ASICs 120, 220 and 320 While the embodiment has been described with respect to ASICs 120, 220 and 320, other integrated circuits or circuit arrangements may be used to implement the amplifier circuit. Any such circuit only needs to comprise a supply voltage terminal, a ground potential terminal, one or two input terminals and one or two output terminals. Thus, a conventional chip package having between 4 and 6 output pins can be used in accordance with the present invention.

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  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Physics & Mathematics (AREA)
  • Acoustics & Sound (AREA)
  • Signal Processing (AREA)
  • Power Engineering (AREA)
  • Amplifiers (AREA)
  • Control Of Amplification And Gain Control (AREA)

Claims (10)

  1. Schaltungsanordnung (200), die Folgendes umfasst:
    - eine Signalquelle, die ein erstes Analogsignal liefert, das ein Audiosignal ist;
    - eine Signalverarbeitungsvorrichtung, die zur Verarbeitung eines zweiten Analogsignals konfiguriert ist; und
    - eine Verstärkerschaltung, bei der es sich um eine integrierte Verstärkerschaltung handelt, mit mindestens einem Versorgungsspannungsanschluss (262), der so konfiguriert ist, dass er eine Versorgungsspannung (Vdd) für den Betrieb der Verstärkerschaltung empfängt, einem Signalstärkedetektor und einer Signalisierungsschaltung, wobei die Verstärkerschaltung in einem Signalweg zwischen der Signalquelle (110) und der Signalverarbeitungsvorrichtung angeordnet ist;
    - wobei der Signalstärkedetektor so konfiguriert ist, dass er eine Signalstärke des ersten Analogsignals erfasst;
    - wobei die Verstärkerschaltung so konfiguriert ist, dass sie das erste Analogsignal auf der Grundlage der erfassten Signalstärke verstärkt und eine verstärkte Version des ersten Analogsignals ausgibt, die in dem zweiten Analogsignal enthalten ist; und
    - wobei die Signalisierungsschaltung so konfiguriert ist, dass sie eine Verstärkungseinstellung der Verstärkerschaltung an dem mindestens einen Versorgungsspannungsanschluss (262) durch Ändern einer Leistungsaufnahme der Verstärkerschaltung anzeigt, wobei die Verstärkerschaltung so konfiguriert ist, dass sie die Verstärkungseinstellung auf der Grundlage der erfassten Signalstärke auswählt, dadurch gekennzeichnet, dass
    - die Signalverarbeitungsschaltung eine externe Einheit der integrierten Verstärkerschaltung ist; und
    - die Schaltungsanordnung ferner eine Lasterfassungsschaltung (280) umfasst, die einen Erfassungswiderstand (Rext) aufweist und extern mit dem mindestens einen Versorgungsspannungsanschluss (262) der Verstärkerschaltung verbunden ist, wobei die Lasterfassungsschaltung (280) für Folgendes konfiguriert ist:
    Bestimmen eines Verbrauchsstroms (Idd) durch die Verstärkerschaltung auf der Grundlage eines Spannungsabfalls über dem Erfassungswiderstand, und
    Bereitstellen eines Steuersignals, das die Verstärkungseinstellung der Verstärkerschaltung angibt, an die Signalverarbeitungsvorrichtung.
  2. Schaltungsanordnung (200) nach Anspruch 1,
    wobei die Signalquelle (110) ein analoges Mikrofon mit hohem Dynamikbereich (112) umfasst.
  3. Schaltungsanordnung nach Anspruch 1 oder 2,
    wobei die Signalverarbeitungsvorrichtung mindestens einen Analog-Digital-Wandler, einen Analogsignalprozessor, einen Mikrocontroller, einen Digitalsignalprozessor, einen Audiocodec und einen Leistungsverstärker umfasst.
  4. Schaltungsanordnung nach einem der vorhergehenden Ansprüche,
    wobei die Signalisierungsschaltung mindestens eine elektrische Last (R1, R2) umfasst und mit dem mindestens einen Versorgungsspannungsanschluss (262) verbunden ist, wobei die Signalisierungsschaltung so konfiguriert ist, dass sie eine vorbestimmte erste elektrische Last aktiviert, wenn die integrierte Verstärkerschaltung in einer ersten Verstärkungseinstellung arbeitet, und dass sie die vorbestimmte erste elektrische Last nicht aktiviert oder eine vorbestimmte zweite elektrische Last aktiviert, wenn die integrierte Verstärkerschaltung in einer zweiten Verstärkungseinstellung arbeitet.
  5. Schaltungsanordnung nach einem der Ansprüche 1 bis 4,
    wobei die Signalisierungsschaltung so konfiguriert ist, dass sie ein erstes Steuersignal bereitstellt, um eine erste Verstärkungseinstellung für eine erste vorbestimmte Zeitspanne anzuzeigen, wenn die integrierte Verstärkerschaltung in einen Betriebsmodus geschaltet wird, der die erste Verstärkungseinstellung verwendet, und ein zweites Steuersignal bereitstellt, um eine zweite Verstärkungseinstellung für eine zweite vorbestimmte Zeitspanne anzuzeigen, wenn die integrierte Verstärkerschaltung in einen Betriebsmodus geschaltet wird, der die zweite Verstärkungseinstellung verwendet.
  6. Schaltungsanordnung nach einem der Ansprüche 1 bis 4,
    wobei die Signalisierungsschaltung so konfiguriert ist, dass sie ein erstes Steuersignal liefert, um eine erste Verstärkungseinstellung anzuzeigen, solange die integrierte Verstärkerschaltung unter Verwendung der ersten Verstärkungseinstellung arbeitet, und dass sie das erste Steuersignal nicht liefert oder ein zweites Steuersignal liefert, um eine zweite Verstärkungseinstellung anzuzeigen, solange die integrierte Verstärkerschaltung unter Verwendung der zweiten Verstärkungseinstellung arbeitet.
  7. Schaltungsanordnung nach einem der vorhergehenden Ansprüche, die ferner einen einstellbaren Verstärker (126) umfasst, der so konfiguriert ist, dass er mit einer von mehreren unterschiedlichen Verstärkungseinstellungen betrieben werden kann.
  8. Schaltungsanordnung nach einem der vorhergehenden Ansprüche, die ferner einen Vorspannungsgenerator umfasst, der so konfiguriert ist, dass er mit einer von mehreren unterschiedlichen Mikrofon-Vorspannungseinstellungen betrieben werden kann.
  9. Schaltungsanordnung nach einem der vorhergehenden Ansprüche,
    wobei der Signalstärkedetektor so konfiguriert ist, dass er einen Schalldruckpegel des Audiosignals bestimmt.
  10. Verfahren zum Betreiben der Schaltungsanordnung (200) nach einem der Ansprüche 1 bis 9, wobei das Verfahren Folgendes umfasst:
    - Erfassen, durch den Signalstärkedetektor, einer Signalstärke des ersten Analogsignals, das von der Signalquelle (110) bereitgestellt wird;
    - Auswählen der Verstärkungseinstellung auf der Grundlage der erkannten Signalstärke;
    - Verstärken, durch die Verstärkerschaltung, des bereitgestellten ersten Analogsignals auf der Grundlage der Verstärkungseinstellung, und Bereitstellen des verstärkten Signals an die Signalverarbeitungsvorrichtung; und
    - Anzeigen, durch die Signalisierungsschaltung, der Verstärkungseinstellung an dem mindestens einen Versorgungsspannungsanschluss (262) der Verstärkerschaltung, indem eine Leistungsaufnahme der Verstärkerschaltung geändert wird;
    - Bestimmen, durch die Lasterfassungsschaltung, eines Verbrauchsstroms (Idd) durch die Verstärkerschaltung auf der Grundlage eines Spannungsabfalls über dem Erfassungswiderstand;
    - Bereitstellen, durch die Lasterfassungsschaltung, eines Steuersignals, das die Verstärkungseinstellung der Verstärkerschaltung angibt, an die Signalverarbeitungsvorrichtung.
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CN113347534A (zh) * 2021-05-25 2021-09-03 朱成超 话筒的音频开关的控制方法及控制电路

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CN108028630A (zh) 2018-05-11
EP3367565B9 (de) 2023-07-05
JP2018530223A (ja) 2018-10-11
EP3347985A1 (de) 2018-07-18
CN109245738A (zh) 2019-01-18
US20180262173A1 (en) 2018-09-13
EP3367565B1 (de) 2023-04-19
US10581397B2 (en) 2020-03-03
WO2017041822A1 (en) 2017-03-16
US20180269843A1 (en) 2018-09-20
US10622957B2 (en) 2020-04-14
EP3367565A1 (de) 2018-08-29

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