EP3259671B1 - Selective translation lookaside buffer search and page fault - Google Patents

Selective translation lookaside buffer search and page fault Download PDF

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Publication number
EP3259671B1
EP3259671B1 EP16703901.5A EP16703901A EP3259671B1 EP 3259671 B1 EP3259671 B1 EP 3259671B1 EP 16703901 A EP16703901 A EP 16703901A EP 3259671 B1 EP3259671 B1 EP 3259671B1
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EP
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Prior art keywords
power mode
local memory
virtual address
memory
low power
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German (de)
English (en)
French (fr)
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EP3259671A1 (en
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Christopher Edward Koob
Erich James Plondke
Jiajin Tu
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Qualcomm Inc
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Qualcomm Inc
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0877—Cache access modes
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0706—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
    • G06F11/073—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment in a memory management context, e.g. virtual memory or cache management
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/079—Root cause analysis, i.e. error or fault diagnosis
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1028—Power efficiency
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1032—Reliability improvement, data loss prevention, degraded operation etc
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/50—Control mechanisms for virtual memory, cache or TLB
    • G06F2212/502—Control mechanisms for virtual memory, cache or TLB using adaptive policy
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/68—Details of translation look-aside buffer [TLB]
    • G06F2212/684—TLB miss handling
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • the present application is generally related to translation lookaside buffer (TLB) structure and management.
  • TLB translation lookaside buffer
  • Portable computing devices such as wireless telephones and personal digital assistants (PDAs)
  • PDAs personal digital assistants
  • a wireless telephone may concurrently serve as a digital camera, multi-media file player, and portable game player.
  • available battery volume is decreasing, e.g., due to smaller portable devices and/or volume being occupied by other hardware.
  • One known technique for reducing power is to configure the computing device to switch, for example, in response to explicit instructions, to a local memory/low power mode.
  • a processing core may be allowed to access only a set of lower power local resources, e.g., a local memory which may be tightly coupled to the processing core, and selected other low power and/or essential device resources, and not have access non-local resources.
  • non-local resources can be powered down or otherwise placed in a non-operational state, providing power savings.
  • a power on sequence must be executed before the non-local resources are accessible to the processor core.
  • attempts to access non-local resources while operating in the local resources low power mode must be prohibited, since those resources may be nonoperational.
  • Known conventional techniques for preventing such access can have costs and other shortcomings.
  • one known technique for preventing attempts to access non-local resources when operating in the local memory/low power mode is to invalidate, when switching to that mode, all entries in the computing device's translation lookaside buffer (TLB) that point to non-local resources.
  • TLB translation lookaside buffer
  • the result is that any attempt to access non-local resources while in the local memory/low power mode will cause a "page fault exception" because there is no valid mapping entry in the TLB.
  • invalidating all the TLB entries that point to non-local resources can require significant processing power and time.
  • a significant number of TLB misses and resulting page walk searches may be required until the TLB is repopulated with valid external memory translation entries. The repeated page walk searches can carry substantial power and time costs.
  • Document WO 98/21712 A2 discloses an address translation mechanism which has a region register with an enable indicator corresponding to a region of virtual addresses, and a TLB coupled to the region register to receive a virtual address.
  • the TLB contains a page entry in response to a TLB miss and a first state of the region register enable indicator.
  • Document US2011/0072234 A1 discloses a method for performing a reverse proxy execution operations in a computer system, involving sending a reverse proxy execution request to a remote memory to perform a memory access request, when the physical address is present in remote memory.
  • aspects can provide, among other features, means and methods for rapid, low processing overhead switching between a local memory/low power mode that can confine access to local memory, and a normal power mode enabling full access, for example, to remote memory and other resources. Further aspects can provide, for example, switching to a local memory/low power mode without requiring invalidating of translation lookaside buffer entries, and switching back to a normal power mode, and providing corresponding full access, without requiring TLB miss/page walk refilling a translation lookaside buffer.
  • Examples according to one or more disclosed method aspects can provide access of memory, and example operations can include storing in a translation lookaside buffer a plurality of translation entries, and each may comprise a virtual address, a physical address and a local memory flag and, in an aspect, the local memory flag can indicate whether the physical address is outside a local memory.
  • Example operations can further include, when a processor is in a low power mode, receiving a generated virtual address, and upon identifying a matching translation entry having a virtual address matching the generated virtual address, then, if the local memory flag of the matching translation entry indicates the physical address of the matching translation entry is outside the local memory, example operations can include generating an out-of-access-range memory access exception.
  • Examples according to one or more disclosed apparatus aspects can provide access memory, and can include a translation lookaside buffer (TLB) that can be configured to store a plurality of translation entries, and each may comprise a virtual address, a physical address and a local memory flag and, in aspect, the local memory flag can indicate whether the physical address is outside a local memory.
  • TLB translation lookaside buffer
  • Example apparatuses according to one or more aspects can be further configured to receive a generated virtual address, and to identify a matching translation entry having a virtual address matching the generated virtual address.
  • Example apparatuses can further include an out-of-access-range exception circuit that may be configured to generate, in response to the local flag of the matching translation entry indicating the physical address of the matching translation entry is outside the local memory, an out-of-access-range memory access exception.
  • an out-of-access-range exception circuit may be configured to generate, in response to the local flag of the matching translation entry indicating the physical address of the matching translation entry is outside the local memory, an out-of-access-range memory access exception.
  • Examples according to one or more other disclosed apparatus aspects can provide access of memory, and include means for storing a plurality of translation entries, each of which may comprise a virtual address, a physical address and a local memory flag.
  • the local memory flag can indicate whether the physical address is outside a local memory.
  • Examples according to other apparatus aspects can include means for receiving, when a processor is in a low power mode, a generated virtual address, means for identifying a matching translation entry having a virtual address matching the generated virtual address, and can include means for generating, if the local memory flag of the matching translation entry indicates the physical address of the matching translation entry is outside the local memory, an out-of-access-range memory access exception.
  • Examples according to one or more disclosed aspects of non-transitory computer-readable medium may comprise code, which, when executed by a processor, may cause the processor to store in a translation lookaside buffer (TLB) a plurality of translation entries, each of which may comprise a virtual address, a physical address and a local memory flag.
  • TLB translation lookaside buffer
  • the local memory flag may indicate whether the physical address is outside a local memory.
  • the code may, when executed by a processor, when a processor is in a low power mode, cause the processor to receive a generated virtual address, and upon identifying a matching translation entry having a virtual address matching the generated virtual address, then, if the local memory flag of the matching translation entry indicates the physical address of the matching translation entry is outside the local memory, to generate an out-of-access-range memory access exception.
  • FIG. 1 shows a logical block schematic of one example switchable power/memory access mode processor 100 in accordance with one or more aspects.
  • the switchable power/memory access mode processor 100 may include an instruction execution circuit 102, which can be, for example, an ARMTM or other similar architecture microprocessor core, or any other architecture programmable state machine capable of executing computer-executable instructions (not shown in FIG. 1 ).
  • Computer-executable instructions for the instruction execution circuit 102 can be stored in memory resources including, for example, a local memory 104 tightly coupled to the instruction execution circuit 102, and a remote memory 106 that may be connected to the instruction execution circuit 102 through, for example, a bus 108. It will be understood that the terms "local and "remote,” in the context of "local memory” 104 and “remote memory” 106 are not necessarily descriptors of physical distance.
  • the local memory 104 and remote memory 106 may have any relative distance from the instruction execution circuit 102.
  • the local memory 104 may be tightly coupled to the instruction execution circuit 102, e.g., via a dedicated link or bus (not specifically shown in FIG. 1 ).
  • the instruction execution circuit 102 can generate virtual addresses that a translation lookaside unit 110 translates into actual physical addresses for accessing, for example, the local memory 104, the remote memory 106 and other non-local resources.
  • the translation lookaside unit 110 can have a translation lookaside buffer (TLB) 112 having a content-addressable memory (CAM) (not separately shown in FIG. 1 ) storing R virtual page entries (hereinafter "translation entries”) such as the visible examples labeled 150-1, 1502 ...
  • TLB translation lookaside buffer
  • CAM content-addressable memory
  • Each translation entry 150 can map a virtual page (i.e., a page according the instruction execution circuit 102 virtual addressing scheme) to a physical page number.
  • the physical page number may correspond to the local memory 104, the remote memory 106, or another non-local resource.
  • the R translation entries 150 can be a portion of a larger (not shown in FIG. 1 ) virtual address-to-physical address (hereinafter "virtual-to-physical") mapping (not specifically visible in FIG. 1 ).
  • the TLB 112 can be configured to access its R translation entries 150 using at least a portion of the virtual address generated by the instruction execution circuit 102 (e.g., P bits of a Q bit virtual address).
  • the TLB 112 may have CAM address decoders (not shown in the figures), and can include write circuitry (not shown in the figures) to update the translation entries 150.
  • the CAM address decoders and write circuitry can be implemented using conventional TLB techniques, which may be supplemented with a selective enabling described later in greater detail.
  • the TLB 112 can be configured to indicate a "TLB hit event" when it finds a translation entry 150 that matches the virtual address (or P bit field of that virtual address) it receives from the instruction execution circuit 102.
  • the TLB 112 can be configured to identify a "TLB miss event" in response to finding no matching translation entry 150.
  • the TLB 112 can be configured to generate, in association with identifying a TLB miss event, a page fault signal (abbreviated in FIG. 1 as "PF").
  • PF page fault signal
  • the translation entries 150 can include a virtual address page number (VPN) field 1502, a physical address page number field 1504 (hereinafter “page field 1504,” and abbreviated as “PGN” in FIG. 1 ) and, in an aspect, a local memory flag field 1506.
  • the local memory flag field 1506 can hold a "local flag” (abbreviated as "LM” in FIG. 1 ) having a value that may be switchable between a first value that indicates the physical address in the page field 1504 is a location in the local memory 104, and a second value that indicates the physical address is a location not in the local memory 104.
  • LM local flag
  • logical "0" will be assigned as the first value of the local memory flag and logical "1" will be assigned as the second value of the local memory flag. This assignment is arbitrary and is not intended to limit the scope of any claimed aspect. Example features and operations relating to the local memory flag are described in greater detail in later sections.
  • a valid/not-valid field such as the example "Valid” field 1508 can also be included.
  • the Valid field 1508 can be set and used in accordance with known, conventional TLB valid/not-valid field techniques and, therefore, further detailed description is omitted.
  • the switchable power/memory access mode processor 100 can further comprise a register, such as the power mode register 114 (labeled by the abbreviation "PWR Mode" in FIG. 1 ) that is assigned or configured to store a power mode indicator.
  • the power mode register 114 can be, for example, a feature of the translation lookaside unit 110.
  • the power mode indicator can have a value that is switchable between a first value, e.g., logical "0,” indicating the switchable power/memory access mode processor 100 is in its normal power mode, and a second value, e.g., logical "1," indicating the switchable power/memory access mode processor 100 is in its low power mode. This assignment is arbitrary and is not intended to limit the scope of any claimed aspect.
  • the translation lookaside unit 110 can include a low power mode out-of-range access exception logic 116, abbreviated for brevity in this description by the arbitrary name "LP access exception logic 116."
  • the LP access exception logic 116 can be configured to receive the local memory flag (e.g., from the local memory flag field 1506) of the retrieved translation entry 150 corresponding to a TLB hit and to receive the power mode indicator from the power mode register 114.
  • the LP access exception logic 116 can be configured to generate, while the switchable power/memory access mode processor 100 is in the low power mode, a low power access exception signal in response to the local memory flag of a TLB hit indicating the physical address is outside of local memory,
  • LP access exception logic 116 may depend, at least in part, on the logical value(s) assigned to the local memory flag, the power mode indicator, and the desired polarity of the low power access exception signal.
  • logical "1" may be assigned as the value of the active low power access exception signal.
  • the above-described example assignment of values to the local memory flag is logical "0" and logical "1" to indicate, respectively, the physical address of the TLB hit being inside and outside the local memory 104.
  • the above-described example assignment of values to the power mode indicator stored in the power mode register 114 is logical "0" and logical "1" to indicate, respectively, the switchable power/memory access mode processor 100 being in its normal power mode and low power mode.
  • the LP access exception logic 116 can then, as visible in FIG. 1 , be implemented as an AND gate.
  • a TLB bit having a physical address outside the local memory will cause a concurrence (i.e., an interval of mutually concurrent existence) at the inputs of the LP access exception logic 116, of a logical "1" value of the local memory flag and a logical "1" value of the power mode indicator.
  • the AND operation of the example implementation of the LP access exception logic 116 will output, as the result, an active (meaning logical "1") value of the low power access exception signal.
  • the switchable power/memory access mode processor 100 can include a power mode disabled hardware page walker circuit 118.
  • the power mode disabled hardware page walker circuit 118 can be configured, according to a further aspect, to receive the page fault signal that the TLB 112 generates in response to a TLB miss event, and to receive the power mode indicator from the power mode register 114.
  • the power mode disabled hardware page walker circuit 118 can be configured to disable itself, i.e., become not operational as to performing a page walking, when it receives the power mode indicator at the value indicating the low power mode. Referring to FIG.
  • the visible example of the LP mode disabled hardware page walker circuit 118 is shown having a disable input, arbitrarily labeled "DE,” for receiving the power mode indicator, and having an input arbitrarily labeled "PW" to receive the page fault signal.
  • Logical "1" can be assigned as the value of the power mode indicator that indicates the low power mode, as described previously in this disclosure. Assuming that example assigned value of the power mode indicator, the LP mode disabled hardware page walker circuit 118 may be configured to disable itself in response to receiving a logical "1" at its DE input.
  • the power mode disabled hardware page walker circuit 118 can be configured, according to a further aspect, to perform, in response to receiving the page fault signal while enabled (e.g., while receiving the power mode indicator at logical "0"), a hardware page walk of the previously described larger (e.g., system-wide) virtual-to-physical mapping.
  • the power mode disabled hardware page walker circuit 118 can be implemented, for example, as a combination of known, conventional hardware page walker circuitry (not specifically shown) with added disabling logic (not specifically shown) configured to receive the power mode indicator.
  • a person of ordinary skill in the art can implement such a combination of conventional hardware page walker circuitry and disabling logic by applying conventional engineering know-how such persons possess to the present disclosure, without undue experimentation. Further detailed description is therefore omitted.
  • the switchable power/memory access mode processor 100 can be configured to respond to the low power access exception signal from the LP access exception logic 116 by invoking a particular exception handler (not shown in the figures).
  • the particular exception handler can be arbitrarily termed an "out-of-allowable-access range exception handler.”
  • the out-of-allowable-access range exception handler may be configured to provide recovery from an attempt of the instruction execution circuit 102 to access a non-local resource, e.g., a location outside of the local memory 104, while the switchable power/memory access mode processor 100 is in the low power mode.
  • the instruction execution circuit 102 can send a virtual address to the translation lookaside unit 110.
  • the virtual address may have Q bits, as previously described.
  • P of the Q bits the TLB 112 can search its R translation entries 150. If a matching translation entry is found, a TLB hit event is generated.
  • the local memory flag field 1506 of the matching translation entry may have a local memory flag, which may be at a logical value ("0" or "1") indicating whether the content of the page field 1504 corresponds to the local memory 104.
  • the power mode register 114 value is logical "0" when the switchable power/memory access mode processor 100 is in the normal power mode, and the logical AND operation of the LP access exception logic 116 therefore renders the local memory flag to be a logical "0" value.
  • the switchable power/memory access mode processor 100 in its normal power mode therefore responds to a TLB hit event by generating a complete physical address (e.g., through an offset circuit 120 operating on the page field 1504 of the retrieved translation entry 150) irrespective of the local memory flag value.
  • a TLB miss event (not separately shown in FIG. 1 ) is generated.
  • the TLB 112 in response, sends a page fault signal, indicating no matching translation entry found, to the PW input of the power mode disabled hardware page walker circuit 118. Since the power mode indicator received at the DE input is logical"0," the power mode disabled hardware page walker circuit 118 is enabled.
  • the power mode disabled hardware page walker circuit 118 therefore responds to the page fault signal by performing a hardware page walk of page tables (not shown in FIG. 1 ) having, as previously described, a complete, updated virtual-to-physical mapping for the instruction execution circuit 102 to access all of its memory and other resources.
  • the hardware page walk performed by the power mode disabled hardware page walker circuit 118 can produce either of two results. One is finding in the page tables a virtual-to-physical mapping for the virtual address that caused the TLB miss event. The other possible result is not finding any virtual-to-physical mapping. If the virtual-to-physical mapping is found, the power mode disabled hardware page walker circuit 118 can provide it to the translation lookaside unit 110 for updating the TLB 112. The updating of the TLB 112 can creating a new translation entry 150 comprising, in addition to conventional TLB mapping information, the local memory flag field 1506 with its local memory flag set to indicate whether the physical address found by the hardware page walk is in, or is not in the local memory 104.
  • one or more of the power mode disabled hardware page walker circuit 118, the translation lookaside unit 110, or other logic can be configured to identify whether the physical address field of the virtual-to-physical mapping found by the power mode disabled hardware page walker circuit 118 is, or is not in the local memory 104.
  • one or more of the translation lookaside unit 110 and the power mode disabled hardware page walker circuit 118 may be configured to set the local memory flag in the local memory flag field 1506 of the new translation entry in the TLB 112 according to that identification whether the physical address location is in or not in the local memory 104.
  • the above-described example operations were associated with the switchable power/memory access mode processor 100 being in its normal power mode.
  • Example low power mode operations of the switchable power/memory access mode processor 100 will now be described.
  • the switchable power/memory access mode processor 100 may be configured, for example, to switch to the low power mode in response to receipt of an externally generated command (not explicitly visible in FIG. 1 ).
  • the power mode indicator in the power mode register 114 can be set at logical "1."
  • One example low power mode access operation can begin with the instruction execution circuit 102 sending a virtual address to the translation lookaside unit 110. If the translation lookaside unit 110 finds a matching translation entry 150, it generates a TLB hit event (not specifically shown in FIG. 1 ). Example operations will be first described assuming a matching translation entry is found. Example operations that may be performed if the translation lookaside unit does not find a matching translation entry will be further described in later sections. When in the low power mode a logical "1" value of the power mode indicator from the power mode register 114 is received at the LP access exception logic 116, as opposed to the logical "0" received when in the normal power mode.
  • That logical "1" causes the output of the LP access exception logic 116 to depend on the local flag in the local memory flag field 1506 of the matching translation entry 150. Therefore, in the low power mode, operation of the switchable power/memory access mode processor 100 in response to a TLB hit event depends on the local memory flag in the matching translation entry 150. If the local memory flag indicates the physical page number in the page field 1504 being in the local memory 104, the operations can proceed as described for the normal power mode, namely, a physical address can be generated and the local memory 104 accessed.
  • the LP access exception logic 116 will output an active (in this example, logical "1") low power access exception signal.
  • the active low power access exception signal in an aspect, can cause the previously described out-of-allowable-access range exception handler to be invoked.
  • the switchable power/memory access mode processor 100 can include logic configured to generate a low power mode TLB miss exception signal, in response to a TLB miss event while in the low power mode.
  • One example implementation of such logical can be the logical AND circuit 122, which can be configured to perform a logical AND of the power mode indicator and the page fault signal that is output from the TLB 112.
  • a TLB miss event while in the low power mode can produce a concurrence (meaning an interval of mutually concurrent existence) of the power mode indicator and the page fail output of the TLB 112 at the inputs of the logical AND circuit 122.
  • the logical AND circuit 122 can generate a resulting active (in this example, logical "1") low power mode TLB miss exception signal.
  • Switching the switchable power/memory access mode processor 100 can include, setting the power mode indicator in the power mode register 114 to the value indicating the normal power mode. Operation can then include, when in the normal power mode, receiving another virtual address, at TLB 112, identifying another matching translation 150 entry having a virtual address matching the another virtual address, accessing a memory, e.g., the local memory 104 or the remote memory 106, irrespective of the local memory flag.
  • FIG. 2 shows a logical flow 200 of example operations in processes of memory accesses associated with switching to a low power (abbreviated as "LP" in FIG. 2 ) mode according to one or more aspects.
  • LP low power
  • operations in the flow 200 can start at 202 where, for example, in response to an external instruction (not explicitly visible in FIGS. 1 and 2 ), the switchable power/memory access mode processor 100 switches to a low power mode.
  • operations at 202 can include setting a mode register to indicate the switch to the low power mode.
  • the power mode indicator in the power mode register 114 can be set to logical "1.”
  • the flow 200 in association with switching to the low power mode at 202, can at 204 disable the hardware page walk. Referring to FIG. 1 , the disabling operation at 204 can be performed by the power mode disabled hardware page walker circuit 118 in response to receiving the logical "1" power mode indicator at its DE input.
  • the flow 200 can then proceed to 208 where the TLB 112 can search its R translation entries 150 using that received virtual address. If the searching at 208 results in a TLB hit (shown as a "YES" at decision block 206) then, as shown by decision block 210, the flow 200 can proceed to decision block 212, from which one of two paths is taken depending on the local memory flag in the local memory flag field 1506 of that matching translation entry 150. Referring to FIG.
  • operation of the decision block 212 may be provided by the logical AND, by the LP access exception logic 116, of the local memory flag and the logical "1" power mode indicator from the power mode register 114.
  • the assigned values of the local memory flag are logical "1" for the physical address of the matching translation entry being in the local memory 104, and logical "0" for that physical address not being in the local memory 104.
  • the flow 200 can proceed from the "YES" branch of 212 to 214 to generate the complete physical address, e.g., using the page field 1504 of the matching translation entry 150.
  • the flow 200 can then proceed to 216 and access the local memory 104 using the physical address generated at 214, and then end at 218.
  • the flow 200 can repeat when another virtual address is received at 206.
  • the search of the TLB 112 at 208 produced a hit, causing a "YES" routing from the decision block 210.
  • a search of the TLB 112 at 208 may fail to produce a hit, resulting in a "NO" routing from the decision block 210.
  • the flow 200 may then proceed to 220 and generate the low power mode TLB miss exception signal, for example, based on the logical AND circuit 122 operating on the page fault from the TLB 112 and the power mode indicator at logical "1".
  • the flow 200 can proceed to 222 and generate the low power access exception signal (abbreviated as "LXE" in block item 222).
  • LXE low power access exception signal
  • operations at 222 can comprise the AND operation of LP access exception logic 116.
  • the flow 200 can then proceed to 224 and, for example, invoke the previously described out-of-access range exception hander.
  • FIG. 3 shows a logical flow 300 of example operations in processes of memory accesses associated with switching to a normal power mode according to one or more aspects.
  • example operations in the flow 300 are described in reference to the FIG. 1 switchable power/memory access mode processor 100. It will be understood that such description is not intended to limit any aspect or practice of same to the FIG. 1 switchable power/memory access mode processor 100 architecture.
  • operations in the flow 300 can start at 302 where, for example, in response to an external instruction (not explicitly visible in FIGS. 1 and 3 ), the switchable power/memory access mode processor 100 switches to the normal power mode (abbreviated as "NP" in block item 302).
  • operations at 302 can include setting the power mode indicator in the power mode register 114 to logical "0.”
  • the flow 300 in association with switching to the normal power mode at 302 can, at 304, enable the power mode disabled hardware page walker circuit 118.
  • the enabling operation at 304 can be performed by the power mode disabled hardware page walker circuit 118 in response to receiving the logical "0" power mode indicator at its DE input.
  • the flow 300 may then wait until a virtual address is received by the translation lookaside unit 110 at 306, for example, from the instruction execution circuit 102.
  • flow 300 can proceed to 308 where the TLB 112 can search its R translation entries 150 using the virtual address received at 306. If the searching at 308 results in a TLB hit, i.e., a matching translation entry 150 being found (shown as a "YES" at decision block 310), the flow 300 can proceed to 312 and generate a complete physical address using, e.g., the page field 1504 of the matching translation entry 150. The flow 300 can then proceed to 314 and access its memory resources, e.g., the remote memory 106 and/or the local memory 104, using the physical address generated at 312. After the access at 312 the flow 300 can end at 314 and may repeat when another virtual address is received at 306.
  • the TLB 112 can search its R translation entries 150 using the virtual address received at 306. If the searching at 308 results in a TLB hit, i.e., a matching translation entry 150 being found (shown as a "YES" at decision block 310), the flow 300 can proceed to 312 and generate a
  • the above-described examples of operations in the flow 300 assumed a TLB hit resulting from the search at 308.
  • the search at 308 may fail to find a matching translation entry in the TLB 112.
  • the flow 300 can proceed to 318 and perform a hardware page walk of page tables (not explicitly visible in FIG. 1 ).
  • the hardware page walk performed at 318 can be according to known, conventional hardware page walk techniques and, therefore, further detailed description is omitted.
  • Next operations in the flow 300 after the hardware page walk at 318 can depend on whether it finds a virtual-to-physical mapping, as shown by the decision block 320.
  • the flow 300 may, as shown by the "NO" branch leaving the decision block 320, proceed to 322 and invoke a page fault exception.
  • the page fault exception at 322 may be according to known conventional page fault techniques in response to unsuccessful hardware page walk and, therefore, further detailed description is omitted.
  • the flow 300 can proceed to 324 and determine whether the physical address field of that virtual-to-physical mapping is to a local memory, e.g., the local memory 104, or is outside of the local memory, e.g., the remote memory 106. The flow 300 can then proceed to 326 and use that determination at 324 in updating the TLB 112 with a new translation mapping entry 150.
  • the new translation mapping entry 150 can be formatted according to the example 150-r, having in its VPN field 1502 and page field 1504 the virtual-to-physical mapping found by the hardware page walk at 318, and in its local memory flag field 1506, a local memory flag set a value (e.g., logical "0" or "1") indicating whether the physical address is in the local memory 104, or outside of the local memory, e.g., in the remote memory 106.
  • the flow 300 can then proceed to 314, access the memory using the virtual-to-physical mapping found by the hardware page walk at 318, and then end at 316.
  • FIG. 4 illustrates one example of a personal communication and computing device 400 that can be configured, as described herein, to support or provide functionalities and features described in reference to the FIG. 1 processor system 100.
  • the personal communication and computing device 400 can include a system bus 402 and, coupled to the system bus 402, one or more CPUs 404.
  • the CPUs 404 may comprise, for example, one or more processors or CPUs 406 and one or more cache memories 408.
  • the CPU(s) 406 may be implemented by, for example, one or more programmable computing devices such as, without limitation, one or more ARM-type processing devices (not separately visible in FIG. 4 ).
  • the CPU(s) 406 may capable of performing as a master device.
  • the CPU(s) 406 may be inter-coupled, for example through the system bus 402, to various master and slave devices.
  • the CPUs 404 may, according to conventional communication protocols, communicate with these other devices by exchanging address, control, and data information over the system bus 402.
  • multiple system buses 402 may be provided. In examples having multiple system buses 402, each system bus 402 may constitute a different fabric.
  • the CPU(s) 404 may communicate bus transaction requests to a memory controller 410 of a memory system 412 as one example of a slave device.
  • the CPU(s) 404 may correspond to instruction execution circuit 102 of FIG. 1 .
  • the CPU(s) 404 may be configured to include circuitry (not explicitly visible in FIG. 4 ) and/or computer-executable code (not explicitly visible in FIG. 4 ), implementing the local memory 104, the translation lookaside unit 110 and the power mode disabled hardware page walker circuit 118.
  • the memory system 412 may implement, or form a portion of, the remote memory 106.
  • aspects can include designation as “local memory” certain memory resources (not necessarily visible in FIG. 4 ) that may be physically separated from the CPU(s) 404.
  • aspects can include designation as “outside of local memory” or as “remote memory” certain memory resources (not necessarily visible in FIG. 4 ) that may be physically arranged within areas (not necessarily visible in FIG. 4 ) that may be proximal to, or may even be within one or more of the CPU(s) 404.
  • examples of other master and slave devices can include one or more input devices 414, one or more output devices 416, one or more network interface devices 418, and one or more display controllers 420.
  • the input devices(s) 414 if employed, can include any type of input device, including but not limited to input keys, switches, voice processors, and the like.
  • the output device(s) 416 if used, can include any type of output device, including but not limited to audio, video, other visual indicators and the like.
  • the network interface device(s) 418 if used, can be any type of network interface device configured to allow exchange of data to and from a network 422.
  • the network 422 can be any type of network, including but not limited to a wired or wireless network, a private or public network, a local area network (LAN), a wide area network (WLAN) and the Internet.
  • the network interface device(s) 418 can be configured to support any type of communications protocol desired.
  • the CPU(s) 404 may also be configured to access the display controller(s) 420 over the system bus 402 to control information sent to one or more displays 424.
  • the display controller(s) 420 may send information to the display(s) 424 to be displayed, for example, via one or more video processors 426.
  • the video processors 426 may. For example, process information to be displayed into a format suitable for the display(s) 424.
  • the display(s) 424 can include any type of display, for example, an active or passive liquid crystal display (LCD), a plasma display, and cathode ray tube (CRT).
  • LCD active or passive liquid crystal display
  • plasma display a plasma display
  • CRT cathode ray tube
  • the foregoing disclosed devices and functionalities may be designed and configured into computer files (e.g., RTL, GDSII, GERBER, etc.) stored on computer readable media. Some or all such files may be provided to fabrication handlers who fabricate devices based on such files. Resulting products include semiconductor wafers that are then cut into semiconductor die and packaged into a semiconductor chip. The chips are then employed in devices described above.
  • computer files e.g., RTL, GDSII, GERBER, etc.
  • a software module may reside in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.
  • An exemplary storage medium is coupled to the processor such that the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor.

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Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9658793B2 (en) 2015-02-20 2017-05-23 Qualcomm Incorporated Adaptive mode translation lookaside buffer search and access fault
US10956332B2 (en) * 2017-11-01 2021-03-23 Advanced Micro Devices, Inc. Retaining cache entries of a processor core during a powered-down state
CN108959125B (zh) * 2018-07-03 2021-08-06 中国人民解放军国防科技大学 一种支持数据快速获取的存储访问方法和装置
US11243891B2 (en) * 2018-09-25 2022-02-08 Ati Technologies Ulc External memory based translation lookaside buffer
CN109684236A (zh) * 2018-12-25 2019-04-26 广东浪潮大数据研究有限公司 一种数据写缓存控制方法、装置、电子设备和存储介质
US11301396B2 (en) * 2019-03-29 2022-04-12 Intel Corporation Technologies for accelerated data access and physical data security for edge devices
US11334496B2 (en) * 2019-12-06 2022-05-17 EMC IP Holding Company LLC Method and system for providing processor-addressable persistent memory to guest operating systems in a storage system

Family Cites Families (49)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3012227A (en) 1956-09-26 1961-12-05 Ibm Signal storage system
US4200915A (en) 1978-04-05 1980-04-29 Allen-Bradley Company Program loader for programmable controller
DE3854770T2 (de) 1987-06-29 1997-02-06 Digital Equipment Corp Busadapter für digitales Rechensystem
US5113511A (en) 1989-06-02 1992-05-12 Atari Corporation System for dynamically providing predicted high/slow speed accessing memory to a processing unit based on instructions
US5295258A (en) * 1989-12-22 1994-03-15 Tandem Computers Incorporated Fault-tolerant computer system with online recovery and reintegration of redundant components
US5386563A (en) 1992-10-13 1995-01-31 Advanced Risc Machines Limited Register substitution during exception processing
US5809563A (en) 1996-11-12 1998-09-15 Institute For The Development Of Emerging Architectures, Llc Method and apparatus utilizing a region based page table walk bit
US5996051A (en) 1997-04-14 1999-11-30 Advanced Micro Devices, Inc. Communication system which in a first mode supports concurrent memory acceses of a partitioned memory array and in a second mode supports non-concurrent memory accesses to the entire memory array
US6412056B1 (en) 1997-10-01 2002-06-25 Compac Information Technologies Group, Lp Extended translation lookaside buffer with fine-grain state bits
JPH11282746A (ja) 1998-03-03 1999-10-15 Internatl Business Mach Corp <Ibm> Ｄｒａｍアクセス方法およびｄｒａｍコントロ−ラ
JP3922859B2 (ja) 1999-12-28 2007-05-30 株式会社リコー 画像処理装置、画像処理方法およびその方法をコンピュータに実行させるプログラムを記録したコンピュータ読み取り可能な記録媒体
EP1182561B1 (en) 2000-08-21 2011-10-05 Texas Instruments France Cache with block prefetch and DMA
EP1182568A3 (en) 2000-08-21 2004-07-21 Texas Instruments Incorporated TLB operation based on task-id
EP1182570A3 (en) 2000-08-21 2004-08-04 Texas Instruments Incorporated TLB with resource ID field
US6766433B2 (en) 2001-09-21 2004-07-20 Freescale Semiconductor, Inc. System having user programmable addressing modes and method therefor
US6799257B2 (en) 2002-02-21 2004-09-28 Intel Corporation Method and apparatus to control memory accesses
US7143203B1 (en) 2002-04-26 2006-11-28 Advanced Micro Devices, Inc. Storage device control responsive to operational characteristics of a system
US20040064655A1 (en) 2002-09-27 2004-04-01 Dominic Paulraj Memory access statistics tool
US7146469B2 (en) 2002-10-24 2006-12-05 Sony Corporation Method, apparatus, and system for improving memory access speed
US20040128574A1 (en) * 2002-12-31 2004-07-01 Franco Ricci Reducing integrated circuit power consumption
JP4945053B2 (ja) 2003-03-18 2012-06-06 ルネサスエレクトロニクス株式会社 半導体装置、バスインターフェース装置、およびコンピュータシステム
US20070277023A1 (en) 2003-06-24 2007-11-29 Reinhard Weiberle Method For Switching Over Between At Least Two Operating Modes Of A Processor Unit, As Well Corresponding Processor Unit
US7412581B2 (en) 2003-10-28 2008-08-12 Renesas Technology America, Inc. Processor for virtual machines and method therefor
TWI294569B (en) * 2004-01-16 2008-03-11 Ip First Llc Apparatus and method for performing fast pop operation from random access cache memory and computer-readable storage medium
EP1736887A3 (fr) 2005-05-31 2009-04-22 Stmicroelectronics Sa Repertoire de pages memoire
KR100663864B1 (ko) * 2005-06-16 2007-01-03 엘지전자 주식회사 멀티-코어 프로세서의 프로세서 모드 제어장치 및 방법
US7516274B2 (en) 2005-11-15 2009-04-07 Sun Microsystems, Inc. Power conservation via DRAM access reduction
US7958312B2 (en) 2005-11-15 2011-06-07 Oracle America, Inc. Small and power-efficient cache that can provide data for background DMA devices while the processor is in a low-power state
US7653789B2 (en) 2006-02-01 2010-01-26 Sun Microsystems, Inc. Multiprocessor system that supports both coherent and non-coherent memory accesses
US7882307B1 (en) 2006-04-14 2011-02-01 Tilera Corporation Managing cache memory in a parallel processing environment
US20080147977A1 (en) 2006-07-28 2008-06-19 International Business Machines Corporation Design structure for autonomic mode switching for l2 cache speculative accesses based on l1 cache hit rate
US9652241B2 (en) 2007-04-10 2017-05-16 Cambridge Consultants Ltd. Data processing apparatus with instruction encodings to enable near and far memory access modes
US8601234B2 (en) 2007-11-07 2013-12-03 Qualcomm Incorporated Configurable translation lookaside buffer
US9244855B2 (en) 2007-12-31 2016-01-26 Intel Corporation Method, system, and apparatus for page sizing extension
US8639245B2 (en) 2009-06-08 2014-01-28 Qualcomm Incorporated Method and apparatus for updating rules governing the switching of virtual SIM service contracts
US8719547B2 (en) * 2009-09-18 2014-05-06 Intel Corporation Providing hardware support for shared virtual memory between local and remote physical memory
US8285936B2 (en) 2009-10-20 2012-10-09 The Regents Of The University Of Michigan Cache memory with power saving state
KR101840238B1 (ko) 2010-03-08 2018-03-20 휴렛 팩커드 엔터프라이즈 디벨롭먼트 엘피 데이터 저장 장치 및 방법
US8429378B2 (en) * 2010-07-06 2013-04-23 Qualcomm Incorporated System and method to manage a translation lookaside buffer
US8990602B2 (en) * 2010-12-21 2015-03-24 Intel Corporation Apparatus, method, and system for early deep sleep state exit of a processing element
KR20130002046A (ko) 2011-06-28 2013-01-07 삼성전자주식회사 멀티 코어를 포함하는 저장 장치의 전력 관리 방법
WO2013095559A1 (en) 2011-12-22 2013-06-27 Intel Corporation Power conservation by way of memory channel shutdown
US9075719B2 (en) 2012-02-10 2015-07-07 Hitachi, Ltd. Computer system and storage system
US9141560B2 (en) * 2012-06-29 2015-09-22 Intel Corporation Multi-level storage apparatus
US9069690B2 (en) * 2012-09-13 2015-06-30 Intel Corporation Concurrent page table walker control for TLB miss handling
TW201447579A (zh) * 2013-03-14 2014-12-16 Nvidia Corp 追蹤統一虛擬記憶體系統內分頁錯誤的錯誤緩衝區
JP5734492B1 (ja) 2014-05-08 2015-06-17 ウィンボンド エレクトロニクス コーポレーション 半導体記憶装置
US11656874B2 (en) 2014-10-08 2023-05-23 Nxp Usa, Inc. Asymmetrical processor memory architecture
US9658793B2 (en) * 2015-02-20 2017-05-23 Qualcomm Incorporated Adaptive mode translation lookaside buffer search and access fault

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
None *

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US9858201B2 (en) 2018-01-02
EP3259671A1 (en) 2017-12-27
KR101868389B1 (ko) 2018-06-18
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WO2016133674A1 (en) 2016-08-25
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