TWI294569B - Apparatus and method for performing fast pop operation from random access cache memory and computer-readable storage medium - Google Patents

Description

I2945^L, doc/m IX. Invention Description: [Reciprocal Reference of Related Applications] This case claims US priority. The basic case of this case is US Patent Application No. 10/759489, and the filing date is January 16, 2004. The name is "MICROPROCESSOR AND APPARATUS FOR PERFORMING FAST POP OPERATION FROM RANDOM ACCESS CACHE MEMORY 〇• [Technical Field of the Invention] The present invention relates to a cache memory of a microprocessor, and more particularly to a resolvable stacked type Cache memory with non-stacked memory access - [Prior Art] A microprocessor is a digital device that executes computer program instructions. A typical computer system has a microprocessor connected to the system memory, and the system The memory can store program instructions and the data to be processed by the program instructions. A bottleneck encountered in the execution of such a system, reading data from the system memory to the microprocessor, or writing data from the microprocessor to the system memory. The time it takes to get the body is usually more time-consuming than the microprocessor executing the instructions to process the data. There are usually ten times or even a hundred times the difference between the two times (hence, the micro-processing opportunity is idle while waiting for the memory to be read or written. b However, the designer of the microprocessor knows from the long time ago, The program tends to use only a small amount of data for a long period of time, the program k number. This type of program has a good time regionality 1294569 14394twf.doc/m (temporal ^Hty) ^^ Shell Jdocahty Of reference prindple). In order to take advantage of this principle, modern microprocessors usually have at least one cache memory. The cache memory, "take" is a note on the circuit close to the core of the microprocessor. Storage - a small amount of data, while other data still exist, larger, and farther away from the microprocessor system memory. Cache memory uses the built-in storage unit (stGmgeelement) to store data. When you retrieve data, it is faster than taking data from remote system memory. When the microprocessor executes an instruction to read a memory, such as a load (1〇ad) instruction or a pop (pop) instruction, the microprocessor will first check whether the cache memory has/has ready-made data, that is, Whether the read address has "hit" cache memory. If not, that is, the read address "miss" the cache memory, the microprocessor will not only load the data into the specified scratchpad in the microprocessor, but also the data. Save to cache memory. Now, the data already exists in the cache memory. The next time you encounter an instruction to read the same data, you can load the data from the cache memory to the temporary storage instead of reading from the system memory. Since the data already exists in the cache memory, the above memory read command can be almost completed immediately. The cache memory is stored in a cache line or a cache block. The cache line is the smallest unit of data transferred between the cache memory and the system memory. For example, the size of the cache line can be 64 bytes. When a memory read instruction misses the cache memory, an entire cache line where the read address is located is loaded into the cache memory, and 1294569 14394twf.doc/m is not only required to load the read command. Poor material. Thus, the read command that reads the same cache line data later can be executed very quickly because the data is in the cache memory without reading the system memory. In addition, when a memory write command is executed, such as a st〇re command or a push command, if the write address hits the cache memory, the data can be directly written to the cache line. Delay writing data to system memory. Later, the cache memory writes the cache line to the system memory, usually to make room for the new cache line. The above program is often referred to as a writeback operation. In addition, some cache memories update the entry after the memory write address misses the cache. That is to say, the cache memory will first write back to a record unit of the cache memory as the cache line of the towel (4), and the button will be written in the Shaanxi line where the address is located; k system memory is loaded before the old The cache memory card (four) towel occupied by the cache line. The above is often referred to as a write allocate operation.冋Efficient cache memory can greatly improve the efficiency of the microprocessor. The two main factors that drive memory efficiency are the cache hit rate and the cache access time (4) such as & (10)s ti (4). The rate of the secret is the silk scarf: the time when the number of hits and the number of misses = the sum of the sums. The access coffee is the number of clock cycles of the core of the microprocessor that is required to read the specified material from the cache to the cache memory.戍 j 快快韩(4) shouting because of Qiansi’s memory _ size, also said that the quick-received Lai Keling (four) material number. The larger the silk memory is 1294569 fH / 14394twf.doc/m, the larger the subset of the system memory data that can be stored, the easier the cache line where the data is located exists in the cache memory. Therefore, cache memory always has a tendency to become larger. Traditionally, the size of the cache memory is typically limited by the space available on the microprocessor chip's space that can be allocated to the cache memory. But as circuit components get smaller and smaller, this limitation has gradually disappeared. However, the size of the cache memory also affects the access time of traditional cache memory. Lin's is that the larger the cache memory, the longer the access time. This is because the pass-memory memory is random access memory (_access memory), that is, the time required to access any of the cache lines within the cache memory is the same. Cache the location of the memory in the memory, the circuit will be more _, need to return to (4) time to find the data specified by the memory address. Fortunately, the continuous shrinking and negative cache access time of the circuit components helps to compensate for the increase in the memory of the cache memory and accelerates the clock frequency of the microprocessor (-k ftequenCy) to access the cache. Memory. Therefore, there is now one; = the internal cache of the machine (four), _ is the first - small micro-L1) cache 々丨 駚 如 如 如 如 如 如 如 如 如 be be be be be be be be be be be be be be be be be be be be be be be be be be be For example, S, Pentium _'s level-level Cache is already = _ compared to Pentiumm8's == has 16KB. If you want to record the clock capacity, and you can use the machine core clock. Take the sparse ^, although reducing the cache memory will reduce the effect of 129453⁄4 4twf.doc/m capacity shrink 3" - method 'to increase the effective two goals of the cache memory. Tan Guan, or Lang Shi reached the above [invention content 】 In terms of point of view, the present invention provides _r;:;r; rr _' to store column values. When pushing the resource of the instruction, the value of the column of the push data column is stored. Will be selectively pushed to the top of the last-in, first-out memory. When the push data is in the newly configured cache line in the cache memory, the column value will be pushed in; otherwise, the column value will not be Push in the first-in first-out memory. This device uses pop-up instructions that are usually associated with the previous push command to make a guess pop-up. The push is associated with the pop-up command. In response to the pop-up command, the device immediately provides the data from the cache line of the last-in-first-out memory of the top-most record unit, without waiting for the pop-up source. The result of the calculation of the address does not wait for the decision of whether the source address hits the cache memory. The device will calculate the pop-up source address later and compare its index portion with the top-most record unit of the last-in first-out memory. The column value determines whether the data supplied to the pop-up instruction is correct or not. If it is not correct, there will be a corrective action to provide the correct information. If the pop-up instruction will cause the next pop-up instruction to use another cache line, that is to say If the pop-up instruction is popping up the last data of the cache line specified by the column value, the device will list the above columns.

The I294H value pops up in the first in, first out memory. In one embodiment, the cache memory described above is a set associative cache. In this embodiment, the device includes a second last in first out memory to store the column values. In the push program, the column for storing the push data in the cache memory is selectively pushed to the second last in, first out memory according to the same condition of the column value. In the pop-up program, the device will immediately select the cache line from the last item of the memory, the column value of the unit, and the cache line of the second last-in first-out memory. Guess the data provided without waiting for the result of the pop-up source address calculation, nor for the decision of whether the source address hits the cache memory. In one embodiment, the first and second post-in and first-out memories are the same last-in, first-out memory, wherein the column values and the block values are stored in pairs. In one embodiment, the device records the column value of the last top-in memory of the last-in, first-out memory and the data displacement value of the most recently pushed data among the cache lines specified by the brew value. This displacement value is updated each time a pop-up or push-in command is executed. If the pop-up instruction causes the displacement value to point to the next cache $, the last-in first-out memory will be ejected. Conversely, if the push command causes the displacement value to point to the upper-fast line, the column and slot of the pushed cache line are pushed into the last-in first-out memory. In addition, if there is an instruction to directly modify the stack indicator, the displacement value will be modified, for example, by adding a value to the instruction of the stacked index register. If the above modification causes the displacement value to point to the next cache line, the last in first out memory will pop up. The quick pop-up program provides pop-up data, which can be faster than the 12945^2-cache memory without the above device. To be more explicit, guessing when the data is provided does not include the time required to calculate the pop-up source address and translate the entity source address. In addition, guess the time it takes to provide pop-up data, and it does not include the time required for label comparison. Thus, in at least one embodiment, the pop-up data is provided three clock cycles faster than conventional cache memory. [Embodiment] The use of the private mode of the hair and the moon is usually divided into two regions, that is, a stack region and a non-stack region. Non-heap areas are also commonly referred to as heaps. The main difference between stacking and stacking is that the stacking age is taken, and the scales are often accessed in the way of Oast-in-flm-out (abbreviated as UF〇). The other difference in stacking is the address representation of the read and write instructions. The age of reading into the stack is usually specified directly. The read = is usually indirect with a special register of the microprocessor. This register is usually called the stack cockerel (the ck _ter register). The push command (_) will push the second stack: :: with the new 2 indicator register, and then the data from the micro-processing "to the updated stack indicator register stored in the bribe ER command" will The data to be pushed = Decrement 隹 “ “Scratchpad (for example, if the data is a double word (—Μ, or douMeword), the size is 4 bytes), the tribute is stored in the stack, The updated stack indicator register refers to the (4) address. On the other hand, the Μ instruction (Qing) will put the address when it is temporarily stored from the heap 4 indicator.

1294569 ... 14394twf.doc/m Read the data 'Load the data into the microprocessor's stacking data size, update the stacker & a to play x86 and private register. For example, in the wooden frame #出出令 (for example, p〇p, re will increase the heap size by the size of the pop-up data), θ隹 and the 裇 裇 裇 。. Therefore, the traditional growth (\η" Γ '' stacking is growing with the data push (also, n Wei compassion will gradually pop up and down (that is, the memory address will gradually be temporarily fixed) The stored value is called the scale _ end _. The traditional mechanism of the memory space of Tian Duanfeng. In the general program, the master of the heap, the way, is the subroutine of the subroutine ) and the return address of the program called the program. The called sub-program will bounce and return the address into the microprocessor's program counter (program ΤΓΠ 'Γ 程式 program, (4) called program will pop up parameters, the heap will be restored The original. This concept has an excellent feature that can be used for nested subroutine calls. The quick pop-up procedure described here uses the usual -to-to-bet relationship between push and pop instructions. That is to say, 'the data popped up by each pop-up instruction is usually pushed into the stack by the previous corresponding push command. In the present specification, the pop-up command is the age of moving data from the memory to the microprocessor'. Shift processing _ temporary check deduction fine r = among the - transfer n ' and the memory address of the data is indirect, not directly specified by the instruction. In more detail, the memory address of the pop-up data is based on the stack The value stored in the indicator register. 'Examples of 'pop-up instructions in X% architecture' are POP, RET, and LEAVE refer to 13 1294569 14394twf.doc/m, their source operands (s〇urce 〇perand) are According to the relative address of the inner valley value of the stack indicator register, their target operand (destinahon operand) specifies a register among the microprocessors. In the present specification, the load instruction (load) Is a non-pop-up instruction that moves data from the memory to the microprocessor. That is, the load instruction directly specifies the memory address of the target data, and at least directly specifies one or a set of memory addresses of the specified target data source. The scratchpad. The load instruction example in the x86 architecture is the M〇v instruction, whose source operand specifies a memory location, and its target operand specifies the microsite = a temporary temporary register group Save.

"In the specification of the present invention, the push command is an instruction to move data from the microprocessor to the brother memory, wherein the memory location is specified indirectly, rather than directly in the instruction. More specifically, the push dragon The memory bit = is based on the value stored in the microprocessor's stack indicator register. In the xf 6 architecture, the examples of push instructions are PUSH, cALL, and ENT£R #曰々匕The different elements are relative addresses based on the number of contents of the stacked indicator registers, and their source operands specify a register of the microprocessor register group. In this book, The store instruction is to transfer the data from the micro-processing to the memory-non-pushing instruction. That is to say, the storage instruction will connect to the memory address to be stored in the poor material, at least one or a group of directly. A temporary register for the memory address to which the data is to be stored. The example of the store instruction in the χ86 architecture is the MOV instruction, whose target operand refers to = memory location, and its source operand specifies the microprocessor. Save 14 1294569 14394twf.doc/m 1 is a block diagram of a pipeline microprocessor 100 in accordance with the present invention. In one embodiment, the microprocessor 1 includes a microprocessor. Its instruction set generally follows the instruction set of the X86 architecture. More specifically, its instruction set includes at least POP86 POP, PUSH, CALL, RET, ENTER, and LEAVE instructions. In addition, its instruction set is also This includes loading data from memory and storing instructions to memory, such as the x86 MOV instruction. However, this month is not limited to microprocessors using the χ86 architecture, nor is it limited to the x86 instruction set. The processor 1 includes a register set 112. The register set 112 includes a 'majority', an operand for storing the operand of the microprocessor 100: with state lag. In the example, the register group 112 includes general pUrpose registers, address segment temporary segment^^^^^# |i (status and control registers, and instructions) Indicator temporary _ (instruction p〇inter regis Ter), or as a program counter register. In one embodiment, the register set i 12 includes at least one user-visible, x86 architecture microprocessor register set: more specific The register set 112 includes a stack indicator register 152 that stores the top bits of the stack. In one embodiment, the stacked indicator registers 152 are very similar to the ESP registers of the 86. The microprocessor 1 includes an instruction cache gamma 11 such as 011 (^11 幻1〇2, for storing a cache line of the instruction code. In one embodiment, the finger 15 1294569 14394twf.doc /m

The cache 102 includes a first level (leveM = instruction cache storage_connected to the microprocessor (10) system $, a fetched instruction' such as a push and pop command: a stacked shirt of the overlay indicator register 152; Stop = access to the stack in the system memory. = The processor 100 is also packaged with the bus interface of the instruction cache 1〇2 = (bUS mterfaee unit) 118. The bus interface unit (10) is connected to the microprocessor bus (proce bus) 132, the microprocessor 100 is connected to the system memory via a microprocessor bus (four) cess 〇 rbus) m. Busbar interface unit 118 is the interface between each of the four (4) components of microprocessor (10) and microprocessor busbar 132. For example, bus interface unit u8 fetches instructions from system memory to instruction cache 1〇2. In addition, the bus interface unit 118 will read or write data in the system § memory, for example in the system memory, and the stack indicator 152 indicates the stack of top addresses: the microprocessor 100 also includes a light connection. The instruction fetcher 104 of the instruction cache 102. The instruction fetcher 1〇4 fetches instructions from the instruction cache 1〇2. The instruction fetcher 104 sequentially fetches the next instruction specified by the instruction pointer register in the register group 112, unless an event that changes the program flow, such as a branch instruction, is encountered. The instruction fetcher 1〇4 will start fetching the instruction at the target address of the branch instruction, or the exception event (eXCepti〇n), at which point the instruction fetcher 104 will start fetching the corresponding exception handler (exception). Handler routine). The microprocessor 100 also includes a microprogram 16 1294^1 f.doc/m code memory 128 coupled to the instruction fetcher 104. The microcode memory 128 stores instructions to be fetched by the instruction fetcher 104. More specifically, the microcode memory 128 includes instructions for the exception event handler to handle various exception events generated by the microprocessor 1. In one embodiment, the microprocessor 1 will generate an exception event when detecting a pop-up or push-in guess error to correct the stack access state of the microprocessor, as described in more detail below. Microprocessor 100 also includes an instruction translator 106 coupled to instruction fetcher 1〇4. The instruction translator 1-6 receives instructions from the instruction fetcher 104, such as push and pop instructions, decodes the instructions, and then translates the miCroinstructions performed by other portions of the pipeline of the microprocessor 100. In one embodiment, the other portion of the official line of the microprocessor (8) includes a reduced instruction set computer (red in instruction set c〇mpmer, abbreviated as Risc) core that executes the microcode. In another embodiment, the instruction translator 1-6 generates a mdicator for each instruction to indicate that the translated code is translated, popped, loaded, or stored. Called the macro code. Microprocessor 100 also includes an instruction scheduler 108 that interfaces with instruction ^. The instruction scheduler 108 receives the translated microcode from the instruction switch 22, and issues the microcode 134, and executes the execution unit of the stone horse (execud〇nun(4) ιΐ4. 108 receives the intra-valley value of the microcode 134, n4 + ° 152, and executes the microcode. In the embodiment only, the execution unit 114 includes an integer unit 17 1294569 14394twf.doc/m (integer 仙it), A floating point unit (fl〇atingp〇intunit), a multimedia extension unit (MMX unit), a stream single instruction multiple data extension unit (SSE unit), a branch unit (branch dish, one load unit (1(10)d unit) ): and a storage unit (st〇re unit). The loading unit execution is an instruction to load data from the system memory into the microprocessor 1 , including the pop-up finger storage unit to execute the storage instruction, that is, to store the data from The microprocessor (8) stores instructions to the system memory, including push instructions. • The microprocessor 100 also includes a write-back stage 116 coupled to the execution unit 114. The write back unit 116 receives the execution unit 114 execution曰々, , , α, and write the result, such as the data of the pop-up instruction, back to the register group 112. ..... The microprocessor 1 also includes the data cache 126, data The cache 126 is coupled to the bus interface unit 118 through the bus bar 136 and coupled to the execution unit 114 via the bus bar 138. In an embodiment, the lean cache 126 is the first level data cache memory. The data cache 126 includes a stack cache 124 and a non-stack cache 122. The bus interface unit 118 grabs data from the system memory, takes 126, and extracts data from the data. Cache 126 writes the system memory. The status of the sheep, the field, the bus interface unit 118 will write the cache line from the stack cache 124 and the non-stack cache 122 (four) unified memory, and from the system memory The body reads the cache line to write the allocated entry of the stack cache 124 and the non-stack cache 122. More specifically, the bus interface unit 118 will be stacked in the system memory. The data specified by the push and pop instructions is transmitted between the stack cache 124 and the stack cache 124. 569 14394twf.d〇c/n In an embodiment, the non-stacked cache 122 A body includes a conventional-level cache memory, and the design goal is to face a randomly distributed j memory address, The access time is (10) (four). In m but the 'non-heap cache 122' includes a four-way set associative cache. However, the storage unit will use the non-pushing instruction data to determine whether to store the data in the heap = ancestor 24 or f heap read 122. The storage unit will push the second instruction of the instruction;: put it on the stack * wire 124 instead of the non-stack cache 122, and will not be expected, such as 5 put instructions # material 'stored in non-stack cache and non-stack cache 122 is not worthy of the traditional cache memory. The Heap Express 124 will be further explained later in conjunction with Figure 2. In the rle1r embodiment, the 'microprocessor 100 also includes a second level to take the second level; to support the level - _ cache is stored from the first level of data:: = second level disk swap w... take 2 (including non Stack cache 122: The cache line removed from ίι_4) and the first level data cache 126 抓 grab the cache line from the first level cache. Referring to Fig. 2, Fig. 2 shows the storage unit (st〇rage ei~s) of the pile tL 2memory according to the invention. Although 124 is itself a stack, it is with the heap t end within the system memory. It is indicated by the content value of the stack indicator register 152. The heap $cache 124 is a stack of storage from system memory. 19 1294569 14394twf.doc/m The embodiment of Figure 2 includes 16 storage units, or entries, which are labeled 〇15. The topmost record unit is called record unit 0, and the bottom line is called record unit 15. However, the present invention is not limited to a specific number of recording units in the stack cache 124. Each record unit has space to accommodate the data of the cache line 2〇6, the address tag 204 of the cache line 2〇6, and the cache status 202 of the cache line 206. In one embodiment, the cache state 2〇2 generally follows four well-known states representing cache coherency (c〇herenCy), ie modified, exclusive, shared. And invalid (Invalid), collectively known as MESI. In one embodiment, a cache line 206 contains 64-bit data. In another embodiment, the address tag 204 contains the physical address of the cache line 206. In one embodiment, the address tag 204 includes upper significant bits of the physical address of the cache line 206 for uniquely identifying the cache line 206. In one embodiment, the microprocessor 1 includes a memory paging system responsible for translating virtual memory addresses into physical memory addresses, and the address tags 204 also contain fast Take the virtual address of line 206. In one embodiment, this virtual address is actually a hash result of the virtual address bit to reduce the required storage space. The following will detail how to utilize the virtual address portion of the address tag 204 to make speculative loads on the stack cache 124. The stack cache 124 receives a new cache state to pass the sc-write MESI signal 212. Put into the top of the record unit of the cache type 20 1294569 14394twf.doc / m evil 202 stop. The stack cache 124 receives the new address tag to be placed in the address tag 204 of the topmost record unit via the sc_write one tag signal 214. The stack cache 124 receives the new cache line to place the data of the topmost record unit 2〇6 by sc-write-data signal 216. The stack cache 124 also receives the push-sc signal 232 from the control logic circuit (c〇ntr〇11〇gic) 302 of FIG. When the control logic circuit 3〇2 pushes the push-sc port number 232a to a true value, the stack cache 124 will translate a d-recording unit downward, that is, the bottom recording unit will be removed from the stack. The cache 124, each of the remaining recording units will accept the storage content of the previous recording unit, and the contents of the sc-writeJViESI signal 212, the sc-write-tag signal 214, and the sc-write-data signal 216 will be written in the heap f. Cache 124 records at the top of the record unit. In one embodiment, each double word of the cache line 206 can be individually written via the sC-Write_data signal 216. In another embodiment, a double block contains four bytes. The present invention also includes other embodiments in which each word group (word, i.e., 2 bytes) or each byte of the cache line 206 among the stack caches 124 can pass through sc-write data. Signals 216 are written individually. The stack cache 124 provides the MESI state 202 of sixteen recording units in scJV [ESI[15:0] signal 222. Stack cache 124 provides an address tag 204 of sixteen record units with sc_tag[15:0] signal 224. The stack cache 124 provides sixteen record units of cache line data 206 with an sc-data[15:0] signal 226. The cache line 206 of the topmost recording unit is provided by sc_data[0;| signal, the cache line 206 of the second recording unit is provided by sc_data[lj signal, and so on, the cache of the lowest recording unit. Line 2〇6 is 21 1294569 143 94twf.doc/m is provided by SC_data[15] signal. The address tag 2〇4 and the Mesi state 2〇2 are also provided in the same manner. Stack cache 124 also receives pGp-se signal 234 from control logic 302 of FIG. #控制逻辑电路3〇2 When the P〇P_SC signal 234 is set to true, the stack cache 124 will be flattened by f-record units, that is, the topmost record unit will be removed from the heap and the decision 124 will be taken. The remaining parent records will receive the next record unit 1 content. In the β-embodiment, 'When a recording unit pops up the stack cache i Μ day:, when the p〇p_sc signal 234 is true, the MESI state 2G2 of the bottom record unit of the stack cache 124 is updated to invalid. The MESI state 2〇2 of all the recording units of the stacking cache 124 just started is invalid. ..., please refer to Figure 3, which is a block diagram of additional components of the stacked cache 124 in the Figure, in accordance with the present invention. Stack cache 124 includes a control circuit 302. The 0 control logic circuit 302 receives the push-instr signal 342 from the storage unit of the execution unit 114. When the push-instr signal 342 is a true value, it indicates that the storage unit is requesting to store the data in the data cache 126 of the map in response to the push command from the instruction scheduler 1〇8 of the figure. Control logic circuit 302 also receives a pop-instr signal 344 from the load unit of execution unit 114. When the pop-instr signal 344 is true, it indicates that the load unit is requesting loading data from the data cache 126 in response to the pop-up instruction received from the instruction scheduler 108. Control logic circuit 302 also receives load-instr signal 346 from the load unit of execution unit 丨14. When the load-instr signal 346 is true, 22 1294569 14394twf.doc/m indicates that the load unit is requesting loading data from the data cache 126 in response to the load instruction received from the instruction scheduler 108. Control logic circuit 302 also receives store-instr signal 348 from the storage unit of execution unit 114. When the store-instr signal 348 is true, it indicates that the storage unit is requesting to store data to the data cache 126 in response to the store instruction received from the instruction scheduler 108. Control logic circuit 302 also receives an add_sp_instr signal 352 from the integer unit of execution unit 114. When the Add_sp_instr signal 352 is true, it indicates that the integer unit is notifying the data cache 126 that there is an add instruction (add t0 the stack pointer instruction) from the instruction scheduler 108, such as the ADD instruction of χ86. In one embodiment, this instruction adds a constant to the stack indicator register, just like the ADD ESP, imm instruction. Heap 4: The cache 124 also contains the address generator generat〇r) 306. The address generator 306 receives the operands from the register set 122 of FIG. 1, such as base values, shift values (0ffsets), and memory descriptor values, and generates based on the received values. Virtual address 334. The virtual address 334 is a virtual memory address that accesses a memory instruction, such as a push, pop, load, or store instruction. In the case of an input instruction, virtual address 334 is the virtual address of the data source. In the case of a store instruction, virtual address 334 is the virtual address of the data destination. In the case of a pop-up instruction, virtual address 334 is the virtual address of the pop-up data source. In terms of push instructions, virtual address 334 is the virtual address of the destination of the push data. In one embodiment, the load and store unit includes the address 23 1294569 143 94twf.doc/m generator 306. The stack cache 124 also includes a translation lookaside buffer (TLB) 308 coupled to the address generator 306. The translation buffer 308 stores information of the page tabie to translate the virtual address 334 into a physical address 336. In one embodiment, the translation buffer 308 translates only the upper portion of the physical address 336, while the lower portion is the corresponding lower portion of the virtual address 334. In another embodiment, a page has at least 4 KB, so the lowest 12 bits of the physical address 336 are not translated. The stack cache 124 also includes two comparators 312 coupled to the address generator 306. Each comparator 312 receives a virtual address 334, each. One of the comparison states 312 receives the virtual address portion ' of the sc__tag[0] signal 224 of FIG. 2 and the other comparator 312 receives the virtual address portion of the sc_tag[1] signal 224. That is, the two comparators 312 each receive the virtual address portion of the address tag 204 of the top two recording units of the stack cache 124 of FIG. 2, and compare the corresponding virtual sc_tag signal 224 and virtual address 334, respectively. . If the virtual sc_tag[0] signal 224 is equal to the virtual address 334, the first comparator 312 will generate a true value at the VA-match[0] signal 362, and the VA-match[0] signal 362 will be provided to the control logic. Circuit 302. Similarly, if the virtual scjag[l] signal 224 is equal to the virtual address 334, the second comparator 312 will generate a true value in the VA-match[l] signal 362, and the VA-match[l] signal 362 will also be provided. Control logic circuit 302. Control logic circuit 302 also receives the sc-MESI[15:0] signal 222 from stacker 124 in FIG. The control logic circuit 302 will use the VA-matchHiO] signal 362 and the sc-MESI[1:〇] signal to determine whether the virtual address 334 hits the top two recording units of the stack cache 124, The guessload is loaded from the stack cache 124, as described in more detail below. That is, the 'control logic circuit 3〇2 uses the VA-matchniO' signal 362 and the sc-MEsi[1:〇] signal 222 to determine whether the virtual address 334 is equal to any of the virtual sc-tag[1:〇] signals 224. A valid virtual address portion. In one embodiment, the virtual address tag 204 is a hash result of the virtual address bit, and the virtual address 334 ® is hashed before being supplied to the comparator 312. It should be noted that although in one embodiment of FIG. 3, the top two recording units of the stack cache 124 are checked to determine whether or not to enter the ^^^; loading, the present invention also includes checking two or more tops. Record other real-implementation units of the unit, and in another embodiment, only the topmost one record ♦ unit is checked. The more items that are checked, the greater the chances of detecting a fast load. Therefore, the larger the cache line, the fewer record units that need to be checked. The embodiment of Figure 3 is to examine 128 bytes. #Stack cache 124 also includes sixteen comparators 314 coupled to translation buffer 308. These comparators 314 each receive a physical address 336 and also each receive one of the corresponding scj;ag[15:0] signals 224. That is, the comparator 314 receives the physical address portion of the address tag 204 corresponding to the sc-tag signal 224 and compares it with the physical address 336. If the entity sc_tag[0] sfl 224 and the physical address 336 are the same, the first comparator 314 will generate a true value in the PA-match[0] signal 364, and the PA_match[0] signal 364 will be provided to the control logic. Circuit 3〇2; if the entity sc_tag[i] 25 1294 shed-signal 364 224 is the same as the physical address 336, the second comparator 314 generates a true value in the PA-match[l] number 364, pA"natch The [l] signal 364 is also provided to the control logic circuit 3〇2; and so on, up to the sixteenth comparison state 314. The control logic circuit 〇2 uses the pA-match[15:〇] signal 364 and the sc-MESI[15:0] signal 222 to determine whether the physical address 336 hits any of the record units of the stack cache 124 to Stacking cache 124 loads the poor material' and decides whether the pop-up and guessing loaded data is positive or not. Details will be described later. That is, the control logic circuit 3〇2 uses the PA-match[15:0] signal 364 and the sc-MESI[15:0] signal 222 to determine whether the physical address 336 is associated with the sc-tag[15:〇] signal 224. A valid entity address is partially the same. The control logic circuit 302 also generates a sc-hit signal 389, which is provided to the load and store unit of the execution unit U4 to indicate the cache line involved in the pop-up, push-in, load, or store instructions. At least on the guess, there is a stack cache 124. In the case of a pop-up instruction, the control logic 302 asserts a true value at the sc-hit signal 389 to respond to the true value of the pop-instr signal 344 before confirming that the pop-up source address hits the stack cache 124. It will be detailed later in conjunction with Figure 5. In the case of a push instruction, when sc-MESI[15:0] signal 222 and pa-match[15:0] signal 364 indicate that physical address 336 is equal to one of the valid entity address labels of stack cache 124, or When the stack cache 124 configures the cache line involved in the physical address 336, the control logic circuit 302 will generate a true value in the sc_hit signal 389, which will be described in detail later in FIG. For the load instruction, when the sc-MESI[1:0] signal 222 and the VA_match[l:0] signal 362 indicate 26 I294H. - When virtual address 334 is equal to one of the valid virtual address labels of the topmost record unit of stack cache 124, control logic 3〇2 will guess the true value at % signal 389, or at sc_MESI[15:〇] The signal 222 and the PA-matchtKO] signal 364 indicate that the physical address 336 is equal to one of the valid physical address labels of the stack cache 124, and the true value is generated non-guessed at the sc^hk signal 389, which will be explained later with reference to FIG. In the case of a store instruction, when the 'sc-MESIfao' signal 222 and the PA_match[15:〇] signal 364 indicate that the physical address 336 is equal to one of the valid entity address labels of the stack cache 124, the control logic circuit 3〇2 will The signal produces a true value, which will be further explained later in conjunction with FIG. Control logic circuit 302 is also self-illustrated! The non-stack cache 122 receives the n〇n-sc-hit signal 366. When the physical address 336 hits the non-stack cache 122, the non-SC_hit signal 366 is a true value. Control logic circuit 3〇2 also produces push-sc number 232 and p〇p sc signal 234 of FIG. The stack cache 124 also includes a φ-offset register 322 coupled to the control logic circuit 3〇2 to store a value called fp-〇ffset. The register 322 outputs its value as an fp-offset signal 396 and is then supplied to the control logic circuit 302. The value of the fp-offset register 322 is used to perform a quick pop-up procedure from the stack cache 124, as described in detail below. As can be seen from the following figures, especially the flowcharts of FIGS. 5-7, the fp_ffset register 322 specifies the most recent push command stored in the cache of the top recording unit of the stack cache 124. Location of the data. That is, the fp_ffset register 322 specifies the data location of a push command, and this data has not been popped up in the stack within the main memory. In one embodiment, the power supply saturates 27 1294569 14394 twf.doc/m register 322 contains a four-bit value to specify sixteen of the cache lines 206 stored in the topmost record unit of the stack cache 124. The displacement value of one of the double word groups. The control logic circuit 302 monitors the pop-up, push-in, and add to stack pointer instructions to anticipate changes in the heap index register 152 and to make the values of the fp-fset register 322 and the heap The bits [5:2] of the indicator register ία are consistent. In an embodiment, the control logic circuit 〇2 will update the fp when the load, store, or integer unit of the execution unit ii4 分别 respectively indicates a pop-up, push-in, or heap: £#曰&add instruction. 〇 ffset register 322. In another embodiment, when control logic 302 updates fp_ffset register 322, it does not wait for write-back unit 116 to update stack indicator register 152. In this way, j push-in command, stack indicator addition instruction, or other pop-up instructions; the buckle can use the expected value of the stack indicator register 152 without waiting for the write-back unit 116 to update the stack indicator register. After 152, the bits [5:2] of the stack indicator register 152 are obtained. The Stacker 124 also includes a multiplexer 318 that is lightly connected to the fp-〇ffset register and has six inputs. In one embodiment, the sixteen inputs of multiplexer 318 each receive one of sixteen doublewords of sc-data[〇] signal 226. The multiplexer 318 receives the I 〇 chest signal = as a transfer person, and takes one of the sixteen double words of the se-data [G] job, one of which is output at the fp-data signal 398, and the % sequence is quickly popped up. The instructions are supplied to the pop-up instructions, which are described later. The counterfeit cache 124 also includes an arithmetic unit 304 coupled to the control logic 302. The arithmetic unit 3〇4 receives fp_〇fftet information 28 1294569 14394twf.doc/m No. 396. Arithmetic unit 304 also receives a decrement signal 384 from control logic circuit 3〇2. If control logic 3〇2 produces a true value at decrement signal 384, arithmetic unit 304 decrements the value received from fp_〇ffset signal 396 and provides the result to output 372. If the decrementing procedure causes an underflow, the arithmetic unit 304 will generate a true value at the underbit signal 388 and provide it to the control logic 302. Arithmetic unit 304 also receives an increment signal 386 from control logic circuit 3〇2. If control logic 302 generates a true value at increment signal 386, arithmetic unit 304 increments the value received from fp_〇ffset signal 396 and provides the result to output 372. If the incrementing program causes an overflow, the arithmetic unit 304 will generate a true value at the overflow signal 392 and supply it to the control logic circuit 3〇2. Arithmetic unit 304 also receives an add signal 382 from control logic circuit 3〇2. If control logic 302 generates a true value at summing signal 382, arithmetic unit 304 adds the value received from fp_0ffset signal 396 to the value received from add_sp_val signal 394 and provides the result to output 372. If the addition causes an overflow, the arithmetic unit 304 generates a true value at the overflow signal 392. In an embodiment, the add_sp_val signal 394 is provided by an integer unit of the execution unit 114 of FIG. The value of add_sp_val signal 394 is the value specified by adding a value to the stack indicator register I%. The heap cache 124 also includes a multiplexer 316 that is coupled to the two inputs of the fp-〇ffset register 322. The output of the multiplexer 316 is coupled to the input of the 29 1294 shed ftf.doc/m φ_full et register 322. The multiplexer 316 receives the bits [5:2] of the output of the stacked index register 152 at the other input with the output 372 of one input terminal 410. The multiplexer 316 receives the control signal 368 from the control logic circuit 302 as a selection input to select one of the two inputs and output to the fp_〇ffset register 322. The stack cache 124 also includes a multiplexer 326 coupled to the control logic circuit 〇2, having sixteen inputs. Each of the inputs of the multiplexer 326 receives the stack cache 124 and provides one of the sixteen cache lines 206 of the sc_data[15:0] signal 226. The multiplexer 326 selects one of the sixteen sc_data[15:0] signals 226 based on the Writeback_mux-sel signal 328 generated by the control logic circuit 〇2. The output of multiplexer 326 is provided as an input to a writeback line buffer 324. The output of the write back line buffer 324 is provided through the bus 136 to the bus interface unit 118 of FIG. Control logic circuit 302 also generates a writeback_request signal 338, which is also provided to bus interface unit 118. The write back line buffer 324 and the writeback_request signal 338 are used to write the cache line from the stack cache 124 back to the system memory, as described in more detail below. The control logic 302 generates a true value in the allocate_fill_buffer signal 397 to configure a fill buffer to place the cache line into the system memory, or another cache memory from the microprocessor 100. The body obtains the cache line, for example, from the stack cache 124 or a second level cache memory, which will be described later. Control logic circuit 302 also generates a true value on exception event signal 399 to indicate that an exception event has occurred, causing the microprocessor to execute the microprogram 30 12945 sensitive wf. "Exception event handler within code memory 128, details The control logic circuit 302 also generates a spec-sc-load-mux sel signal 391, a normal-sc-load-mux-sel circuit number 393, and

Ll-niux-sel signal 395, will be explained later with Figure 4. Please refer to FIG. 4. FIG. 4 is a block diagram showing the muxing logic of the first level data cache 126 according to the present invention. The data cache 126 includes four input multiplexers 4〇2, which are provided to the bus 138 of FIG. More specifically, the multiplexer 4〇2 provides a loading unit at the round-trip 138 that pops up and loads the data to the execution unit 114 of the map. The first input of multiplexer 402 is coupled to the non-stacked cache 122 of Figure 1 to receive data 432' to provide data to the load from non-stacked cache 122: ^ program. The second input of multiplexer 402 receives the output 424' of a multiplexer 404 having sixteen inputs to provide data to the self-stack cache i% = guess loader. The third input of the multiplexer receives another output 426 of the multiplexer 406 having six inputs to provide data to the transmitter. . The normal (or non-guessing) loader of the heap cache. The fourth input of multiplex = 402 receives the fp_data signal 398 of Figure 3 to provide a trick to the fast pop-up procedure. The multiplexer 4〇4 receives sixteen double blocks of the cache line 422 output by the two-input multiplexer 412. The multiplexer 404 selects one of the sixteen double blocks of the cache line 422 according to the bit of the physical address 336 of FIG. The multiplexer 406 receives sixteen two-wheels of the cache line 428 that is output by a multiplexer 408 having sixteen inputs. The multiplexer selects one of the sixteen doubles of the cache line 428 based on the bits [5:2] of the physical bit 31 1294569 14394twf.doc/m address 336. The two inputs of the multiplexer 412 receive the cache lines of the two top recording units at the top of the stack cache 124 via the sc_data[l:0] signal 226. The multiplexer 412 selects one of the two cache lines of the sc_data[l:0] signal 226 as the output signal 422' according to the spec_sc_load-mux-sel signal 391 of FIG. 3 and the SpeC-SC An i〇ad_mux__sel signal 391 is generated by the control logic circuit 302 according to the values of the l〇ad_instr signal 346, the VA-match[l:0] signal 362, and the sc-MESI[l:0] signal 222. . The sixteen inputs of multiplexer 408 each receive a cache line of sixteen record units of stack cache 124 via sc-data[15:0] signal 226. The multiplexer 408 selects one of the sixteen cache lines of the sc_data[15:0] signal 226 as the output signal 428' according to the normal-sc-load-mux-sel signal 393 of FIG. The sc_load mux sel signal 393 is generated by the control logic circuit 302 based on the values of the load-instr signal 346, the PA-match[15:0] signal 364, and the sc-MESI[15:0] signal 222, which will be described later. 5 is a flow chart of a quick pop-up procedure from the stack cache 124 of FIG. 1 in accordance with the present invention. The process begins with step 5〇2. At step 502, the instruction translator 1 图 6 of FIG. 1 decodes the pop-up instructions, and the instruction scheduler 108 of FIG. 1 sends the pop-up instructions to the load unit of the map execution unit 114. Next, the load unit will generate a true value at the p〇Rjnstr signal 344 of FIG. The flow proceeds to step 5〇4. At step 504, the multiplexer 318 selects the appropriate double word from the top line of the stack cache 124, 32 1294569 14394 twf.doc/m, the cache line SC_data[〇] (10), to fp according to FIG. An offset register 322 _ value provides an address signal 398. In response to the true value of the pop signal 344, the control circuit 302 of FIG. 3 outputs a value at the L1-mux-sel signal 395, causing the multiplexer 402 of FIG. 4 to select the fp-data signal view of FIG. Then, the load unit is provided to the loading unit of the execution unit 114 via the bus bar 138 to supply the = instruction, and then the write back unit 116 will print the signal Φ of the her signal to the specified position of the pop-up instruction. Among the registers m are - • , the device. For example, if the pop-up command is the RET finger of the X86; the pop-up data will carry the command indicator register of the temporary bank group 1丨2. Another example: If the pop-up instruction is an x86 LEAVE instruction, the pop-up data will temporarily store the EBP register of the state group 112. As another example, if the P〇P instruction of ':疋X86 is popped up, the popup data will be loaded into the scratchpad group 112 as the temporary register specified by the POP instruction. As can be seen from Figure 5, the data is a guess. This is because it is not certain that the source address of the pop-up instruction generated at the physical address 336 at step 516w will be provided to the manned unit's pop-up material with the top-most record bit of the HSBC cache 124. The address is the same. In addition, in response to the true value of the p〇pJnstr signal 344, the control logic 302 generates a true sc-hit signal 389 to the load unit of the execution unit 114 at the scJlit signal 389 of FIG. The flow then proceeds to step 506. At step 506, the control logic circuit 〇2 will generate true at the increment signal 386, causing the arithmetic unit 304 to increment the fp-offset signal by 3% and provide an incremental result in the round-out 372, and then the control logic circuit 3〇 will pass through. 33 1294569 14394twf.doc/m The over control signal 368 causes the multiplexer 316 to select this incremental result for loading into the fp_〇ffset register 322 of FIG. Next, at step 508, control logic circuit 3 检查 2 will check overflow signal 392 to determine if the incrementing of step 506 causes each of the suffocating states 322 to overflow. That is to say, whether the control logic circuit 3 instruction causes the stack indicator to be temporarily stored is determined to be the next one; = output if yes, the process proceeds to step 512, otherwise to step 514. At step 512, control logic 302 generates a true value at p〇p_% signal 234 to eject the topmost record unit of stack cache 124. The top-most record unit is popped up in order to make the stack cache 124 盥 cache, because the current pop-up instruction is transferring the cache _ last-double word stored in the top-end g In the embodiment, the step 512 is performed after the step 518, which is described later, so that the value of the sc_tag[0] signal 224 of the record unit providing the data in the physical address 336 and the step 5〇4 can be compared. In one embodiment, the value of sc-tag[〇] signal 224 used in step 〇4 is stored and left for later, step 518 is used. Although in an embodiment, the fp-saturated register illusion 2 is a double-word displacement value, the present invention also includes other embodiments in which the double-word group is pushed in. The push-in and the bullet-out data are different, for example, a word, a byte, or a quad will calculate the pop-up finger. Next, in step 514, the address generator 3〇6 The source virtual address 334 of the order. Next, at step 516, translation of the scratchpad 3〇8 will result in a source entity address 336 of the pop-up finger 34 1294 total twf.doc/m command. Next, at step 518, one of the comparators 314 of FIG. 3 compares the entity address 336 generated at step 516 with the entity sc_tag[0] signal 224 of FIG. 2 to produce the PA of FIG. Match[〇] signal 364. Next, at decision step 522, control logic 302 checks s: -MESI[0] signal 222 and pA-match[0] signal 364 to determine if the topmost recording unit of stack cache 124 is valid and pops up. Whether the source entity address 336 of the instruction is equal to the body address tag 204 of the topmost record unit of the stack cache 124, that is, whether the physical address 336 hits the topmost record unit of the stack cache 124. In one embodiment, the bit [5··2] of the physical address 336 is also compared with the value of the Φ-offset signal 396. The latter is a double word for selecting the fp-data signal 398 to

Is Sint correct? If the source entity address of the pop-up age m is the topmost record unit of the main cache 124, the process ends here, and the test pop-up program provides the correct pop-up data. Otherwise, the process proceeds to step 524. (4) Pingbeibei Village No In step 524, the control logic circuit 3〇 ί ί2: micro/computer _ execution exception event processing = where the exception event production provides the status of the error data. In an embodiment, the index register stack r124' is loaded into the stacking embodiment. The Iβ2 also includes writing the stacked cache lines back to the system memory and 124 of the active first level caches. The process ends in step 35 12945 - 524. As you can see before, you will also be described in detail later in Figure 1. The quick pop-up program in Figure 5 can make the pop-up command clear (4), which is faster than the traditional cache (4) that does not distinguish pop-up and manned commands. Several clocks are in week 3. 6 is a flow chart showing the push procedure of the stack cache i24 pushed into the map according to the present invention. The process begins with step 6〇2. At step 602, the instruction translator 1〇6 of Fig. 1 decodes the push-in instruction, and then the instruction scheduler 1〇8 issues a push-in instruction to the storage unit of the execution unit 114. The storage unit will then generate a true value in Figure 3, signal 342. Next, at step 604, the control logic circuit 302 generates a true value at the decrement signal 384, causing the arithmetic unit 3〇4 to decrement fp_〇 to the signal 396, and output a decrement result at the output terminal 372, and the control logic circuit 3〇2 The control signal 368 is utilized to cause the multiplexer 316 to select the decrement result to load it into the fp-offset temporary storage 322 of FIG. In addition, in response to the true value of the push_instr signal 342, the control logic circuit 3〇2 generates a true value at the sc_hit signal 389 to supply the storage unit of the execution unit 114. Next, at step 606, the address generator 306 calculates the target virtual address 334 of the push command. Next, at step 608, the translation buffer 308 will generate the target entity address 336 of the push command. Next, at step 612, one of the comparators 314 of FIG. 3 compares the entity address 336 generated at step 516 with the entity scjag[0] signal 224 of FIG. 2 to produce the PA_match[0] of FIG. Signal 364. 36 l294mi, 〇c/m Next, in step 614, the control logic circuit 3〇2 checks s:_MESI[0] shout 222 and PA_match[〇] signal 364 to determine the topmost record of the ^® cache 124. Whether the unit is valid, and decides whether the target entity address 336 of the referral finger is equal to the topmost ^= of the stack cache 124. That is, whether the real-age address η6 hits 2 heaps (four) takes 124 times. Track position. Two == will enter (10)18. In the embodiment, the 5 recorded units hit by .w are not at the top of the stack cache 124, and 124 will be empty after the effective recording unit of the towel is written. The flow then proceeds to step 616. The data of the push button 16 will be stored in the topmost record unit of the sc~write-data signal 216, and stored in the physical address 336, the double line of the cache line 2〇6 specified by the bit το [5:2] The word shift value. If necessary, the MESI status 2〇2 of the topmost recording unit will be updated via _212, for example, updated to the modified status =- 贝 疋 from the register group 112, the temporary specified by the push instruction. For example, 'If the push command is χ (4) Call command push 2 = Calculate the next command from the register group 112 command indicator register

ΒΝ = ϋ indicator. - As another example, if the push command is x86 ^. 9, 7, push the poor material is the content value of the EBP = device of the x86 register group 112. As another example, if the push command is the order (4) temporary storage. In the _16 end 在 in decision step 618, because the target address 336 of the push data misses 37 I294H-/m stack=take 124, the stack cache 124 must be configured with a new logged unit at the top to Store the cache line where the push target address 336 is located. To do this, the Stack Cache 124 will pan down one record unit and the bottom record unit will move out of the Stack Cache 124. Therefore, the control logic circuit 3〇2 checks sc_MESI[15] 222 to determine whether the bottommost record unit of the stack cache 124 is valid. If it is active, the process proceeds to step 622, otherwise step 624 is entered. At step 622, the control logic circuit 〇2 will schedule the write back of the bottommost record unit of the stack cache 124 by generating a true value in the writeback_mux-select signal 328, causing the multiplexer 326 to select sc. The -data[15] signal 226' is the cache line of the bottommost record unit of the stack cache 124 to supply the write back line buffer 324, and then generates a true value at the writeback_request signal 338 to request the sink of Figure 1. The interface unit 118 writes the cache line described above back to the second level cache or system memory. Next, in step 624, the control logic circuit 3〇2 sets up a push_sc > signal 232 to cause the stack cache 124 to translate downward by one recording unit to respectively transmit 8 (; 1 \ 1 1 1 (1 & 3 The signal 216, 3""1"" & 2 signal 214, and the SC-write-MESI signal 212 store the push data and its address tag and MESI status. Next, at step 626, the control logic circuit 3 2 will configure a load staging area so that the stack cache 124 is ready to accommodate the cache line where the push target's target address 336 is located and store the cache line into the stack cache 124. In an embodiment, the steps 626 also includes accessing the non-stacked cache 122 38 1294 欢 f.doc / m process at step 628 end ^ recording the combination of the push information in the early position. 媳 = please / according to Figure 7, Figure 7 is in accordance with the present invention, ® 1 - 2, the program flow chart of the stacking index addition instruction. For example: ^ Use: Part of the well-behaved program = The pop-up instruction should follow = Say, 'Every pusher has the right = sub-program The required parameters (.^^ Recalling the function of the body C Ϊ ( (fUnetkm) is to use the system to record two, Γ transfer. 4 Will execute - a series of PUSH instructions to push the parameters, abundance, and weave orders to push the human-item parameters. For example, before calling the function that receives five four-byte parameters, the call is responsible: five times Let 'push five parameters into the stack. Then call; ^ ^LLf ^ ', push the return address to the stack, and control: ,,, and port. The last instruction of the subroutine is RET, which The returning address will be returned from the heap. The program to be called must restore the = space of the parameter. One method is to execute the POP instruction five times in succession, so that the stack indicator returns to the value before the parameter was pushed. However, due to The calling function does not need these parameters. Most of the compilers (C〇mpiler) directly use the 39 1294掀 ADD deduction to increase the size of the space occupied by the parameters back to the stacking indicator. Generate an ADD instruction instead of five instructions, so the program execution will be faster and the code will be smaller. In the above example, the calling program will add 20 to the stack indicator. This is the most common, push Inconsistent with pop-up instructions Thus, in one embodiment, the fast pop-up apparatus of the present invention will find an instruction to add a value to the stack indicator and adjust the value of fp-offset 322. This flow begins at step 702 of Figure 7. The instruction translator 1〇6 of FIG. 1 decodes an add instruction that targets the stack to be temporarily stored as 152, and the instruction scheduler 1〇8 sends the add instruction to the integer unit of the execution unit 114. Then the integer unit The true value will be generated in the add_sp-instr signal 3M of FIG. Next, in step 704, the control logic circuit 3〇2 generates a true value at the addition signal 382, causing the arithmetic unit 3〇4 to add the add-print signal to the fp-offset signal 396, and provide the result at the output 372. The control logic 302 causes the multiplexer 316 to select the result via the control signal 368 to load into the fp_0ffset register 322 of FIG. Next, at decision step 706, the control logic circuit 〇2 checks the overflow signal 392 to determine if the add procedure of step 704 creates an offset of the offset state 322. That is, the control logic circuit 3 determines whether the above-described addition instruction causes the stack indicator register 152 to point to another cache line. In step 706, the overflow means that the addition causes the stacking buffer 152+ to point to the cache line of the topmost storage unit of the stack cache m. More specifically, if the addition causes an overflow, the stack indicator register I294^i, oc/1 152 usually points to the address of the cache line whose memory address is adjacent to and larger than the topmost storage unit of the stack cache 124. Cache line. Therefore, the stack cache 124 must be ejected so that the correct cache line is at the top of the record unit. In one embodiment, control logic 302 issues an add instruction that causes stack indicator register 152 to overflow more than one cache line. In this embodiment, in the next step 708, the number of line units N that the stack cache 124 must pop out is calculated by the following formula, and the size of the false line is 1 byte. · An oriset + add-sp One val) / 64 Therefore, if N is greater than 1, it indicates that an overflow occurs, and the flow is combined with step 708, otherwise the flow ends. 3 = step 708 ’ control logic circuit 3〇2 will say J true f in the qing-sc signal to pop up the topmost recording unit of the stack cache 124. However, if you decide that the top 10 of the record unit is valid, you will write the effective remaining line back to the system. The action is not the same as the record. As described in step 7〇6, the value of '' in '-yous| is calculated by the calculation of 'stacking cache' and the state of being valid is written back to the second step in the step stacking speed η according to this Invented from the stack of Figure 1 with 8C. Simply said, private. Figure 8 contains Figure 8 VIII, sin, order; Figure 8 Β 示 堆叠 ^ ^ f f f f f f f f f 124 124 124 124 124 124 124 124 124 124 124 124 124 124 124 124 124 124 124 124 124 124 124 124 124 124 124 124 124 124 124 124 124 124 124 124 124 124 124 124 124 124 124 124 124 124 124 124 124 124 124 124 124 124 124 124 124 Loader for non-stacked cache 122. The process begins with a step. In the general program, the system memory stack has another main purpose, that is, the space required to configure the subprogram's area variables (l〇cal variables). The method of de-private configuration space is to subtract the amount of space required for the area variable from the stack indicator. The region variable is then loaded into the instruction fetch, where the target address of the load instruction is the relative address calculated from the stacking metric. Therefore, the poor information reported may be on the same cache line as the recently pushed data. In addition to this, the program may execute a load command to retrieve the parameters of the heap for the calling program. The pushed parameter is likely to span two cache lines, that is, one of the push commands will cause the stack indicator to point to the next cache line, as described in steps 618 through 628 of Figure 6. Thus, some parameters - will be in the cache line of the second record unit at the top of the heap cache 124, and ^ is not the topmost record bit, the money is recorded in the __ three record sheets - and so on. Thus, in one embodiment, the loader from the stack cache 124 takes advantage of this and checks the stack cache 124 to see if the loaded data is present at the top two record units. By directly checking the two recording units at the top of the 彳, the traditional cache memory row decode operation can be avoided, saving one clock cycle. In addition, in an embodiment, the guess load can save another clock cycle by using the virtual address 334 of the load instruction instead of the physical address 33^ to compare the address tags to see the load data. Whether there are two record units at the top. If the virtual address matches one of the top two record units, the load data is likely to be in the record unit just hit, although ^ is not determined because it may be virtual aliasing. In an embodiment of the microprocessor 42 1294569 14394 twf.doc/m machine 100, the stack cache 124 provides error data during guess loading because the operating system switches tasks and thus updates memory paging information (paging Information), resulting in a false virtual address match. In a consistent embodiment, particularly when using a stack address segment register, such as an SS register of SS architecture, processor 100, stack cache 124 is guessing load time. Error data is provided, because the stack segment register is updated, affecting the effective address calculation, and may cause false virtual addresses to match. # Although Figure 8 illustrates an embodiment in which the top two record units of the Stack Cache 124 are checked as candidates for guess loading, the guess loader is not limited to checking a certain number of topmost record units. Others are also included in this, where the guess load checks for a different number of topmost record units. At step 802, the instruction translator 106 of Fig. 1 decodes a load instruction, and the instruction scheduler 〇8 sends the load instruction to the load unit of the execution unit U4. Then the load unit will generate a true value in the loadjnstr signal 346 > of Figure 3. Next, at step 804, the address generator 306 calculates the source virtual address 334 of the load instruction. Next, at step 806, the two comparators 312 of FIG. 3 compare the virtual address 336 generated in step 804 with the virtual sc_tag[l:0] signal 224' of FIG. 2 to produce the VA-match[l: of FIG. 0] Signal 362. Next, at decision step 808, control logic 302 checks SeJV[ESI[l:〇] signal 222 and VA_match[l:0] signal 362 to determine 43 I294m, 最c/m stack cache 124 topmost Does any of the two record units have the source virtual address 334 of the manned command conforming to the stack cache 24? The top part of the two record units of the address label class virtual part = mountain is the "child" virtual address 334 whether to hit the top of the stack cache (four) cut @ record unit. If yes, the rest will enter step 812 Otherwise, it enters step 824 of Figure 8A. Also I, r ί ^ 812 ' In response to the true value of 1〇ad-instr signal 346, control one, ^ path 302 will be in spec-sc-1 〇ad-fine, such as The signal 391 generates a value 'to enable the multiplexer 412 to be selected in the decision step _, which includes: a valid address tag 204 of the source virtual address 334 of the command of the port, and two cache lines of the stack cache 124 ( That is, % one of her [one of the gang signals m, to provide the signal 422 of Figure 4. In addition, multiplex = 404 will select the bit of the physical address from the cache, line 422 * [5:2] The double word group of ^ is supplied to the signal 424 of Fig. 4. Moreover, the control logic 3〇2 will generate a value in L1_mux of Fig. 3, so that the multiplexer of y selects the input 424 to pass The bus bar m is provided to the manned unit of the row unit 114 to read the supply age, and the write back will load the input 424 into the register group 112. Loading the register of the binary Πα. As can be seen from the graph SA, the data is a speculative provisioning unit. The guess is because the loading instruction generated at the physical address 336 will not be confirmed in the following step 81^. The source entity address, whether or not, is supplied to the address of the load data of the load unit from the top two record units of the stack cache 124. Since the step 8 detects that the virtual address 334 hits The top two records 44 1294569 14394 twf.doc/m of the stack cache m, the control logic 302 will generate a true value at the SCJlit signal 389 to provide the load unit to the execution unit 114. Next, at step 814 The translation buffer 308 will generate the source entity address 336 of the load instruction. Next, at step 816, the two comparators 314 of FIG. 3 compare the entity address 336 generated by step 814 with the entity sc_tag[i:〇 ] Signal 224 'At step 812, the loaded data is outputted speculatively to produce

The corresponding PA-match[l:0] signal 364 is generated. Next, at decision step 818, the control logic circuit 302 checks the PA-match[l:0] signal 364 corresponding to the record unit of the stack cache 124 that provided the load data at step 812 to determine the load instruction. Whether the source entity address 336 is equal to the physical address label 2〇4 of the above-mentioned recording unit, that is, whether the physical address 336 hits the recording unit. If the source address 336 of the loaded instruction hits the guessing record unit 1 of the stack cache 124, the flow ends, that is, the guess loader provides the correct pop-up data. Otherwise, the flow proceeds to step 822. At step 822, control logic circuit 3 会 2 will generate a true value at the exception event signal 39 < cause the microprocessor to execute the exception event handler for the if, human program to provide the error (four) of the flight. (4) Event Processing (4): Make the load instruction _ correct (4). In the implementation of the money, the exception = = ί4 Ϊ from the non-stack cache 122 or system memory or L2 cache to load the correct material. Flow ends at step 822. (4) ΓίΓ知, will be described later with reference to Figure 11, the guessing loader of Figure 8Α enables the manned personnel to supply manned instructions, can be transferred to ^ 45 c / m 12945 _ _ take the memory faster on several clocks cycle. In step 824 of Figure 8B, translation of the scratchpad 3〇8 will result in the source entity address 336 of the load instruction. Next, at step 826, the comparator 314 of FIG. 3 compares the entity address 336 generated by step = 4 and the entity sc_tag [15 call signal 224 corresponding to the sixteen record units of the stack cache 124 to generate a PA_match. [15:0] Signal 364. Next, at step 828, control logic 302 checks s:JV[ESI[15:0] signal 222 and PA-match[15:0] signal 364 to determine if stack cache 124 has a record unit status of Valid, and whether the source entity address 336 of the load command is equal to the physical address tag 204 of the valid record unit, that is, whether the physical address 336 hits the stack cache 124. If so, the flow proceeds to step 832, otherwise it proceeds to step 834 of Figure 8C. In step 832, in response to the true value of l〇ad-instr signal 346, and in response to the source of the load instruction virtual address 334 misses the top two records of the stack cache 124, and the source entity that responds to the load instruction The address 336 hits the stack cache 124, and the control logic circuit 3〇2 generates a value in the normal-scjoad-mux-sel signal 393, causing the multiplexer 408 to select the source that has been determined in step 828, which is equal to the source of the load instruction. The effective physical address of the λ body address 336 is one of the sixteen cache lines of the stack cache 124 (ie, sc_data[15:0] 226) to round the signal of FIG. 428. In addition, multiplexer 406 will select the doubleword specified by bit [5:2] of physical address 336 from cache line 428 to input 46 1294569 14394 twf.doc/m for signal 426 of FIG. Moreover, the control logic circuit moves a value in the L1-mux-seUfU tiger 395, so that the multiplexer 4〇2 selects the load 426 and supplies the load order to the execution unit via the bus 138 to supply the load command. Write back to the unit ιΐ6 later will be the signal 426: the manned to the manned command specified, the map of the register group ι ΐ 2 of the field register. Since the step US detects that the physical address 336 hits the heap: the capture 124' control logic circuit 3〇2 generates _^ at the sc-(10) signal 389 to provide the load unit to the execution unit 114. The process ends at step 832w. This can be seen later, as will be explained in detail with FIG. 12, the normal loading procedure of the stacking cache 124 of FIG. 8B allows the loading data to be supplied to the loading-曰7, which can be compared to a conventional cache memory, for example. The non-stack cache 122, . is fast on at least one clock cycle. At step 834 of FIG. 8C, the non-stack cache 122 receives the index portion of the generated physical address 336 of step 82 of FIG. 8B (index_(4), and then performs column decoding on the index to select one in the overlay buffer 122. Columns, or a set of ways. Next, at step 836, the non-stack cache 122 compares the high-order portion of the physical address 336 generated by step 824, or the label portion, and the set selected in step 834. Each block (the physical address tag of the wa force. Next, at decision step 838, the non-stack cache 122 checks the comparison result of step 836 and the valid bits of the selected block to determine the physical address of the load = 336 whether to hit the non-stack cache 122. If hit, the process will proceed to step 842, if not, the process will proceed to step 844. 47 twf.doc/m 1294569 In, the non-stack cache 122 will be from it The bearer data hit by the physical address 336 provides manned data. The flow ends at step 842. At step 844, the non-stack cache is missed because the (four) coffee & loaded physical address 336 misses the non-stack cache 122 122 will be configured in its towel - a record Bit 'to load the cache line where the physical address 336 of the missed load instruction is located. Down, in step 846, the non-stack cache 122 will cache from the system memory or the first level, and the cache will be missed. The line loads the record unit configured in step 844. Next, at step 848, the non-stack cache 122 will provide the load data from the cache line loaded in step 846. The flow ends at step 848. In an embodiment, Steps 834 through 848 of Figure 8C are performed in the manner of conventional cache memory. That is, Figure 8C illustrates the conventional non-stack cache 122, the tradition of missing the stack cache 124 when loading the physical address 336 Referring to Figure 9, Figure 9 is a flow diagram of a deposit procedure for entering the first stage cache 126 of Figure 1 in accordance with the present invention. The flow begins with step 9: 2. At step 902, the instruction translation of Figure 1 The device 1〇6 will decode the store instruction. The instruction scheduler 108 will send the store instruction to the storage unit of the execution unit 114. Then, the storage unit will generate a true value in the storejnstr signal 348 of Fig. 3. Next, in the step 904, the address generator 306 calculates the storage instruction The target virtual address 334. Next, at step 906, the translation buffer 308 will generate the target entity address 336 of the store pointer f.doc/m. Next, at step 908, the comparator 314 of FIG. The physical sc_tag[15:0] signal 224 corresponding to the physical address 336 generated by the step 906 and the sixteen recording units of the stack cache 124 is compared to generate a PA-match[15:0] signal 364. Down, in decision step 912, the control logic circuit 3〇2 checks the scJV[ESI[l5:〇] signal 222 and the PA-match[15:0] signal 364 to determine

Whether the fixed stack cache 124 has a record unit whose status is valid, and whether the target entity address 336 of the store instruction is equal to the stack address cache 124, a valid record unit physical address label 2〇4, that is, the entity Whether address 336 hits stack cache 124. If so, the process proceeds to step 914, otherwise step 916 is entered.

In an external step 914, the stored data is placed in the valid record unit of the stack cache 124 where the address matches in the decision step 912, and the stored data is stored in the bit address of the physical address 336 through the s^_:rite_data signal 216 [5: 2] The double word shift value of the specified cache line 206. If necessary, the MESI status 2G2 of the topmost recording unit is updated to the modified state by, for example, the se-writeJvl ESI signal 212. The stored data comes from the location of the scratchpad or #存忆。. For example, if the deposit instruction is an x86 instruction, the general purpose register is the data source, and the memory is stored in the temporary storage, and the source of the ν instruction is +& Device. Since step 912 detects that physical address 336 hits 隹" control logic circuit 3 〇 2 will be at %, signal-produced, supplied to the storage unit of execution unit % 114. The remaining step 914 49

Jm is over. In step f 16, the label portion of the entity address phantom 6 generated in step 〇6 is compared with the non-heap® cache 122, the physical label of each block of the selected set of the index portion of the physical address 336. . Next, at decision step 918, control logic 302 checks non-sc-hit apostrophes 366 to determine if the target entity address 336 of the store instruction hits non-stack cache 122. If it is hit, the flow proceeds to step 922, otherwise it proceeds to step 924. At step 922, the deposited data is stored in a column of non-stacked caches 122 that are valid and equal in the selected set of (four) 918. The process ends at step 922. At step 924, since decision step 918 determines that the storage entity address 336 misses the f-stack cache 122, the non-stack cache 122 configures therein a record unit to accommodate the cache line where the entity address 336 of the instruction is located. Next, at step 926, the non-stack cache 122 will fetch from the system memory or the first level, and load the previously missed cache line into the record unit of the non-stack cache 122 configured in step Μ#. Next, at step 928, the non-stack cache 122 stores the deposited data into the cache line loaded at step 926. The process ends at step 928. In one embodiment, steps 902 through 906 and steps 916 through 928 of FIG. 9 are all performed in a conventional cache memory. That is, steps 902 through 906 and steps 916 through 928 are conventional deposit procedures performed on the conventional non-stack cache 22 when the address 336 misses the s: cache 124. 50 1294 Huan (5) m Gu Chuan, Fig. 10疋 According to the present invention, as shown in Fig. 5, the stacking cache 124 performs a fast pop-up phase. Figure 1G includes four columns, labeled i to 4, and the four pulses corresponding to the microprocessor ι〇〇 also include five rows, each representing the action of the microprocessor ιβ. Or the result. The square of each row and column intersection of Figure 1G is "popped" to indicate where the pop-up instruction is located in the g-line of microprocessor 100. In the clock cycle 1, according to the first column of Figure 1G, Figure! The load unit of the execution unit 1H will generate a true value in the p〇p_instr signal 344 of FIG. 3 to request pop-up information to the pop-up instruction, as shown in the step of FIG. In the clock cycle 2, according to the second column, the cache line of the topmost recording unit of the cached 124 i-offsl signal 396 is supplied to the pop-up command, as shown in step 5〇4 of FIG. More specifically, the multiplexer 318; will provide the sixteen double-words in the sc_data[0] 226 from the topmost recording unit of the stack cache 124, and select the double-word 398 specified by the electronic signal 396. And the multiplexer will choose the electric Yang, enter the second 8. In addition, the stack cache 124 will be notified by ^(10) signal loading. The early TL has a pop-up command hit. That is to say, the stack cache will notify the manned unit that the data of the pop-up instruction is located in the stack cache 124. As previously explained in conjunction with Figure 5, the guess of the s〇it signal 389 'because it has not been determined that the bomb generated by the lion 3 will be later = the source address will be equal to the cached 3 will be cached from the stack. The top record unit of 124 is provided to the address of the manned unit (4) out of the data. In the example, the sc-hit job 389 informs the loading unit that a pop-up instruction occurs. ^ 51 I2945369fd〇c/m A, will pass through the figure π, MbSI[0] w double certificate, so at the top of the recording unit When it is valid, the stack cache 124 will notify the loading unit that there is a bullet to produce a scarf. That is, although the control logic circuit 302 does not confirm the address match before notifying the pop-up hit, at least confirms that the topmost record unit of the stack cache m is valid.曰 In clock cycle 2, according to the virtual address 334 of the third column of Figure 3, just like the pop-up iUri ’ according to the fourth column, the translation of the temporary storage area will produce == = = step 5 of circle 5. _Stacking cache m == control logic circuit 302 will detect the step to the 524 incorrect pop-up data, as shown in Figure 5, 13 quickly pop-up instructions to the pop-up instructions, faster than the traditional memory The clock cycle, the comparison chart 10 and the figure that will be described later can make the first-level data cache 126 provide the cost = the quick pop-up and the instruction-free cache 0 ▼ · the tour address 336 a - rr m The double word of the data, the position [5:2] is used to provide the pulse of the week ^, not = pulse = ^. 396, and the data is in the line of the day, marked as a timing chart. Figure η package. Period. Figure 11 also includes six columns, from which the four clocks of the processor have not been made or result. Figure u is a box of each of the processors 1GG, not blank, male 52 1294 4twf.doc / m "load" to indicate the load command in the microprocessor 1 () The location in the pipeline. In the clock cycle 1, according to the first column of FIG. 11, the loading unit of the execution unit 114 of FIG. 1 generates a true value in the i〇ad-instr signal 346 of FIG. 3 to request loading of the data into the load instruction. This is shown in step 8〇2 of Fig. 8. In clock cycle 2, according to the second column, address generator 306 calculates virtual address 334 of FIG. 3, as shown in step 804 of FIG. In clock cycle 3, according to the third column, comparator 312 of FIG. 3 performs a virtual tag comparison to generate a VA-match[1:〇] signal 362, as shown in step 806 of FIG. In addition, the control logic circuit 3〇2 generates a spec-scjoad-mux-sel signal 391 according to the VA-match[l:0] signal 362 and the scJVIESI[l:0] signal 222 of FIG. 2, as in step 812 of FIG. Show. In addition, the stack cache 124 will notify the load unit with a sc-hit signal 389 that a load command hit has occurred, as shown in step 812 of FIG. That is, the stack cache 124 notifies the load unit that the data required to load the instruction is located on the stack cache 124. As previously described with respect to Figure 8, the hit indication is guessed because the source entity address 336 of the load instruction generated during clock cycle 3 has not been determined to be equal to 124 k from the stack cache at clock cycle 4. Supply the address of the poor material loaded in the early yuan. In clock cycle 3, according to the fourth column, the translation buffer 308 will generate the source entity address 336 of the load instruction, as shown in step 814 of FIG. In clock cycle 4, according to the fifth column, the load data is provided to the load unit as shown in step 812 of FIG. More specifically, the multiplexer 412 of FIG. $ selects two cache lines of 53 1294569 14394 twf.doc/m sc-datanw] signal 226 according to spec-sc-load-mux-sel signal 391. If the multiplexer 402 is selected according to the bit [5:2] of the physical address 336, the input 424 is selected. In addition, and in the clock cycle 4, according to the sixth column, it is detected that the stack cache 124 provides the work / 2 will be detected to 822. Wrong and loaded data. As can be seen from the comparison of Fig. 11 and Fig. 13 which will be described later, the guess: causes the first level data cache 126 to provide data to the cache memory of the load instruction for several clock cycles. Referring to Fig. 12', Fig. 12 is a timing chart of the normal load program according to ==124, and the second = program. Figure 12 consists of five rows. The private processor loo ## ^ ^Ν ί should be in the second five columns of the micro-processor, the squares of the respective generations, not blank, β ί, fruit. Figure 12: Each line of intersections is the same as in the pipeline of the processor. 'The instruction is not loaded in the micro 114 load! 'According to the first column of 81 12', the execution unit of Figure 1 generates the true value by the first letter of the first name ^ Figure 3, giving the true value' to the load instruction, just like The steps of Figure 8 are shown. In the temple cycle 2, according to the second column

The virtual address 334 is as shown in the step of _8. H truncation 3 ‘translating temporary storage area 308 according to the third column' produces a binary source entity address 336' as shown in step 824 of Fig. 8. According to the fourth column, the comparator 314 of FIG. 3 will enter 54 12943⁄43⁄4 4twf.doc/m row physical label comparison to generate the pA-match[15:〇] signal 364 ' of FIG. 3 as shown in FIG. Step 836 is shown. In addition, the control logic circuit 3〇2 generates a normal-sc"〇ad-muX-Sel signal 393 according to the PA_match[15:0] signal 364 and the sc_MESI[15:0] signal 222 of FIG. 2, as shown in FIG. Step 832 is shown. In addition, the stack cache 124 notifies the load unit with a sc-hit signal 389 that a load command hit has occurred, as shown in step 832 of FIG.

0 In clock cycle 5, according to the fifth column, the load data is provided to the load unit as shown in step 832 of FIG. More specifically, the multiplexer 408 of FIG. 4 selects one of the sixteen cache lines of the sc-data[15:〇] signal 226 according to the normai_sc_i〇ad-mux-signal, the multiplexer. 406 will select the correct double word based on the bit [5:2] of the physical address 336, and the multiplexer 402 will select the input 426. Comparing Figure 12 with Figure 13 described later, the normal loader program = causes the first level data cache 126 to provide data to the load instruction, which is faster than conventional cache memory.

% > Figure 13, Figure 13 is a timing diagram of the loading procedure from the non-stacked cache 22, as depicted in Figure 8 of the present invention. Figure 13 includes = marked as! Up to 6, the six clock cycles corresponding to the microprocessor ^ 3 also includes six columns 'each representing one action of the microprocessor, Ό . The square of each row and column in Figure 13 is either blank or factory ^". To indicate that the load instruction is in the pipeline of the microprocessor, the execution unit of Figure 1 is in clock cycle 1, according to the first column of Figure 13, 55 1294569 14394twf.doc/m =1, loading a few sessions The true value of the 1〇ad-instr signal 346 of FIG. 3 is generated to request the manned data to the manned command, as shown in the steps of FIG. In the clock cycle 2' according to the second column, the address generator traverses the virtual address 334 of FIG. 3 as shown in step _ of FIG. In the clock cycle 3', according to the third column, the temporary storage area is translated, and the source entity address 336 of the load instruction is generated, as shown in step 824 of FIG.

In clock cycle 4, according to the fourth column, the non-stack cache 2 performs conventional column decoding based on the index portion of the physical address 336, and reads data from each block of the set specified by the result of the column decoding. In clock cycle 5, according to the fifth column, the non-stack cache 122 will use the physical address, and the tag portion is compared with the ▲ sign entity class bid b of each column of the selected set. Based on the standard rail comparison, the wire and the effective position of each shed 70, the non-stack cache 122 generates a way sdect signal to select a valid and valid barrier.

In the clock cycle 6, according to the sixth column, the non-stack cache 122 selects the cache line specified by the A number in the column, and selects among the cache lines just selected according to the low bit of the physical address 336. The correct double word group. In addition to the examples illustrated in Figures 10 through 13, the present invention also encompasses other embodiments in which the various functions previously mentioned, such as address comparison and multiplexing, incorporate different clock cycles, and The fast pop-up, guess load, normal load, and loader from the non-stack cache 22 are not limited to the above embodiments. As can be seen from the above description, the advantage of the stack cache 124 being separated from the non-stack cache 122 is that compared to the conventional 56 1294 f.doc/m single-cache memory that does not distinguish between stacked and non-stacked access, The capacity of the first level data cache i26 can be effectively increased, and the access time of the first level data cache 126 is not increased. In addition, since the non-stack cache m does not store stacked data, the program-based access non-stack cache 122 is more efficient than the same size of conventional cache memory. In addition, the stack cache 124 can speed up most of the pop-up finger =, this is the first of the four ships, the required amount of money can be = at the top of the stack cache 124, because the top information is very ^ The data that is pushed into the stack cache 124, that is, the latest resource cache 124 will guess to provide pop-up data before deciding whether the pop-up address actually hits the stack cache 124. Further, the stack cache can be Accelerate the age of most of the scales, which is also due to the first-out, the information is likely to be located near the stacking speed ^ ^ one or more cache lines. So 'stack cache Before the comparison of the addresses to determine whether the loaded data exists, it is based on the virtual address comparison, from the top of the record unit - guess that this makes the stack cache 124 in most cases: = more for loading the tribute 'Because there is no need to wait for the virtual address to be translated into entity = j to compare the physical address. Finally, if the loaded virtual address is not tested, 早 λ 2 ί early bit 'so that loading data can't guess 彳' stacking fast Take 124 will be killed at the manned physical address 2 = 124 when the loading data is provided. If the loaded physical address is not you 曰 f,, 124 ' is provided by the non-stack cache 122 to load the data. Yi 2: 2 ί take 124 time to read the data will The change, the more the clock cycle required for the more action, the one of the time changes of the original 57 1294569 14394twf.doc / m because the read stack cache 124 is the bit 1 of the stack 1 within the stack cache 124. 1 another variation reason 1400 ^ square hold ^ 14, Figure 14 is a pipeline microprocessor 100 according to the present invention, port θ f / ° microprocessor _ similar to the microprocessor of Figure 1 β /, 疋政处理机触The first-level data cache 14G2 does not include the heap=take 124. The first-level data cache of Fig. 14 is loaded with a 1402 fast pop-up, the details will be described later. - The eye is referenced to Fig. 15, which is a diagram according to the present invention. Figure 14 is a block diagram of the first-level shell material cache 1402. Several of the components are similar to the corresponding ones of Figure 3, and the functions are similar. Similar components use the same label. More specifically, the data is fast. Taking 14〇2 includes address generator 3〇6, responsible for receiving operand 332 and generating virtual address 334; translation temporary storage The area 3〇8 is responsible for receiving the virtual address 334 and generating the physical address 336; the arithmetic unit 304 is responsible for receiving the addition signal 382, the decrementing signal 384, and the incrementing signal 386, and generating the under-bit signal 388 and the overflow signal 392; The multiplexer 316, the multiplexer 318, the fp_0ffset register 322, the add-sp-val signal 394, the bit [5:2] of the stack indicator register 152, the output signal 372, and the fp-offset signal 396, except for the differences described below, the above elements function similarly to the elements of the same reference numerals in FIG. The data cache 1402 also includes a control logic circuit 1502 that functions in some respects similar to the control logic circuit 302 of FIG. Control logic circuit 1502 receives pushjnstr signal 342, pop_instr signal 344, and add_sp_instr signal 352 similar to control logic circuit 302. Control logic circuit 1502 produces control signal 368 similar to that of Fig. 3 of 58 1294569 14394 twf.doc/m. Control logic circuit 15 产生 2 generates an exception event signal 399 in response to a fast bullet sequence error, except for the difference described below, which is like the corresponding signal of FIG. The data cache 1402 also includes a storage array (gamma zero dement array) 1504' for mechanical recording, from their health label and cache state 'for example MESI status. In the embodiment of Figure 15, storage array 504 has N"solids" or a collection, and four rows, or blocks. It is also said that 'Linku takes 1402 is a four-block set-associated cache. However, the present invention is not limited to a cache with a certain number of holds. In the implementation, the cache line size stored in the storage directory is 64 bytes. The data cache 1402 also includes a column decoder (r〇w such as (3) plus .15〇6. The column decoder 1506 receives the specified storage array! The row signal of one of the N columns of 5〇4 is 1552. The decoder 15〇6 will be in the ^1 number of signals [Nl:〇] 1542, the one specified by the signal 1552 = true value. Then, the storage array 15〇4 will output the above true reading. Signal [team 1: : 15 | 1542 specified column signal 1594. That is to say, the cache line data, address label, and mesi bear of the selected parent 一J will be output on signal 1594. In the embodiment of FIG. 15, signal 1594: the face will take four cache lines each containing sixteen double blocks, and the address tag 1574 corresponding to each cache line and the valid bit in the MESI state. The data cache 1402 also includes a multiplexer 1528 coupled to the storage array 15〇4, four wheel-in ends. The four inputs of the multiplexer 1528 are each 59 1294 total 4 twf.doc/m self-receiving storage array 1504 The output of the four cache lines 1594. The studio 1528 selects four cache lines according to the control input 1596, wherein the output is At signal 1592, the selected cache line is provided via signal 1592 to multiplexer 318, which provides a double word on bus bar 138 based on fp_0ffset signal 396. Data cache 1402 also includes control logic circuit 15 〇 2 The fastjop nickname 1564. The control logic circuit 15 〇 2 will generate a true value in the fast j 〇 p signal 1564 in response to the true value of the p 〇 p - 匕 batch signal 4, from the data cache 1402 for a quick pop-up operation. The material cache 1402 also includes a storage unit stack, or a recording unit stack, called an fP-row stack 1516, coupled to the control logic circuit 15=. The fp-row stack 1516 is composed of a plurality of storage units, each storage location A value points to a column of the storage array 1504. In one example, each unit of the fp-row stack 1516 stores one bit, where N is the number of columns of the storage array 1504. fp a plurality of row stacks 1516 The storage unit constitutes a stack, including the topmost recording unit 15M to store the most recently pushed column value (row vaiue), which is provided by the control logic circuit 1502 via the new-row signal 1554. That is, new-r The ow ring number 1554 will indicate the column of the cache line containing the most recent push command data in the storage array 1504, which will be described later in detail. The column of the most recent pusher data is stored to allow the data to be cached. The 1402 performs a quick pop-up procedure, which will be described later in detail. The electric---stack (5) 6 also controls the logic circuit 15〇2 to receive the push-r〇w signal 1562. When the control logic circuit 1502 generates a true value in the push-row signal 1562, the _ heap 12945 splicing 1516 will translate down one recording unit, that is, the bottom recording unit will move out of the fp_row stack 1516, and each of the remaining recording units The contents of the previous record unit will be received, and the contents of the new_r〇w signal 1554 will be written to the topmost record unit of the fp-row stack 1516. The fp_row stack 1516 also receives the p〇p_r〇w signal 1558 from the control logic circuit 1502. When the control logic circuit 15〇2 generates a true value in the p〇p_row signal 1558, the fp_row stack 1516 will shift up one recording unit, that is, the topmost recording unit will move out of the fp_r〇w stack 1516, The remaining parent records unit will receive the contents of the next record unit. The data cache 1402 also includes a multiplexer 1512 having two inputs coupled to the fp-r〇w stack 1516. An input of multiplexer 1512 receives the contents of the topmost recording unit 1514 of fp-row stack 1516, designated as fp-row signal 1556. The other input of multiplexer 1512 receives an index portion of physical address 336 from translation buffer 308, or column selection portion 1548. In one embodiment, index 1548 is the lower address bit of physical address 336. If fast 〇p signal 1564 is the value, multiplexer 1512 will select fp-row signal 1556 for output to column signal 1552, to column decoder 15〇6; otherwise, multiplexer 1512 will select index 1548 to Output to column signal 1552. The data cache also contains another storage unit, or a recording unit, which is called fp-way stack 1534, and is coupled to the control logic circuit 〇2. The fp-way stack 1534 consists of multiple storage units, each of which has a value of $1, pointing to a block that stores _15G4. In the embodiment of Figure 15, each solution of the fP-way stack 1534 stores two bits 1294 and withdraws ^twf.doc/m 以 to indicate one of the four columns of the storage array 1504. The fp_way heap, 1534's multiple storage units form a stack, including the topmost recording unit 1532, to store the most recently pushed block value (way vahie), which is provided by the control logic circuit 1502 with the new one way signal 1582. In other words, the 'new-way signal 1582' will indicate that among the columns specified by the new one row signal 1554, the cache line containing the data of the most recent push command is stored in the storage array 15〇4, which will be detailed later with FIG. Description. Store the block containing φ with the most recent push data, and let the data cache 1402 execute the quick pop-up procedure, which will be described later. The fp-way stack 1534 also receives the push-way signal 1588 from the control logic circuit 丨5〇2. When the control logic circuit 15〇2 generates a true value in the push-way nickname 1588, the fp-way stack ι534 will go down: pan one record unit, that is, the bottom record unit will be shifted out* Qiao-way Hefeng I534 Each of the remaining recording units will receive the contents of the previous recording unit, and the contents of the new-way signal 1582 will be written to the topmost recording unit 1532 of the fp-way stack 1534. The fp-way stack 1534 also receives the p〇p-way signal 1586 from the control logic circuit 15〇2. ^ _ control logic circuit 1502 generates a true value at p〇p-way signal 1586, and stack U34 translates one record unit upwards, that is, the topmost record unit is shifted out of fp-way stack 1534, and each of the remaining records The unit will receive the contents of the next record unit. In one embodiment, the fp-row stack 1516 and the fP-Way stack 1534 are comprised of a single stack in which each record unit stores a column value and a column value. The data cache 1402 also includes a multiplexed 62 c/m 1294 shed _ 1526 with two inputs coupled to the fp-way stack 1534. An input of multiplexer 1526 receives the contents of the topmost recording unit 1532 of fp-way stack 1534, designated as fp-way signal 1584. The other input of multiplexer 1526 receives a normal-way-select signal 1578. If the fast ") 〇p signal 1564 is true, the multiplexer 1526 will select the fp-way signal 1584 for output to the mux select signal 1596, which is provided to the multiplexer 1528, otherwise the 'multiple mode 1526' The normai-way-seiect signal 1578 is selected for output to the multiplex selection signal 1596. In a real example, the parent 5 recording units of the 'Φ-way stack 1534 and the fp_r〇w stack 1516 all contain a valid bit, and the fastj) 〇p signal 1564 is determined by the topmost recording unit 1514. And the most significant bit of the top record unit 1532 is the result of a logical OR operation. That is to say, although the control logic circuit 1502 does not check whether the pop-up source address is consistent or not before performing the fast pop-up, at least φ-Γ is first checked (the topmost recording unit 1514 of the ην stack 1516 and the fp-way stack ι534) The topmost seven-record unit 1532 is valid. In this embodiment, each time the fp way stack 1534 and the fp-row stack 1516 are popped up, after the upward shift, the effective bit of the bottommost record unit is set to false. Value (false) The data cache 1402 also includes a way select generator 1524 that is coupled to the control logic circuit 1502. The column selection generator 1524 receives each of the selected columns from the storage array 1504. The flag 1574 and the valid bit 1576. The column selection generator 1524 also receives the address tag portion 1546 from the entity address 336 of the translation buffer 308. The bar selector generator 1524 compares the entity address tag 1546 with the storage array 63. F.doc/m 1504 outputs each tag 1574, where the physical address tag 1546 may be from a pop-up, push-in, load, or store instruction. If the address tag 1574 is One is equal to the physical address tag 1546, and the corresponding valid bit 1576 indicates that the address tag 1574 is valid, and the block selection generator 1524 generates a true value at the cache-hit signal 1572 of the φς: supply control logic circuit 1502. In addition, the column selection generator 1524 outputs the value of the valid and equal column, that is, the column hitting the storage array 1504, to the normal one way-select signal 1578, and supplies it to the control logic circuit 15〇2 and the multiplexer. 1526. The data cache 1402 also includes a check logic 1508 coupled to the storage array 15〇4. The check logic 15〇8 receives the physical address 336, the fastjpop signal 1564, the fp_row signal 1556, fp— The way signal 1584, the address tag 1574, the valid bit 1576, and the fp__0ffset statement 396. The check logic circuit 1508 will check to determine if the data provided to the pop-up instruction is correct in the fast pop-up procedure. The check logic circuit 1508 will Determines whether the correct column values and column values provided by fp-row signal 1556 and fp-way signal 1584, respectively, are used in the fast pop-up procedure from storage array 150. 4 Select the correct cache line to provide the correct pop-up data. In one embodiment, the check logic 1508 compares the value of the fp-row signal 1556 in the fast pop-up procedure, and the block specified by the fp-way signal 1584. Address tag 1574. In one embodiment, the check logic circuit 1508 also compares the value of the fp_r〇w signal 1556 used in the fast pop-up procedure with the corresponding bit of the physical address 336. In one embodiment, the check logic 1508 also compares the value of the 64 Ϊ 294569 l4394 twf.doc/m Φ~offset signal 396 used in the fast pop-up procedure with the corresponding bit of the physical address 336. The check logic circuit 1508 also confirms that the valid bit 1576 of the block specified by the fp-way signal 1584 indicates that the cache line taken in the fast pop-up procedure is valid. If the cache line described above is not active or the correct cache line is not taken, the check logic circuit 15 8 generates a dummy value at the fp-check signal 1544 for supply to the control logic circuit 15〇2. Otherwise, check logic circuit 1508 will generate a true value at fp-check signal 1544 for supply to control > logic circuit 1502. Referring to Figure 16, Figure 16 is a flow diagram of a quick pop-up procedure from the data cache 1402 of Figure 15 in accordance with the present invention. The process begins with step 16〇2. At step 1602, the instruction translator 106 decodes the pop-up instructions, and the instruction scheduler 108 sends the pop-up instructions to the loading unit of the execution unit 114 of FIG. The load unit then generates a true value at p〇p-instr signal 344. Next, in step 1604, in response to the true value of the p0pjnstr signal 344, the control logic 15 〇 2 will generate a true | value at fastj) 〇 p signal 1564. Therefore, the multiplexer 1512 selects the fpjr〇w signal 1556 to output to the column decoder 15〇6 via the column afU tiger 1552. Then the column decoder 15〇6 will generate a true value above the one specified by the fp-row signal 1556 among the masters sfl唬[N-l:〇] 1542. The storage array 15〇4 then outputs a list of true read signals in the output signal 1594. In response to the true value of the festjop signal 1564, the multiplexer 1526 will select the power signal ^!^4 to provide the multiplexer 1528 via the multiplex selection signal 1596. The multiplexer 1528 then selects the cache line ' from the 65/m I294m,d〇c block specified by the fp_way signal 1584 to output the signal 1592. The multiplexer 318 is combined with ~. The cache line 1592 of the port 1528 selects the correct double word J攸: Finally writes back: -^ 70 114 the manned unit to provide the temporary register specified by the pop-up instruction in the pop-up instruction 112. For example, for the temporary = 3RET command, the pop-up data will be loaded into the register group 112 L FAV day-day register. As another example, if the pop-up command is X86's LE=VE ‘order, the pop-up data will be loaded into the EBP register in the scratchpad group 112. As another example, if the pop-up command is a p〇p command of χ86, the data will be loaded into the scratchpad group 112, and the PQp command specifies the temporary state. As can be seen from Figure 16, the data is provided to the loading unit speculatively. The guess is because the pop-up instruction source address that would be generated at the physical address 336 in step 1616 has not been determined, which would be equal to the recording unit specified by the fp-row signal 1556 and the fP-Way signal 1584 from the storage array 15〇4. Provide the address of the popup data to the load unit. Next, in step 1606, the control logic circuit 1502 generates a true value at the increment signal 386, and then the arithmetic unit 3〇4 increments the fp_〇fftet signal 396, and then outputs the incremented value to the signal 372, and the control logic circuit 1502 The multiplexer 316 is selected by the control signal 368 to load the value into the fp_〇ffset register 322. Next, at decision step 1608, control logic circuit 1502 checks for overflow signal 392 to determine if the incrementing of step 1606 caused the fp-〇ffset register 322 to overflow. That is to say, the control logic circuit 1502 66 I2945l ^ twf.doc / m = will cause the heap 4 indicator 152 to point to the next - cache, the second process will enter step 1612, otherwise it will enter step 1614. Step 1612, the control logic circuit 15 1558 generates a true value, with a strong φ f 曰 〇 P〇P-r〇w tiger pressure king value Μ no fp-r〇w stack 151 bits, control logic circuit 15 〇 2 ★ Heli n ^ has recorded as early as the P叩 oneway signal 1586 to produce the real top town P, ay stack 1534 the top record unit. This is for 2 ......money memory cache, because in the storage array 15〇4 animals, the topmost recording unit i5i4 and Φ-heap® 1534 6^3⁄4 top 1532 of the stack 1516 by fp- The previous double word group of the cache line stored in the recording unit 1 is being ejected by the pop-up command to pop up the system. In the embodiment, step 1612 is performed after step 1618 described later. In another embodiment, for the steps! The values of the deleted fp-row signal 1556 and the fp-way signal 1584 are saved and left for use in step 1618. Next, at step 1614, the address generator 306 calculates the source virtual address 334 of the pop-up instruction. Next, at step 1616, the translation buffer 308 will generate the source entity address 336 of the pop-up instruction. Next, in step 1618, the check logic circuit 15 8 compares the corresponding portion of the physical address 336 generated in step 1616 with the address tag 1574 selected by the fp_way signal 1584, and compares the corresponding portion of the physical address 336 with The fp-row signal 1556, and compares the corresponding portion of the physical address 336 with the fp_〇ffset signal 396' and checks the valid bit 1576 selected by the fp_way signal 1584 to generate a control logic circuit 67 I294H〇c/m 1502. Fp_check signal 1544. Next, at decision step 1622, the control logic circuit 15〇2 checks the fp-check signal 1544 to determine if the source entity address 336 of the pop-up instruction hits the storage array 1504, fp_r〇w stack i5i6盥fp one Way stacks the recording unit specified by the topmost record unit of 1534. If it hits, the process ends here, that is, the guess quick popup program provides the correct popup data. Otherwise the process will proceed to step 1624. At step 1624, control logic circuit 1502 generates a true value at exception event signal 399, causing microprocessor 14 to execute an exception event handler to process the condition of the guessing fast pop-up program providing the erroneous data. The exception handler will cause the popup to receive the correct data. In one embodiment, the exception handler will empty the fp-row stack 1516 and the power-to-stack stack 1534, and load the correct $1 of the stack indicator register 152 into the fp. —offset register 322. The process ends at step 1624. As can be seen from the following, the detailed pop-up procedure of Figure 16 allows the conventional cache memory to provide pop-up data to the pop-up command, which can be several clock cycles faster than without the fast pop-up device. Referring to Figure 17, Figure 17 is a flow diagram of the data cache 1402 of Figure 15 for a push procedure in accordance with the present invention. The process begins with step 17〇2. ' ^ At step 1702, the instruction translator 106 decodes the push instruction: however, the instruction scheduler 108 will send the push instruction to the storage unit of the execution unit 114. The storage unit then generates a true value at pUSh_instr signal 342. Next, in step 1704, the control logic circuit 15 〇 2 will generate a true value at the decrement signal 384, and then the arithmetic unit 3 〇 4 will decrement the power - 〇 以 68 68 c / m Ι 294 ^, 〇 396, will be decremented The value is output to signal 372. Control logic circuit 1502 causes multiplexer 316 to select this value via control signal 368 to load it into fp_offset register 322. Next, at decision step 1706, control logic circuit 1502 checks for under-signal 388 to determine if step 1704 decrements fp-offset signal 396 to cause the fp-offset register 322 to be under-asserted. That is, control logic circuit 1502 determines if the push command causes stack metric register 152 to point to the previous cache line. If so, the process proceeds to decision step 1716, otherwise it proceeds to decision step 17〇8. At decision step 1708, control logic circuit 1502 checks cacheJiit signal 1572 to determine if the target entity address 336 of the push command hits storage array 1504. If hit, the flow proceeds to step 1712, and if not, proceeds to step 1714. At step 1712, the data cache 1402 treats the current push command as a normal push command to hit the data cache 1402. That is to say, Data Cache 1402 will process this push command in the traditional way known in the field of data caching. Since the push action does not point to the previous cache line, there is no need to update the fp-row stack 1516 and the fp_way stack 1534; thus, the next pop-up program may specify the topmost record unit 1514 and fp_way of the fp_row stack 1516. Stacks the data of the cache line specified by the topmost record unit 1532 of the 1534. The process ends at step 1712. At step 1714, control logic circuit 1502 generates a true value at exception event signal 399, causing microprocessor 1400 to execute an exception event handler to update fp_row stack 1516 and fp_way stack 1534. In one implementation 69 I2945ld. - In the example, the exception handler will empty the fp_row stack 1516 and fp-way 1534 and load the correct data for the bits [5:2] of the stack indicator register 152 into the fp-0ffset register 322. Next, the flow proceeds to step 1726. At decision step 1716, control logic 15 〇 2 checks cache_hit afl number 1572 to determine if the target entity address 336 of the push instruction hits memory array 1504. If it is hit, the flow proceeds to step 718, otherwise it proceeds to step 1726. At step 1718, control logic 15 〇 2 will decide to hit the columns and columns of storage array 1504. The column hit is indicated by index 1548. The hit is indicated by the normal-way-select signal 1578. Control logic circuit 1502 will provide the hit column to fp_way heap 4: 1534 with new one way signal 1582. In addition, control logic circuit 1502 provides the hit column to fp-row stack 1516 with newjrow signal 1554. Next, at step 1722, control logic 1502 will generate a true value at push_row signal 1562 to push the value provided by new_row 1554 into fp_row stack 1516. Control logic circuit 1502 also generates a true value at push_way signal 1588 to push the value provided by new_way 1582 into fp_way stack 1534. Next, at step 1724, the data cache 1402 treats the current push command as a normal push command to hit the data cache 1402. That is, after updating the fp_row stack 1516 and the fp_way stack 1534 at step 1722, the data cache 1402 processes the push command in a conventional manner known in the art of data caching. The process ends at step Π24. ►c/m At step 1726, the control logic circuit 1502 determines the cache line that is replaced by the cache line 336 involved in the index 548 specified by the index 1548 in the storage array 1504. The data cache 1402 must be loaded now. In one embodiment, the control logic circuit b] selects the oldest unused block among the selected columns. The control logic circuit 1502 provides the replaced block to the fp-way stack 1534 via the new-way signal 1582. In addition, the control logic circuit 15〇2 provides the column selected by the index 1548 to the fp_r〇w stack 1516 through the new one row signal 1554. Next, in step 1728, the control logic circuit 15〇2 generates a true value in the push-row signal 1562 to push the new_r〇w signal 1554 long: the value supplied to the fp-row stack 1516. The control logic circuit 1 also generates a true value at the push_Way signal 1588 to push the value provided by the new_way signal 158a2 into the fp_way stack 1534. Next, at step 1732, the data cache 1402 treats the current push command as a normal push command to miss the data cache 1402. That is to say, j updates the fp_row stack 1516 and the parent one way stack 1534 in step 1728, and the data cache 14G2 will process the push command in the traditional way of taking the _ know. The process ends at step 1732. Referring to Figure 18, there is shown in Figure 18 that the microprocessor 1400 of Figure 14 processes (iv) an index plus age paste. The process begins at step 1802. In step 1802, the instruction translator 106 decodes the addition instruction destined for the heap indicator register 152 of FIG. 14, and the instruction scheduler outline 71 12945 is proud - the integer that sends this addition instruction to the execution unit 114 unit. The integer unit then generates a true value at add_spjnstr signal 352. Next, in step 1804, the control logic circuit 1502 generates a true value at the addition signal 382, and then the arithmetic unit 3〇4 adds the add_sp_vd signal 394 to the fp_〇ffset signal 396, and outputs the sum to the signal 372. The control logic circuit 1502 causes the multiplexer 316 to select the sum 'to load into the fp__offset register 322 via the control signal 368.

Next, at decision step 1806, control logic circuit 15 会 2 will check overflow signal 392 to determine if the add procedure of step 1804 caused the fp-offset register 322 to overflow. That is to say, the control logic circuit i5〇2 determines whether the addition instruction causes the stack indicator register 152 to point to the other line and take the line. In step 1 ', the overflow condition refers to the force σ method so that the stacking finger is temporarily stored as 152 and no longer points to the data cache 14 〇 2, the electric _r 〇 w stack 1 mountain 516 the topmost recording unit 1514 and fp — The cache line in which the highest unit of the stack (10) records the unit of record pointed to by 1532. More specifically = say, if the addition causes an overflow, the stack indicator register 152 will usually point to the memory address adjacent to and larger than the data cache 14 () 2, the topmost record unit 1514 of the stack 1516 and the stomach stack i53 - 4 f top. The cache line of the cache line stored in the recording unit pointed to by the recorded unit 1532 is the cache line of the stop line. Therefore, the fp-bribery stack 1516 stacks out the action, so that the fp bribe stacks the topmost record of the 1516 I 4 /, the first top record unit of the year 1ay Hays 1534 refers to the magic circuit H logic circuit 1502 will mouth Port 52 / Pang position has been added to a cache line 72 I29451 ^ 4twf.doc / m order. In this embodiment, in the next step 1808, the number of recording units popped up by the fp-row stack 1516 and the fp-way stack 1534 is calculated by the following method, assuming that the size of the cache line is 64 bytes. = (fp_offset + add_sp_val) / 64 Therefore, if N is greater than 1, it indicates that an overflow occurs, and the flow proceeds to step 1808, otherwise the flow ends.

At step 1808, the control logic circuit 1502 generates a true value in the bristles 1558 to pop up the topmost recording unit of the fp-row stack 1516, and the control logic circuit 1502 also generates a true value at the p0p-way signal 1586. To pop up fp a way to stack the topmost record unit of 1534. As explained in step 1806, in one embodiment, the value of N is calculated, and the fp-row stack 1516 and the fP-Way stack 1534 each pop up N record units. The process ends at step 1808. °

Referring to Figure 19, there is shown a timing diagram of the quick pop-up procedure of Figure 16 from the data cache 1402 of Figure 1 in accordance with the present invention. Figure 19 includes four rows ' labeled 1 through 4 corresponding to four clock cycles of the microprocessor 14A. Figure 19 also includes six columns, each representing a "micro" of the microprocessor i. As a result, the square of each row of intersections of the ® 19 is either blank or "popped" to indicate pop-up instructions at the microprocessor 14. The location of the 〇〇. ^ Τ In the clock cycle 1, according to the first column of Figure 19, the execution unit ii4#::== P〇P-1 read signal 344 generates a true value to request the pop-up to sell the private order, as shown in FIG. Steps 16〇2 are shown. In clock cycle 2, according to the second column, column decoder 1506 decodes the column values provided by 73 I29451^4twf.doc/m fp_row signal 1556 to generate one of the read signals [Nl:〇] 1542. The true value is as shown in step 1604 of FIG. Then, the storage array 1504 outputs a true value read signal [N-1:0] 1542 of the selected columns of the four columns, each record unit cache line, address label, and sorrow 'like the same as Figure 16 Step 1604 is shown. In clock cycle 2, according to the third column, address generator 306 calculates virtual address 334 as shown in step 1614 of FIG. In clock cycle 3, according to the fourth column, the multiplexer 1528 selects the cache line 1592 specified by the ® fp-way signal 1584, and the multiplexer 318 selects the cache line 1592 just selected, fp_〇ffset The correct double word specified by signal 396 is as shown in step 1604 of FIG. In an implementation: in the example, the lower word of the physical address 336, the double word group specified by the element [5:2], is selected in the cache line 1592. In clock cycle 3, according to the fifth column, the translation buffer 308 will generate the source entity address 336 of the pop-up instruction, as in step 1616 of Figure 16, which is not in the clock cycle 4 'based on the sixth column' control logic The circuit checks the fp-check signal 1544 to determine if the previously made guess pop-up procedure is incorrect, as shown in steps 1618 through 1624 of FIG. In one embodiment, the timing of the load instruction is executed from the data cache 1402 of FIG. 15, similar to the timing of executing the load pointer from the non-stack cache 122 of FIG. 1; therefore, FIG. 13 can also be used to illustrate The data cache takes the timing of the load instruction. Comparing FIG. 19 with FIG. 13, it can be seen that the quick pop-up program of FIG. 16 causes the data cache 1402 to provide data to the pop-up command, which can be 74 c/m Ι 294 ^ ^ 〇 does not include the quick pop-up device of FIG. 15 , and does not distinguish between pop-up and load The traditional cache memory that enters the instruction is on several clock cycles.一 In one embodiment, the bits [5:2] of the virtual address 334 are used to select the dual subgroup instead of the fp_〇ffset signal 396. Although the present invention has been described in detail with reference to its purpose, technical features, and advantages, the present invention includes other embodiments. For example, the stacked cache or stack memory described above can be implemented in a variety of ways to achieve a memory with a last in first out function. One of the embodiments is a function of circular FIFO memory.

^ircular FIFO memory) has a stack of top and bottom S metrics to determine which record unit to push or pop next time, and when the stack is emptied. Furthermore, although the foregoing embodiments are mainly based on the instructions of the χ86 architecture, the stack is grown toward the direction in which the memory address is gradually reduced, and the present invention can also be applied to, the stacking command causes the stack to grow in the direction in which the memory address is gradually increased. Microprocessor. Moreover, while the above embodiments only disclose the size of a cache line, other cache lines of different sizes may be used in the present invention. In addition, the present invention has been described in detail with reference to the appended claims. In addition to being implemented in hardware, the present invention can also be implemented in a computer-readable (e.g., readable) medium (e.g., by computer code and data). The above computer digital can implement the function or manufacture of the present invention, or both. For example, the implementation can be a general programming language (such as C, C++, JAVA ', etc.); GDSII database; hardware description language including VerilogHDL, VHDL, Altera HDL (AHDL) (hardware 75 f.doc/m description Languages, ie HDL), and the like; or other programming and/or circuit design tools in the related art. The above computer digital data can be stored in any known medium that is acceptable (eg, readable) by a computer, including semiconductor memory, magnetic disk, optical disk (such as CD-ROM and DVD-ROM, and the like). It can also be embodied in a computer data signal, such as a carrier wave or any other medium, including digital, optical, and analog media. Therefore, the above computer digital can be transmitted through the communication network, including the Internet and the intranet. The invention can also be implemented as an intellectual property (i.e., IP) core, such as a microprocessor core, such as a computer digital (for example, part of it), or at a system level, such as a system on chip (System on Chip, • That is, s〇c) is implemented and converted to hardware in the process of the integrated circuit. In addition, the present invention can also be implemented in a combination of hardware and computer digital. Finally, those skilled in the art of the present invention should be able to easily design or modify other structures based on the concepts and embodiments disclosed herein to achieve the same objectives as the present invention without departing from the scope of the appended claims. The spirit and scope of the invention as defined. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a block diagram of a pipeline microprocessor in accordance with the present invention. 2 is a block diagram of a stack cache of the diagrams in accordance with the present invention. 3 is a block diagram showing additional components of a stacked cache of the drawing in accordance with the present invention. 4 is a block diagram showing a plurality of 76 1294 woven 4 twf.doc/m selection logic circuits of the first level data cache of the figure 根据 according to the present invention. Figure 5 is a flow diagram of a green field pop-up procedure in accordance with the present invention. 127. Fast Flowchart for Fast Flowchart FIG. 6 is a diagram of a stacking cache adder diagram for performing a push procedure to a map according to the present invention, and showing a diagram of a stacking index program executed by the graph microprocessor: According to the invention, the reason for loading the data from the stacking cache of Fig. 1 is to carry out the storage procedure to the level of the map-level fast: two: = Ming' from the weight of Fig. 1 to proceed to the entry of Fig. 5 === Benga, guessing from the heap 4 cache. Figure 12 is a timing diagram of the non-guessing manned program according to the present invention. The normal load procedure of Figure 8 is performed. The cache is a block diagram of the line of the manned === of Figure 8. Block diagram. The first level data cache of Yang Figure 14 is a flow chart of the program according to the present invention. The poor material cache is fast-moving. 77 1294 is poor-plus. Figure 17 is a flow chart of the data flow from the push-in procedure to Figure ls in accordance with the present invention. Figure 18 is a flow diagram of a microprocessor executing a stacked index addition instruction in accordance with the present invention. Figure 19 is a timing diagram showing the quick pop-up procedure of Figure 16 from the data cache of Figure 15 in accordance with the present invention. [Main component symbol description] 0~3 Storage array block number 1~6 Clock cycle 100 Pipeline microprocessor 102 Instruction cache 104 Instruction fetcher 106 Instruction translator 108 Instruction scheduler 112 Register group 114 Execution Unit 116 write back unit 118 bus interface unit 122 non-stack cache 124 stack cache 126 first level data cache 128 micro code memory 132 microprocessor bus 134, 136, 138, 142 · · data signal 78 /m 12943⁄4^ 152 ··Stacking index register 202 ··Cache state 204: Address tag 206: Cache line data 212~216, 222~226, 232, 234: Data signal 302: Control logic circuit 304: Arithmetic unit 306: address generator 308 · translation temporary storage area 312, 314: comparator 316, 318: multiplexer 322: fp_offset register 324: write back line buffer 326: multiplexer 328: data Signal 332: Operational unit 334 · Virtual address 336: Physical address 338~372: Data signal 382: Addition signal 384 ··Decrement signal 386: Increment signal 388 ··Under signal 389~391 ··Data signal 79 1294 Huan f.doc/m 3 92: overflow signal 393~398: data signal 399: exception event signal 402~412: multiplexer 422~432 ··data signal 502: decode and issue pop-up instruction 504: guess provides pop-up data 506: increment fp offset 508: Overflow? 512: Stack Cache Popup 514: Calculate Virtual Address 516: Self-Translating Scratchpad Query 518: Compare Physical Address with Physical Address Label of the Top Recording Unit of Stacked Cache 522: Hit? 524: Exception event is generated to correct error 602: Decode and issue push command 604: Decrement fp_offset 606: Calculate virtual address 608: Self-translating buffer area query 612: Compare physical address with stack topmost record Unit Physical Address Label 614: Hit? 616: Store the data at the top of the stack cache. 1294 Huan f.doc/m 618: The lowest record unit of the stack cache is valid? 622: Schedule write back to the bottom of the stack cache unit 624: Push new data, address label and status into the stack cache top 626: Configure the fill buffer area 628: Incorporate the received cache line Stacking cached record unit 702: Decode and issue a stack indicator addition instruction 704: fp - 〇 ffset = fp - 0ffset + vaiUe

706: Overflow? 708: The data cache pops up, and the program writes back the valid cache line 802 that is popped up. · Decodes and issues the load instruction. 804: Calculates the top two virtual bits 806 of the virtual address cache: Compare the virtual address with the stack address. Tag 808: Hit?

Material 812 · · from the valid and consistent stack cache record unit guess provider 814: self-translating temporary storage area query cache record 816 · · compare physical address with valid and consistent stack bit physical address label ^ 818 :hit? 822: Exception event is generated to correct the error 824: Self-translating buffer area query 826: Entity entity address and entity of all stacked cache record units 1294 Group w- address label 828: hit? 832: Lifting the recording unit from the valid read-and-kick line 834: performing column decoding on the non-stack cache to select the set person/, 枓 836: comparing the physical address with the selected address set of the mouth address tag Real 838: Hit? 842: From the effective and consistent face stacking 844: configuration record unit early for the Bellow 846: loading the missed cache line into the configured record unit 848: providing data from the non-stack cache 902: decoding and issuing Store instruction 904: Calculate virtual address 906: Self-translating temporary area query _: Compare physical address with all stacked cached address tags only body 912: hit? 914 · Store data to a valid and consistent stack cache record unit 916: Compare the entity address with the physical address label of each column of the selected set among the non-stack caches. 918 ··Hit? 922 · Store data to a valid and consistent non-stack cache unit 924: In non-stack cache configuration record unit 926: Load missed cache line into a non-stack cache record 82 1294 shed - Unit 928: Storing data on non-stack cache 1400: pipelined microprocessor 1402: first level data cache 1502: control logic circuit 1504: storage array 1506: column decoder 1508: check logic circuit 1512: multiplexer 1514: fp_row stack top 1516 : fp row stack 1524 : column selection generator 1526, 1528 : multiplexer 1532 : fp_way stack top 1534 : fp_way stack 1542 : read signal [N_1:0] 1544 : data signal 1546 · · tag 1548 : index 1552 · · Column signal 1554~1558, 1562~1564, 1572: Data signal 1574: Address label 1576: Valid bits 1578, 1582~1586, 1588, 1592~1596: Data signal 83 1294 Total ^twf.doc/m 1602 : Decode and issue a pop-up instruction 1604: Guess provides pop-up data 1606: increment fp-offset 1608: overflow? 1612 : fp_row stacking and fp way stack popping 1614: Calculating virtual address 1616: Self-translating buffer area query 1618 · Comparing entity address with physical address label 1622: Hit? 1624: Exception event is generated to correct the error 1702: Decode and issue the push instruction 1704: Decrement fp_offset 1706: Under? 1708: Hit? 1712: General push instruction processing as a hit 1714 · Generate exception events to update fp_row stack with fp_way stack 1716: Hit? 1718: Decide on the hit column and block 1722: Push the hit column into the fp_row stack, push the hit bar into the fp-way stack 1724: see the general push command hit 1726: in the selected Column 1728 in the column is determined to be substituted: push the replaced column into the fp_row stack, push the replaced column 84 I294^twf.doc/m into the fp-way stack 1732 · see the missed general push instruction processing 1802: decode And issue the stack indicator addition instruction 1804: fp-offset two fp-offset + value 1806: overflow? 1808 : fp row stacking and fp way stacking popup 85

Claims (1)

12943⁄4^ twf.doc/m X. Patent application scope: 1. A fast pop-up device for random access memory, including · a first-in first-out memory, storing a plurality of column values y after the first memory The topmost recording unit includes a storage-reciting value; a multiplexer, including: a column value first-input terminal, receiving the latest n-person end receiving access machine access cache from the topmost recording unit A selected part of a memory address of a memory of a memory; the two ends of the memory are selected by a value to select the input terminal, the type of the instruction is specified, and the type of the input finger (four) is popped up. Command, the multi-guard is selected to provide a rain end to provide at the output. , μ input 2 · as described in the scope of the patent application, i = speed = set 'if the selected wheel input end of the specified type is 2 曰 7, then the multiplexer selects the second input 3. Random as described in item 1 of the patent application: Take: Out. a quick pop-up device, wherein if the selection ===body=out command' then the more than one selects the second round of the person's end "provided in the == as in the patent application scope item r-speed ejecting device, which is stored in The column values each include a parent of the target address of the push command. 86 1294 欢 f.doc/m A push-in system that has not been ejected from the stack memory is coupled to the left and A~ And 4 piles should be sU 12. If Shen = 1! · Feng Jilong - microprocessor. The body's quick pop-up month wears the random access cache memory described in item 9 of the track, and hits the random "take = two: u:=: the object in the memory ^:::^ ... Exposure and storage of the information: = in the package of a paste, its patent scope of the item mentioned in the item of the quick pop-up device, including: Determine the first second after the first tB memory 'storage most of her value = In-first-out memory contains storage - 1 top of the latest block value = record [ 15. As described in the patent application scope item 14 of the rapid bomb (four) set, including: (4) take δ 隐 hidden one second The device includes: the first first input end of the memory, receiving the latest block value from the second last in first out recording unit; and a second input receiving a column selecting a value of the output end, providing a value to select a block of the memory; and a type of the instruction to select the input terminal to specify access to the random access cache 88 1294$, if the order is Two more work crying selection ^ input ^ day type is pop-up finger 16 such as Shen-I II - the input end to provide The output end. I6. For example, the quick pop-up device of the body described in the patent application of the 帛 专利 帛 帛 帛 帛 帛 帛 帛 戍 戍 戍 戍 戍 戍 戍 戍 戍 戍 戍 戍 戍 选取 选取 选取 选取 选取 选取 选取 选取 选取 选取 选取 选取 选取 选取 选取 选取The type of the input pointer is a load instruction, and the first is provided at the input end. The location of the random access cache bar according to item 16 of the monthly input range of the input body, wherein the block The selected value contains a block, and the point is here. 'Dai is equal to a tag part of the source address of the load instruction is. For example, please refer to the random access cache memory pop-up device described in item (4), wherein If the selected input end finger of the second multiplexer is not a pop-up command, the second multiplexer selects the second input port to provide the output terminal. 駚^9·If the patent scope is 15th The random access cache memory - one, one, pop-up device, wherein the second last-in first-out memory stores a number of the block values respectively designated in the random access cache memory, save push A block of the target data of the instruction. The cache memory value is divided into: wherein the output number of the second second multiplexer is listed with the block, and the random access cache memory is selected as one of the cache lines to supply the command, wherein the The cache line contains the source data of the capture. 0 2!·For example, the random access cache memory described in the second paragraph of the patent scope of the application 12945 — 体 快速 , , , , , , 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 945 945 945 945 945 945 945 945 945 945 945 945 945 945 945 945 945 945 945 945 945 945 945 945 945 The specified cache line. If you have eaten your body, you will take the column 22. If you apply for a patent, Fan Yidi, the body's quick pop-up device, including:, \^^^^^^^^^^^^^^^^^^^^^^^^^^^^ Cache memory as a towel, the output value specified by the work = the value of the column - the cache line in the cache line (four) 22 pin to access the cache memory access device, where the displacement value will Respond to - pop up refers to people and increments. 7 24. For example, in the fast pop-up device of the random access cache according to claim 23, wherein the increment of the Wei displacement value causes the displacement value to overflow, the random access cache memory is from the The last column value of the last in first out miscellaneous. </ RTI> </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; 26. The fast pop-up device for random access memory according to the scope of the patent application, further comprising: &quot; a comparison logic circuit coupled to the topmost recording unit to receive the latest column value 'and Comparing the latest column value with a portion of the memory address 'where the 6H address contains a source data address of the pop-up instruction. I294^§twf.doc/m 27· The quick pop-up device of the portable body described in claim 26 of the patent application further includes: a ton machine access cache memory exception event wheel &amp; end, (4) 比较 the new column The value does not match the 2 way recorded in view (4) in the most recent condition. T彳日#2························································································ A computer can use the media, and the bean type in the bean is used by the 耘 code calculation device. /, in the middle of the dip-type product a match - the signal is provided 'and the computer data signal contains 3 〇 · - a random pop-up memory quick pop-up method, the column steps: imitation of a push-in command data In the random access cache memory, a column of values specified by a column; after the storage, the field pushes the column value to a topmost recording unit of a last-in first-out memory; and after the pushing, A request is received to read the random access cache, wherein the request specifies a request category. 31. The fast pop-up method of the random access cache memory twf.doc/m I2945^4 body as described in claim 30, further includes one of the following steps: if the request type is a pop-up instruction, Reading the random access cache memory according to the column value stored in the topmost recording unit of the last in first out memory; and if the request type is a load instruction, a memory address specified according to the request Read the random access cache memory. 32. The fast pop-up method of the random access cache according to claim 30, wherein the + file storing the push instruction includes:, v^ storing the data of the push instruction to One of the columns of the random access cache memory ^, wherein the barrier is specified by a block value. 33. The fast pop-up method of the random access body as described in claim 32 of the patent application further includes the following steps: After entering the memory of the daily memory, the first top of the first incoming and outgoing memory is blocked. Recording unit 34. A fast pop-up method for a random access fast body as described in claim 33, wherein the first and the same are the same as the latter. The quick pop-up method of the 33rd 顼 申请 申请 , , , , , , , , , 申请 : 申请 申请 申请 申请 申请 申请 申请 申请 申请 申请 申请 快速 快速 快速 快速 快速 快速 快速 快速 快速 快速 快速 快速 快速 快速 快速 快速 快速 快速 快速 快速 快速Randomly stored 36. The random pop-up memory of the random access cache 92 12945, as described in claim 31, provides a quick pop-up method for the μ·-/πι body, and further includes the following steps: Deciding to read the silk picking with the age (four) ❺ 槪Value, ^ Section lacks general (4) = used ^ The data specified by the pop-up command - block. A body, although stored 37. As claimed in the patent scope of the Honghong body, the method of rapid pop-up, which determines The steps further include: ', take the memory to compare the source of the pop-up instruction - source It is expected that her machine accesses the cache to provide the record - the record is selected according to the block value. The value of the armor iron is 38. The quick pop-up method of the body described in the third paragraph of the patent application includes the following steps. : Transfer the cache memory to the storage step and decrement a displacement value, &amp; access a cache line of the cache memory. The material level: refers to: the middle cache line is located in the random memory, set: , the specified column. The value of the column is 39. For example, the pop-up method of the syllabus of the patent application scope includes the following steps: _ access cache memory storage scale (four) order, job _ value The method for reading the fast pop-up method of the body described in item 31 further includes the following steps: _ sparing, accessing the value for the reading step, m specifying the external machine accessing the cache memory, storing Today (4) 疋 机 41 41. If you apply for a list of data specified by patent rH. 随机 40 items of random access cache memory 93 I294W, ^ f.doc / im a quick catch eject device, the computer can read The program mom includes: a majority of the _ the first top record unit; and 匕Store - the latest column value - a second code, providing a multiplexer, including · the latest column value; - the first - the input terminal receives the memory from the topmost record unit - the instruction: gas: body: Two of the memories are provided with a value of 2 to select the random access cache input terminal to specify; if the input terminal is selected to be provided at the round end. To select the first 95