TW556212B - L2 cache LRU generation method and apparatus - Google Patents

Abstract

An associative cache memory having an integrated tag and LRU array storing pseudo-LRU information on a per way basis, obviating the need for a separate LRU array storing pseudo-LRU information on a per row basis. Each way of the integrated array stores decoded bits of pseudo-LRU information along with a tag. An encoder reads the decoded bits from all the ways of the selected row and encodes the decoded bits into standard pseudo-LRU form. The control logic selects a replacement way based on the encoded pseudo-LRU bits. The control logic then generates new decoded pseudo-LRU bits and updates only the replacement way of the selected row with the new decoded pseudo-LRU bits. Thus, the control logic individually updates only the decoded bits of the replacement way concurrent with the tag of the replacement way, without requiring update of the decoded bits in the non-replacement ways of the row.

Description

556212 A7 B7

V. Description of the Invention (/) Comparison of related applications This application claims priority based on a provisional application of a US patent. Its serial number is _, and was filed on October 23, 2001. "[2 CACHE LRU GENERATION METHOD AND APPARATUS". (1) Technical Field of the Invention: [0001] The present invention relates generally to the field of associative cache memory used in microprocessors, especially information of cache and line replacement algorithms in an associative cache memory. Storage and generation. (II) Background of the Invention [0002] In the differentiating system, '3 memory storage generally includes a hierarchical system with different types of memory storage devices. In this system, different levels of memory storage have different characteristics, especially capacity and data access time. In this memory system, a lower hierarchy indicates that it is closer to the processor of the system. The memory device furthest from the processor usually has the largest capacity and is the slowest. Common examples are electro-mechanical devices, such as magnetic tapes, compact discs, and hard disk storage devices, commonly referred to as mass storage devices. Although relatively slow, they can store a significant amount of data. [0003] The next layer in the system is generally a system memory containing solid-state memory devices, such as dynamic random storage ---------- · installation ---- ---- Order --------- i (Please read the notes on the back before filling out this page) Printed by a member of the Intellectual Property Bureau of the Ministry of Economic Affairs and Consumer Cooperatives 2 556212 A7 B7 V. Description of the invention (>) The fetch memory (dynamic random access memory, DRAM for short), although its access time is one of the tenth power of large-capacity storage, but its capacity is the same. [0004] In this memory system, the level closest to the processor, the temporary storage Is of the processor is not counted, and usually one or more levels of cache memory can be found. Cache memory has extremely fast access times. A common example is static random access memory (SRAM). In many cases, one or more levels of cache memory and processor are integrated on the same integrated circuit. This is especially true of new microprocessors. Cache memory stores or "caches" the data most commonly accessed by the processor from system memory to provide faster data access when requested by the processor. I [0005] Cache memory generally stores data in units of cache lines. The commonly used cache line size is 32 bytes. Because the cache memory is smaller than the system memory, when data is read from or written to the cache memory, the system memory address of the data has only a part of it, which is often called the index portion. ) Or index, which is used to address fast memory. As a result, multiple system memory addresses are mapped to the same cache index. In a direct-mapped cache, only one of the multiple system memory addresses mapped to the same cache index can be cached at a time. Therefore, if a program frequently accesses two system memory locations mapped to the same cache index, the two will often be replaced with each other in the cache memory. In order to reduce this situation and improve cache performance, associative cache is generally used

Standards · Zhongguan Family Standard ^ grid moxj / JIT 556212 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 ------- B7 V. Description of Invention (>>) --- associative cache. [0006] Unlike direct mapping cache memory, each index stores only a single-cache line ' associated cache memory stores one row or group of N cache lines in each index. Associative cache memory allows a cache line to exist on any of the N locations in the selected column. This type of cache memory is called n-way associative cache memory or N-way set-associative cache memory. Because there are N different ways in the selected set or column, the cache line may be Stored in it. [0007] Since the cache line can be stored in any of the N-way associated cache memories-when-the new cache line is to be written into the cache memory, the association cache must be determined in Which of the N ways the new cache line is written to retrieved. That is, the 1-associative cache memory must determine which of the existing N cache lines in the retrieved column is to be replaced. Choose the most probable way, namely the cache line, to replace it. It is hoped that it will not be used in the near future. This is the task of cache replacement algorithm. An example of the method used to determine which way to replace is to replace the selected peasant in the list. The peasant is used less frequently and is leas ^ recently used (LRU), which is the cache line. The cache memory is kept in a known row to determine which way is the least recently used information. In conventional associated cache memory, this LRU information is stored in a functional block in units of rows. The functional block is physically associated with the storage cache line itself and its associated address tag. The function blocks are separated. [0008] The conventional associated cache memory contains at least three relatively large (Please read the Zhuyin on the back? Matters before filling out this page)

556212

Functional blocks or arrays are printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs, which can be physically distinguished. The first is a data array, which stores the actual data cache lines, and is configured as a plurality of rows with N cache lines, as described above. [0009] The second functional block that conventional associative cache memory has is a directory, also known as a tag array. This directory is configured similarly to a data array with N channels. That is, the index portion of the system memory address addresses this directory to select a list of N entries. An entry in a known path in a known row of this directory stores a corresponding cache line marker and cancer in the data array. Index 3 has been indexed to form the system memory address corresponding to the cache line, or at least the earlier part of the system memory address. When the cache memory is accessed, each tag in the selected row in the directory is compared with the system memory address and checked with the cache line status to determine if a cache hit has occurred. A common example of a cache line state is the MESI state of the cache line. [0010] The third functional block of conventional association cache § Memories is the LRU array. As mentioned earlier, in conventional associated cache memory, LRU information is stored in units of rows. That is, the LRU array is also addressed by an index. However, the index selects only a single item in the LRU array, not an entire column. That is, the single item retrieved contains LRU information for the entire cache line in the corresponding data array. The reason why the conventional associated cache memory separates the LRU array from the data array and the directory is that the items of the LRU array may be updated every time any cache line in a row is updated, but the data array or directory It is based on the cache line to update the National Standard (CNS) A4 (210 X 297 mm) for the Han National Week. ----------- install ------ --Order --------- (Please read the notes on the back before filling out this page) 556212 A7 B7 V. Invention Description (Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs: New, that is, only once Listen to the-way in the N way of the array and the directory. [0011] For cache memory, there has always been more than six times t. Secondly, to keep up with the continuous increase in processor speed: then the capacity of the 1 body increases, and it will It is necessary to reduce the cache memory. Fortunately, it may be reduced. In particular, the cache memory is integrated into the processor. ^ ^ This is required. In the new type of microprocessor, the integrated cache memory will consume slightly The precious circuit area that handles the bump circuit of H. Heart said [0012] However, the conventional associative cache memory contains three real The fact that there are separate and fairly large function blocks runs counter to the need to keep the cache memory as small as possible. One disadvantage of the conventional method is that it replicates some of the logic that already exists in the array due to the directory, like It is address decode logic and write logic (write 10), so it needs to occupy the area of the integrated circuit or circuit board. Another disadvantage is that the independent LRU array is compared with the directory and data. Arrays usually have different aspect ratios, which have a negative impact on floorplanning. That is, it is difficult to place these functional blocks in integrated circuits in a way that uses space efficiently. On the die. Another disadvantage is that the separated LRU array constitutes another functional block, which needs to be placed and routed on the plane of the integrated circuit or circuit board. [0013] Therefore What we need is to generate and store the replacement information of the associated cache line in a more efficient use of space to reduce the associated cache memory size The impact of the size and space configuration. This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) «t -------- IT --------- (please first Read the notes on the back and fill in this page) 556212 A7 、 Invention description (t) (C) Brief description of the invention: [0014] The present invention provides-the replacement information is recorded in Wei Mi_, its cache line is small, compared with The Rongting Bureau Wei line, _H m Yuan Jiyun, because it achieves the aforementioned purpose, is out today. So, cache the memory. The cache memory provides an N-way switch and a plurality of storage elements for storing ^ μ—

Column, the standard __ $ 二 _ ^ =, _ data barrier m it depends on all pieces of memory, configured as M rows and N ^ 1. Γ storage files are stored one corresponding cache line-mother two multiple storage The component also stores information used to decide which n-way to replace. 2. The cache memory also contains control logic, control l0glc) 'is transferred to the tag array to read the information from all N channels that are taken by μ column A by k. The control logic also chooses to replace N channels according to the read information, and only updates the information of the selected channels to be replaced. [0015] In another aspect, a feature of the present invention is to provide an n-way associative cache memory. The cache memory includes a data array, which is arranged in N ways and has a plurality of rows. Each of the plural series stores N cache lines corresponding to N channels. The data array also includes an index input to select one of the plurality of rows. The cache memory also includes a directory, which is coupled to the data array 'and configured as N channels, and has a plurality of columns. Each of the plural series stores the replacement information of the cache line. The cache line replacement information is distributed on the N channels, so that each channel stores only a part of the cache line replacement information. The cache memory is also compatible with the Chinese National Standard (CNS) A4 specification (21G X 297)

Install -------- Order --------- (Please read the precautions on the back before filling this page) Α7

556212 V. Description of the invention (7) contains control logic, coupled to the directory, for receiving cache line replacement information from one of the plurality of selected rows, and in response to generating a signal to return. The signal specifies data One of the N channels of the array is used to replace a corresponding cache line in the selected N cache lines of one of the plural sequence. [0016] On the other hand, a feature of the present invention is Provides a four-way associative cache memory. The cache memory contains a data array. The data array has M rows. Each row in the M row has four lanes, and each lane has a cache line storage element ( line storage element) to store a cache line. The cache memory also contains a directory coupled to the data array. The directory has the M column. Each column in the M column has the four channels, each A tag storage element (a tag storage element) stores a tag for the cache line corresponding to a cache line storage element stored in one of the data arrays. The tag storage element also stores a two-bit cache Line replacement capital. The body also includes an encoder, which is lightly connected to the directory, and is used to read eight of the four channels of one selected column M from each channel containing the two bit cache line replacement information. The decoder uses the pseudo-ieast-recentiy-used encoding method to encode the eight bits into three bits. The three bits are selected in the M column. "Four riches, specify which-Di" field is the least used recently. [0017] On the other hand, a feature of the present invention is to provide an associated cache with an integrated mark and record exchange information_ The cache memory contains two storage elements with M rows and N paths ------------ install -------- order -------- -(Please read the note on the back? Matters before filling out this page) Printed by the Employees ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 8 556212» B7 V. Description of the invention (f) Each-storage element stores a cache line mark and The column has an input terminal for receiving-indexing, the index_two = the M column of the ... the cache memory also contains a control logic storage element queue, which is selected with a simple崎 _ Qi has, the road = the replacement information of each road is encoded into the replacement information of each row. This is the demand for a separate cache line _ Wei Zhiling element_. [0018] Another feature of this issue is Provides ν-associated cache memory. The cache memory contains a two-dimensional ^^^ 3 = each column also stores quasi-LRu (―) Beicheng. LRU-Beixun contains N-channels distributed in the column The N parts are aggregated to specify which of the N paths is actually the least recently used. N_Remember—the corresponding quasi-information of each of the N parts follows Each of the N tags can be updated individually. The cache button also contains a control profile and an input reduction array, which is used to receive N partial quasi-coffee information distributed in the N channels of the column. The control logic is also the permutation-cache line in the two-dimensional data_, one of the corresponding two-dimensional tags and arrays of the cache memory. The cache line designated by the N sections is the least recently used in this column. [0019] Another feature of the present invention is to provide a method for updating-having an associated cache memory of M columns and N channels. The method includes a basis-cache line record. From the silk record, one of the columns ′ is fetched and the N line of the selected line is read, and the cache line exchange information stored in each line is read. The method also includes a response to the reading action, selecting the selected row of _ 9 t paper, f-degree turn-over standard (CNS) A4 size ⑵Q χ 297 public ^ · 556212 A7 B7 five block diagrams, description of the invention (wherein One is used for replacement, and responds to reading and selecting actions to generate new cache line replacement information. The method also includes updating the path with the new cache line replacement information after the generated action. [0020] This One advantage of the invention is that it eliminates the need to design a separate array of bits for the replacement algorithm. Another advantage is that it can avoid repeating most of the address decoding logic, writing logic, and other similar logic. It must be done for the conventional method. Although it is shown in practice that each index requires eight bits (2 bits / way * 4 ways), and the conventional method requires only three bits το, but the present invention has It is noted that the copied array control logic and three per-indexes of 70 will be larger than the size of the eight storage bits of the cache memory of the present invention. Another advantage is that it increases the number of existing mark arrays. Bit count and ride her to put on charm — An array of windings is required outside. [0021] Other features and advantages of the present invention will become clearer after examining the rest of the description and illustrations in this specification. 4) Description of the invention's illustrations: Notes on the four-way customs clearance of materials Lai Zhifang [0023] Figure 2 is a diagram of the control logic of the conventional cache memory [00f], and Figure 3 is a flowchart illustrating how the conventional cache memory of Figure 1 replaces a cache line. Illustration. [Θ is the four-way associative cache memory ^ -------- ^ --------- according to the present invention (Please read the precautions on the back before filling this page )

This paper size is applicable to the Chinese national standard 0 x 297 mm) 556212 V. Description of the invention (1 block diagram. [0026] FIG. 5 is a block diagram of the four cache memories in accordance with the present invention. &Quot; Control logic [0027] FIG. 6 is a flow chart of the operation of adding four cache memories according to the present invention, such as changing a cache line. Printing the drawing number description of the staff consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs: 100 custom four-way associated cache Memory 102 control logic 106 data array 112 cache address. 116 index, 122 new mark 126 demultiplexer 132 column selection signal 134 rep 1 acement-way-se 1 ect [3: 0] signal 142 LRU [2: 〇] Signal 144 new—LRU [2: 0] signal 154 mark storage element 156 cache line storage element 158 LRU storage element 204 replacement circuit generator 206 new LRU generator 302 ~ 316 conventional replacement cache line operation flow 400 four-way associative cache memory 402 control logic 404 tag array 424 demultiplexer 434 rep 1 acement-way-se 1 ect [3: 0] signal 104 tag array 108 LRU array 114 tag 118 byte offset 124 demultiplexer 128 new cache line ------------ t— (Please Read the notes on the reverse side and fill in this page) _ n This paper size is applicable to China National Standard (CNS) A4 (210 X 297) 556212 A7 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of Invention (442 per— way—LRU [7: 0] § hole number 444 new—per—way_LRU [1: 0] signal 454 mark and LRU storage element 464 mark 468 LRU information for each way * 502 per-way one LRU to per-rowJLRU encoder 504 permutation path generator 506 per-way-LRU decoder 508 per-row-LRU [2: 0] signals 602 ~ 616 Operation flow of permutation cache line of the present invention (five) Detailed description of the invention: [0028] This section will First, a related art associative cache memory without the advantages of the present invention will be described in order to better understand the present invention. [0029] Please refer to FIG. 1, which shows a block diagram of a conventional four-way associative cache memory 100. In one of the write operations of the fetch memory 100, a new cache line 128 is provided to write the cache memory 100. A designated cache address 112 of the cache line to be read or written , It is sent to cache memory 100. In particular, The cache address 112 of the new cache line 128 is used to write the new cache line 128 into the cache memory 100. The cache address 112 includes a standard delta-portion 114, an index portion 116, and a one-byte offset portion 118. The mark 114 contains the most significant bits of the cache address 112. Index 116 contains the medium significant bits of cache address 112, and byte offset 118 contains the least significant bits of cache address 112. [0030] The cache memory 100 includes a data array 106. The data array 106 includes a plurality of storage elements for storing cache lines, which are illustrated in the cache line storage element 156 of FIG. The storage element 156 is configured with two plural numbers and one paper rule when closing the house ^! S) A4 post ⑽ 556 212 A7 B7 V. Description of the invention (1 >) Columns and plural two-dimensional _. The summary line_ peach. The cache memory 100 includes four ways' labeled as way 0, way 2 and way 3, as shown in the figure. A per-cache line is a cache line storage element 156 located at the intersection of 1 and the line. The index 116 of the cache address 112 is sent to the data array 以 with a row select signal (and select signal ·) 132. Column selection signal 132 Selects one of the data arrays 1G6 to write a new cache line 28. A quick take-off can shut off any H-Peng towels set to the road. That is, writing any of the -cache lines into one of the columns of the data array selected by the row selection signal 132 is permissible. In most financial applications, compared with direct mapping of cache memory, this kind of chick increases cache memory, hit rate and efficiency. [0031] Cache; the memory also includes a demultiplexer (126), coupled to the data array (1). Demultiplexer 126 is controlled by replacement_way_select [3: 0] signal 134, and one of the four ways of data array 106 is selected to write new cache line 128. Demultiplexer 126 receives this new cache line 128 and selectively sends it to one of four ways of data array 106 specified by replacement_way_select [3: 0] signal 134. The repiacement-way-seiect [3: 〇] signal 134 is generated by the control logic 102, which will be explained in detail in Figure 2 below. Therefore, the new cache line 128 is written into the storage element 156 which is one of the paths selected by the replacement_way_select [3: 0] signal 134 in the column selected by the row selection signal 132. [0032] The cache memory 100 also includes a tag array 104, also referred to as the directory 104. The mark array 104 contains a plurality of remaining 13 for storing marks. The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm). M -------- ^ ----- ---- (Please read the notes on the back before filling this page) 556212

The memory element printed by the employee's consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs is illustrated in FIG. The marker array is configured as a two-dimensional array with the same number of rows and paths in a similar manner to the data array. —Cache-like—the mark age element 154 is located at the intersection of the column and the row, and the mark storage element 154 corresponds to the cache line storage element 156 located on the data_ 1G6 phase_ column and row. The mark 114 at the address 112 is sent by the new mark signal 112. The row selection signal 132 selects a row of the tag array 104 to write a new tag 122. This flag is read when a read operation of the cache memory 100 is performed to determine whether a cache hit has occurred. In addition to storing the mark of the cache line, the mark storage element 154 can also store the cache status

Negative Λ 'such as MESI (Modified' Exclusive, Shared, jnvalid) status information, or cache status information related to other cache-consistent algorithms. If the mark in the mark storage element 154 matches the mark 114 in the cache address 112, a cache hit occurs, and the cache line has the required correctness. X

[0033] The cache memory 100 also includes a second demultiplexer 124 connected to the tag array 104. The demultiplexer 124 is also controlled by a replacement-way-Select [3: 〇] signal 134, and one of the four ways of the mark array 104 is selected to write a new mark 122. The demultiplexer 124 receives the new tag 122 and selectively sends it to one of the four ways of the tag array 104 designated by the print_way_Select [3: 0] signal 134. Therefore, the new mark 122 is written in the row selected by the row selection signal 132, and the storage element 154 is one of the roads selected by the signal 134. -------- 1 --------- (Please read the precautions on the back before filling out this page) 14 556212 Five A7 B7 、 Invention description (\ f〇 [0034] cache memory 100 also includes an array ⑽, which contains a plurality of storage elements for storing and information, which is exemplified in the LRU storage element 158 of Fig. 2. The array ⑽ is configured as a dimensional array, and the number of rows and data__ and Mark _Temple_. Which information is stored in -column-LRU storage element 158, which corresponds to the same row and path in the data array 106-cache line storage element 156. Column selection gas number 132 also Sent to LRU array · Array 108 receives new LRU information from Qing-LRu [2.〇 °] signal 144. This new LRU information describes which of the four channels selected by the column selection signal 132 is which is the most recent The least used. This new LRU information is written into the storage element 158 selected by the row selection signal 132. The new_LRU [2: 0] signal 144 is generated by the control logic 102, as shown in Figure 2 below. Some of them will be explained. The LRU array 108 also uses one of the columns selected by the column selection E132 from the LRU array 108 to provide the coffee load, and borrows LRU [2: 0] news. 142 sends it to the control logic IQ. The restraint logic 102 uses the second information received by the LRU [2: 0] signal 142 to generate the replacement-way_select [3: 0] signal 134 and the new-LRU [2: 0 ] Signal 144, as will be described next. [0035] Please refer to FIG. 2, which shows a block diagram of the control logic 102 of the conventional cache memory in FIG. 1. FIG. 2 also shows that the description is included in each of the figures. The equation of the combination logic of the blocks. Figure 2 also shows a tree diagram and bit encoding method, which describes the three-bit encoding method for the compiled stone horse information of a four-way quasi-LRU algorithm in the conventional technology. The four-way quasi-LRU algorithm is a commonly used replacement algorithm for associative cache memory, because it uses fewer bits than the real method and is easier to update, but still has most of the real coffee ^ ------ -^ --------- (Please read the notes on the back before filling out this page) 556212 A7 Printed by the Intellectual Property Bureau Employee Consumer Cooperative of the Ministry of Economy What is the least recently used cache line for the selected column. For simplicity, here is described The quasi-LRU information and related signals are called LRUs, not quasi-LRUs. The three bits of the LRU information stored in the LRU array 108 are sent to the control logic 102 in FIG. The tree diagram shown in Fig. 2 is encoded. [0036] The control logic 102 includes a replacement circuit generator 204 for receiving the picture-LRU [2: 0] signal 142 from the picture-LRU array 108. [0037] The replacement path generator 204 selects a replacement path based on the following rules also shown in FIG. If LRU [2: 0] = 3 'b000, then route 0 is LRU. If LRU [2: 0] = 3' bOOl, then route 1 is LRU. If LRU [2: 0] = 3 ', b010, then Way 0 is LRU. If LRU [2: 0] = 3 '1〇011, then Way 1 is LRU. If LRU [2: 0] = 3' bl00, then Way 2 is LRU. If LRU [2: 0] = 3 'blOl, then Road 2 is LRU. If LRU [2: 0] = 3' M10, then Road 3 is LRU. If LRU [2: 0] = 3 'bill, then Road 3 is LRU. [0038] The replacement method generator 204 generates replacement-way_select [3: 0hfli £ 134 in response to the LRU [2: 0] signal 142 according to the following equation also shown in FIG. replacement_way_select [0] = replacement-Way_select [l] = replacement_ way_select [2] = replacement_way_select [3] delete 2] & ~ LRU [0] -LRU [2 ] & LRU [0] LRU [2] & ~ LRU [1] LRU [2] & LRU [1] [0039] The control logic 102 also includes a new LRU generator (new LRU 16 This paper size applies to China National Standard (CNS) A4 Specification (210 χ 297 mm) (Please read the precautions on the back before filling out this page) Engine Installation ---- tr --------- ^^ 1. 556212

Description of the invention (+ printed by generator of consumer cooperative of employee of Intellectual Property Bureau of Ministry of Economy) 206 for receiving lru [2: 0] signal 142 from LRU array 108. The new LRU generator 206 also receives a replacement_way_select [3: 0] signal 134 from the replacement way generator 204. The new LRU generator 206 generates new Lru information based on the rules shown in Table 1 below (also shown in Figure 2). 0 Replaces the bit change of the channel. 0 '-0x0 = > lxl i' 0xl = > lx0 2 10x = > 01x 3 llx = > 00x Table 1 [0040] The rules of Table 1 are further explained as follows. If the path Q is a permutation path, it is deviated from the path 0 by setting LRU [2], not changing LRU [1], and setting LRU [0], because it is now the most commonly used. If the way 1 is a replacement way, the way 1 is deviated from the way 1 by setting LRU [2], not changing LRU [1], and resetting LRU [0], because it is now the most commonly used. If way 2 is a replacement way, deviate from way 2 by resetting LRU [2], setting LRU [1], and not changing LRU [0], because it is now the most commonly used. If the way 3 is a replacement way, the way 3 is deviated by resetting lru [2], resetting LRU [1], and not changing LRU [0], because it is now the most commonly used. [0041] The new LRU generator 206 generates a new LRU [2: 0] signal 144 of FIG. 1 according to the following equation also shown in FIG. ----------- Install -------- Order --------- (Please read the phonetic on the back? Matters before filling out this page) 17 556212 Intellectual Property of the Ministry of Economic Affairs A7 B7 printed by the Bureau's Consumer Cooperatives V. Description of the invention (丨,) new_LRU [0] = // If the road is replaced by 0, set [0]

rep 1 acement_way_.se 1 ec t [0] I // If the way 1 is replaced, reset [0] (not set) // If the way 2 is replaced, write the old [0] replacement—way—select [2] & LRU [0] | // If the way 3 is replaced, write the old [0] replacement_way_select [3] & LRU [0]; new—LRU [1] =: // if the way is replaced , Write the old [1] replacement_way_select [0] & LRU [1] | // If the way 1 is replaced, write the old [1] replacement_way_select [l] & LRU [1 ] | // If the way 2 is replaced, set [1] replacement—way—select [2]; // If the way 3 is replaced, reset [1] (not set) new—LRU [2] = // If the way is replaced 〇, set [2] r ep1acement_way_se1ect [0] | // If replacing the way 1, set [2] replacement_way_select [l]; // If replacing the way 2, reset [2] (not set) // If the path 3 is replaced, reset [2] (not set) [0042] Please refer to FIG. 3, which shows an explanatory diagram—the operation flow chart of how the memory 1GG is replaced with the cache line. This begins at block 302. [0043] In box 302, the index 116 of FIG. 1 is sent to the LRU array 108 of FIG. 1 through the selection signal 132 of FIG. ) ▼ -install -------- order --------- AWI ·

A7 B7 556212 V. One column of the description of the invention (β). Flow proceeds from block 302 to block 304. [0044] In block 304, the LRU information is read from the LRU storage element 158 of the selected row of the LRU array 108, and sent to the control logic 102 of FIG. 1 through the LRU [2 ·· 0] signal 142. Flow proceeds from block 304 to block 306. [0045] In block 306, the replacement path generator 204 of FIG. 2 generates a replacement_way_select [3: 0] signal 134, as described in relation to FIG. 2. Flow proceeds from block 306 to block 308. [0046] In block 308, the new LRU generator 206 of FIG. 2 generates a newJLRU [2: 0] signal 144 of FIG. 1, as described in relation to FIG. The process then proceeds from block 308 to block 312. [0047] In block 312, the new cache line 128 of FIG. 1 is written into the cache line storage element 156 selected by the row selection signal 132 and the replacement_way_select [3: 0] signal 134. Flow proceeds from block 312 to block 314. [0048] In block 314, the new mark 122 of FIG. 1 is written into the mark-mark storage element 154 selected by the column selection signal 132 and the rep 1 acement_way_se 1 ect [3: 0] signal 134. Flow proceeds from block 314 to block 316. [0049] In block 316, the new LRU information on the new-LRU [2: 0] signal 144 is written into the LRU storage element 158 of FIG. 1 selected by the row selection signal 132. The process ends at block 316. [0050] It is easy to see from FIGS. 1 to 3 that the conventional associative cache memory is stored in a separate array outside the mark array and the data array. ------- Order --------- line--AWI C, please read the note W on the back before filling out this page) Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs, Employee Consumer Cooperatives Paper size applicable to China National Standard (CNS) A4 Specification (21〇X 297 Public Love) A7

-------- ^ ---- (Please read the precautions on the back before filling out this page) ϋ I ϋ II 556212 LRU, the reason for using a separate brush array for custom associative cache memory, each When any one of the selected rows, namely the cache line and the tag, is updated, the LRU information of the -row may also be updated accordingly. In contrast, a tag array is updated on a per-way basis, i.e., every tag unit. That is, -times only the marked-N way towel-way is updated. As discussed above, the use of physically separated data, tags, and LRU arrays avoids the obvious disadvantages. Therefore, as provided by the present invention, it is very desirable to use only an array of a plurality of storage elements to store marker and path replacement information. However, since the markers are updated on a per-channel basis, a solution is needed that allows the way replacement information to be updated on a per-channel basis. [0051] The present invention provides an associative cache memory that integrates an LRU array into a tag array. Normal LRU information, that is, each row of LRU information or row-specific information, is decoded into way-specific information or information on a per-channel basis, which is specific to the information to be The road to replacement. This allows the LRU information of each channel to be written into the private line of the cache line (ie, each channel is taken as a unit). At the same time, the LRU information is also stored in the private sigma array. In other words, the L of the mother road, that is, the information can be written into the tag array via individual roads, instead of all roads in the column. In order to decide which one of the selected | is to be replaced, read the LRU information of each way from all the ways, and encode it into county scale LRU data. The steps to transcode without code are | enabling the integration of markers and LRU arrays. As will be mentioned next, it is necessary to store the decoded LRU bits of each channel more than the normal LRU bits of each channel.

| & requires more storage space, but this is not necessary-a separate LRU $ array is its advantage.

U I___ 20 Paper (CNS) A4 Secret (21G x 297 ^) ----—_ 556212 556212 A7 B7

[0052] Please refer to FIG. 4, which shows the present invention—four Γ = ㈣, unless otherwise specified, the cache memory _ folder A on both sides, and the same component number of 5 memory 100 is taken, No, it's similar. The difference is that the Xia memory side does not contain a separate unitary array as shown in Figure-Conventional ^ Memory 100. On the contrary, the LRU information is integrated into a cache memory and a tag array is deleted. [0053] The cache memory contains a data array and a demultiplexer 126, similar to the components shown in FIG. In a demonstration implementation, the data array 106 can store data. Each cache line contains groups of bits tl. So each column can store 128 bytes. So the array 106 contains 512 columns. [0054] The cache memory 400 includes a tag array 40 and the array 404 is configured in a manner similar to that of the tag array of FIG. 1; As an example, storing 7G pieces 454 is configured not only to store a mark tear, but also to store LRU information 468 for each channel. The marker array 4 ′ is configured in a manner similar to the marker array 106—a two-dimensional array having the same number of columns and paths as the marker array 106… the cache line marker 464 is located in the—column and path The intersection and the point-mark and LRU storage element 454 correspond to the cache line storage element 156 in the same row and path in the data array. The column selection signal 132 is also sent to the mark array 404. The tag portion 114 of the cache address 112 is sent with a new tag signal 122. Column selection Signal 132 selects one of the columns of the mark array 404 to write a new mark I______21

National Paper (CNS) A4 (21G)

-------- t ----- (Please read Note 5 on the back before filling out this page) ^ • 1. 556212 Printed by A7, Employees' Cooperatives, Intellectual Property Bureau, Ministry of Economic Affairs yl) 122. In a read operation of the cache 400, the tag u is compared to determine whether a cache-hit occurs. In addition to storing Spider 2 memory 464 and LRU information for each channel, the tag storage element 454 can also store cache status information, such as leg status information, or cache status information associated with other = consistency algorithms. [0055] In a specific embodiment, each channel of LRU information includes two bits. The encoding method of each channel of information 468 is different from the LRU information of array 108 shown in Figure 1. This is because the LRU of each channel stored in the tag array 404 is 468. It is updated in the unit of the parent channel and stored in ^ That is, the LRU information in the array 108 is updated in units of each column. Although each channel ^ is written in units of the parent channel, it is still read in units of each column, just as the marks are read in the selected column of the mark array 404. That is, 'read each Lru information 468 from each of the four channels of the selected column to determine which one has been least recently used. The encoding and decoding methods of each channel of LRU information 468 will be detailed below. [0056] The cache memory 400 also includes a second demultiplexer 424, which is coupled to the tag array 404. The demultiplexer 424 is also controlled by a replacement-way-select [3: 0] signal 434, and one of the four ways of the mark array 404 is selected to write a new mark 122. Demultiplexer 124 receives this new tag 122 and selectively sends it to one of the four ways of tag array 404 specified by print_way_select [3: 0] signal 434. Therefore, the new mark 122 is written into the column selected by the row selection signal 132, and the storage element 454 is one of the roads selected by the replacement_way_select [3: 0] signal 434. 22 This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) -------- Order --------- (Please read the precautions on the back before filling this page ) 556212 A7

V. Description of the invention (> >) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs [0057] In addition, the demultiplexer 424 receives one of the new one per one way one LRU generated by the control logic 40 [1] : 0] signal 444. Demultiplexer 424 receives new_per__way_LRU [1 ·· 0] signal 444, and optionally provides new one per one way one LRU [1 ·· 0] signal 444 to rep 1 acement_way_ select [ 3: 0] one of four ways of the tag array 404 designated by the signal 434. Therefore, the new_per_way_LRU [1: 0] signal 444 is written into the column selected by the row selection signal 132 along with the new mark 122, and is represented by rep 1 acement—way_se 1 ect [3: 0] signal 434 in a storage element 454 of the selected path. The control logic 402 generates a new_per_way_LRU [1: 0] signal 444 in response to the per-way_LRU information 468 from the tag array 404-all four-way two-bits of all the selected rows 468, the information 468 It is sent to the control logic 402 via per-way_LRU [7 ·· 0] Xunzang 442, as described below in relation to Figure 5. As shown in the figure, perjay-LRU information 468 from road 0, road 1, road 2, and road 3 of the tag array 404 passes signals per-way_LRU [1 ·· 0] 442, per-way-LRU [3 · · 2] 442, 1) 61: 3 ^ -1 1 ^ 1] [5: 4] 442 and 1361 ^ 37-1 ^ 1] [7: 6] 442. The control logic 402 generates the port 13〇611 ^ 111: _ ~ 87_5616 (: 1; [3: 0] signal 434 according to the perjay_LRU [7: 0] signal 442, the details are as follows according to the part to be described in Figure 5. 0058] Please refer to FIG. 5, which shows a block diagram of the control logic 402 of the cache memory 400 of the present invention. FIG. 5 also shows an equation describing the combination logic included in each block. [0059] Control logic 402 contains a per_wayJLRU to per_row_LRU encoder 502. per_way—LRU to perjrowJLRU series 23 This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) -------------- ----- Order --------- (Please read the precautions on the back before filling out this page) 556212 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 —--------- --B7 _____ 5. Explanation of the invention (M) The encoder 502 receives the per_wayJLRU [7: 〇] signal 442 in FIG. 4 and generates the per_r〇w_LRU [2: 〇] signal 508 in response to the following equation shown in FIG. 〇per one row_LRU [2] = per—way—LRU [1] Λ // way 0 [1] per—way—LRU [3] Λ // way 1 [1] per one way—LRU [5] Λ / / Way 2 [1] one row— LRU [1] per one way—LRU [7]; // way 3 [1] per. = Per_way_LRU [4] // way 2 [0] one row— LRU [〇] per— way—LRU [6]; // way 3 [0] per = per—way—LRU [0] a // way 0 [0] per one way— LRU [2]; // way 1 [0] [0060 From the equation of per-way-LRU to per_rowJLRU encoder 502, it can be seen that encoder 50 performs a binary mutex or (exciusive-〇R) on per_wayJLRU [7: 0] signal 442 in a predetermined manner. The operation is to encode the LRU information of each channel on the signal 442 into a standard three-bit quasi-LRU format, as described in relation to FIG. 2. [0061] The control logic 402 also includes a replacement circuit generator similar to that in FIG. The permutation path generator 504 of 204. This permutation path generator 504 receives a per-row_LRU [2: 0] signal 508, and responds to the rep 1 acement of FIG. 4 according to the following equation also shown in FIG. way_se 1 ect [3: 0] signal 434 〇 replacement_way_select [0] = ~ per_row_LRU [2] & ~ perj: ow_LRU [0]; replacement_way_select [1 ] = ~ Per—row—LRU [2] & (Please read the notes on the back first Complete this page)

_ _ I I I I Iδ ,, * _ ^ i ϋ mmae I 1 I 24

556212 A7 B7 V. Description of the invention (> +) rep1acement-way-se1ect rep1acement-way-se1ect per-row-LRU [0]; per-row-LRU [2] i ~ per-row-LRU [1]; per_row_LRU [2] & per_row_LRU [1]; [0062] The control logic 402 also includes a per_way_LRU decoder 506. This decoder 506 receives per-way-LRU [7: 0] signal 442, per-row-LRU [2: 0] signal 508, and replacement-way-select [3: 0] signal 434, and responds according to the following equation The ground generates the new_per_way_LRU [1: 0] signal 444 in FIG. Printed by the consumer co-operative of the Intellectual Property Bureau of the Ministry of Economic Affairs, new one per one way—LR | J [1] = replacement one way one select [〇] & // If the replacement road 〇 ~ per one row—LRU [2] & // and per-row-LRU [2] is 0 ~ per-way-LRU [1] 丨 // then switch the bit of road 0 [1] replacement-way-select [1] & // if the road is replaced ι ~ per_row_LRU [2] & " and pe: r'_n) W_LRU [2] is 0 ~ per—way-LRU [3] rep1acement—way_select [2] per one row—LRU [2] ~ per-wayJLRU [5] replacement one way one select [3] & // If Jin Shiyou q has just i ~ peir—way—LRU [7] · '切换 then switch the bit of way 3 [1] new one per—way —LRU [0] = replacement_way_select [〇] & // If the replacement path is 0 ~ per_row_LRU [0] & " and Per_r〇w_LRU [0] is 0 ~ per_way_LRU [0] 丨 々 then switch the way The bit of 〇 [0] replacement_way_select [1] & // If the replacement road per_row_LRU [0] & " And // then switch the bit of the road 1 [1] // If the replacement road 2 // And per-rowjLRU [2] is 1 // then switch the bit of path 2 [1] n ϋ Hi n ϋ ϋ i · i ^ i · ϋ ϋ a ^ in ^ ^ 1 in δν I ϋ— 1§ ϋ n ϋ I · (Please read the precautions on the back before filling out this page) 25 This paper size applies Chinese National Standard (CNS) A4 (210 X 2 ^ Chu {556212 A7 ~ Per one rowJLRU [1] ~ per one way one LRU [4] rep 1 acement_way_.se 1 ec t perjrow one LRU [1] ~ per one way one LRU [6]; Invention description () ~ per_way_LRU [2] 1 " then switch the bit of path i [0] replacement-way—select [2] & // If the replacement path 2 〒 " and per ~ r〇w—LRU [l] is 0 丨 " then switch Bit 2 of way 2 [0] I & // If the way 3 is replaced & and perjrow—LRUUAl // then the bit of way 3 is switched [〇] [0063] from per-way-LRU decoder 5 It can be seen from the equation of 〇6 that the decoder 506 decodes based on the path selected for replacement.

per-row—LRU [2: 0] signal 508 information to generate new lRU information for each channel, where this information is assembled with the other parent channels LRU S όίΐ 468 of Figure 4 read from the other three channels selected The latter will enable the per-way-lru to per-row-LRU encoder 502 to be encoded into the original standard quasi-LRU form, as described below with respect to FIG. 6. [0064] Please refer to FIG. 6, which is a flowchart of how the cache memory 400 of FIG. 4 replaces a cache line according to the present invention. This process starts at block 602. [0065] In block 602, the index 116 of FIG. 4 is sent to the mark array 404 of FIG. 4 through the column selection signal 132 of FIG. 4 to select a row of the mark array 404. Flow proceeds from block 602 to block 604. [0066] In block 604, the per-way_LRU information 468 is read from the selected row of the marker array 404, and sent to the control logic 402 of FIG. 4 through the per-jay_LRU [7: 0] signal 442. The flow proceeds from block 604 to block 606. [0067] In block 606, the per-way_LRU to 26 in Figure 5 are applicable to the Chinese national standard (CNS) A4 specification (21G X 297 mm). ----- ------ Equipment -------- Order -------- (Please read the precautions on the back before filling out this page) The Intellectual Property Bureau of the Ministry of Economic Affairs Prints the wisdom of the Ministry of Economy Printed by the Consumer Cooperative of the Property Bureau 556212 A7 _, a B7 V. Description of the invention (A) per_row-LRU encoder 502 encodes per_way-LRU [7: 〇] signal 442 into perjOW-LRU [2: 0] signal 508, As described in relation to Figure 5. And the per_wayJJJU [7: 0] signal 442 in block 604 reads each of the four ways of the row of the mark array 404 selected by the row selection signal 132. Flow proceeds from block 606 to block 608. [0068] In block 608, the replacement circuit generator 504 of FIG. 18〇611 ^ 111: "^ 7_3616 (: 1: [3: 0] signal 434, as described in the fifth part of the figure. The flow proceeds from block 608 to block 612. [0069] In block 612, the fifth figure The per__way_LRU decoder 506 generates the newjper_wayJLRU [l: 〇l signal 444 in Figure 4 according to per_way_LRU [7: 0] signal 442, per_rowJLRU [2: 0] signal 508, and replacement_way_select [3: 0] signal 434 as replacement_way_select [3 : 0] The replacement path specified on signal 434, as described in the part of Figure 5. The flow proceeds from block 612 to block 614. [0070] In block 614, the new cache line 128 of figure 4 is written The four cache line storage elements 156 selected by the row selection signal 132 and the replacement_way_select [3: 0] signal 434. The flow proceeds from block 614 to block 616. [0071] In block 616, the new mark of FIG. 122 and new one per one way—LRU [1: 0] signal 444 are written together with the mark selected by the row selection signal 132 and replacement__way_select [3: 0] signal 434 and the LRU storage element 454. The flow ends in the block 616. [0072] It can be seen from the embodiments of FIGS. The paper size of this paper is applicable to China National Standard (CNS) A4 (21Q x 297). Please read the precautions on the back before filling this page), the description of the invention (π) is distributed across columns, but it can be updated on a per-channel basis, and the 'quasi-LRU' information is updated when a channel is replaced. This embodiment is special It is suitable for victim cache. However, this embodiment can also simply be used as a cache memory for adopting other LRU update strategies. For example, the quasi-two shells can also be updated when other events occur. , Such as when a load hit is generated (l = ad hit). In such an embodiment, the permutation way generator becomes an accessed way generator "(accessed way generator), which is- When an update event occurs, select the accessed path, and select the least recently used path when replacing a cache line. In addition, the replacement path generator can consider other factors used to select a replacement path.存在 If there is an invalid way in the selected column, choose to replace it instead of choosing the most Path is the least used. [0073] Although the present invention and the objects, features and advantages have been described in detail 'still other embodiments encompassed within the scope of the present invention. For example, the present invention is applicable to an associated cache body with a size of a road, a column, and a cache line that is not in sight. In addition, the combination of the encoding and decoding in the mark __ concept and the __ calculation information can be taken into account that other permutation methods are not limited to the quasi-LRU algorithm. Furthermore, the present invention can also be used to refer to: cache memory, data cache memory, or combined data / instruction cache, memory. Finally, the present invention is not limited to the use of integrating the cache memory and the processing benefits in the phase circuit, but can also secretly separate the cache memory. "The above" is only a preferred embodiment of the present invention, and it is not possible to limit the scope of the present invention. Examination of the application for this invention 556212 A7 _B7_ V. The equal changes and modifications made in the scope of the invention (β) should still fall within the scope of the invention patent. I would like to ask your reviewers to make a clear note and pray for approval. All prayers. (Please read the notes on the back before filling out this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 29 This paper size applies to China National Standard (CNS) A4 (210 X 297 mm)

Claims (1)

Shen Jing's patent scope 1. An N-way associative cache memory, including: an array of f materials, including the first plurality of storage elements, storing a plurality of cache lines configured as M columns and N channels; a standard s array 'It is the turn of the car. The mark array contains a second plurality of storage elements, which are also configured as the M row and the N path. Each: the second plurality of storage elements are used to store the plurality of cache lines. Take the line-marks, each of which is the second plurality of stored information that reads the miscellaneous_when mosquito ν road; and a control logic, reduced to the mark array, configured to be taken from the M column The selected row of households; ^ has N road to read the information, and according to the information 'choose to replace _ of the N road, and only updates the information in the selected road to be replaced. 2. The cache memory described in item 1 of the scope of the patent application, the control logic in & is configured to update the flag and the information for the road selected for replacement in the N road at the same time. 3. The cache memory as described in the first item of the patent scope, wherein the control logic is more evil: for the road selected for replacement in the N road, the plurality of caches corresponding to its marks are updated substantially simultaneously. Take one of the lines and that information. 4. The cache memory as described in item 1 of the scope of the patent application, wherein the control logic is configured to collect the information read by all the N channels to determine the ν of the selected row of the M row. Which way is actually the most suitable paper size for China National Standards (CNS) A4 (210 X 297 mm) (Please read the notes on the back before filling this page) L · ^ Order ----- ---- Printed by the Consumers' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs of the Ministry of Economic Affairs 556212 A8 B8 C8 D8 6. The scope of patent application is the least used. 5. As described in the application for the cache key described in item 4, wherein the control logic is configured to encode the information read from the all N channels into renegade bits, in accordance with a recent The least-used (pseudo-least-recently-used) coding method specifies the N-way towel that is selected for the M column, which is the least recently used on the real f. 6. The cache memory according to item 5 of the scope of the patent application, whose towel n is equal to 407. ^ The cache clock according to the scope of the patent application area 6, which is stored in the mother-the second plural The information of each storage element is composed of two bits. 1 8. For example, please refer to the cache described in the seventh category of the special fiber line, which is based on the quasi-recent least-recent coding method to specify which N-way of the N-way is selected The plurality of bits that have been least recently used include three bits. 9. The cache memory as described in item 4 of the scope of the patent application, wherein the control logic is configured to read the information gathered by all the N channels, and determine the selected row Of the n channels, which one is actually the least recently used, the one among the N channels is selected to be replaced. 10. The cache entry described in item 9 of the patent scope of claim #, wherein the control logic is configured to generate new information, and is only used to update the information in the N channel selected to be replaced. 11. Cache memory as described in item 1Q of the scope of patent application, which refers to 31 paper sizes common national standard (CNS) A4 specification (210 X 297 meals (please read the precautions on the back before (Fill in this page) tr --------- Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. 6. The logic of applying for a patent scope system to generate new information is based on which of the M columns is selected. One way is essentially the least recently used. 12. The cache memory as described in item η of the patent application scope, wherein the control logic is based on the information in the N way that is selected to be replaced, and is generated. The new information. 13. As mentioned, the cache memory described in item 10 of the patent scope, wherein the control logic further generates the new information based on one of the N-paths selected to be replaced. 14. Rushen , The cache memory described in item 13 of the patent scope, wherein the control logic further generates the new information based on the information in the N road that is selected to be replaced. Item described in the cache clock, wherein from M The information obtained from any of the N roads selected in the column cannot individually indicate which path is the most recently used. 16. Cache as described in item 4 of the scope of patent application Memory, where the control logic = group of money by performing an exclusive-OR operation on the negative information read from all the N channels in a predetermined manner, to Read the collected information to determine which of the N channels selected in the M column is the one that has been least recently used in essence. 17. Kinds of N-channel associated cache memory, including: a body array, It is configured as an N channel and includes a plurality of columns, and each of the plurality of columns is configured as an N cache line of an age-to-Lin N channel. One row of the data array also includes an index input terminal to select one of the plurality of columns. 'Lightly connected to the data array, configured as the N road, including a plurality of 556212 printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs C8 ______ D8 VI. Patent application columns, each of which is configured as a cache line The cache line replacement information is distributed across the N Each way in the way only stores-part of the cache line replacement information; a control logic, _ to the directory, configured to receive the cache line replacement from the selected one of the plurality of columns Information, and generate a message to send back in response to the sidebar 5 tiger designated N cache line in the selected one of the plurality of-to replace the cache line in its corresponding data array. 18 · Rushen快 The cache memory described in item 17 of the patent scope, wherein each of the plurality of columns of the directory is configured to store N tags, and the N tags specify at least the N caches corresponding to the existence of the data array A part of an address of one of the lines. 1 19. The cache memory as described in Item 17 of the Patent Application Gu, wherein the mother group of the list of four complex numbers is stored as N state information, and the n The status information specifies a cache status corresponding to the existence of one of the N cache lines on which the asset manager depends. 20. The cache memory as described in item 19 of the scope of the patent application, wherein the N-state information includes whether the corresponding cache line of the N cache lines stored in the data array is modified (m〇 dified), exclusively held, shared or invalid information. 21. The cache memory according to item 17 of the scope of application for patent, wherein the cache line replacement > includes a number of -relying N cache line towels used to determine the complex sequence selected by the index input terminal, Which _ is the most recently used. This paper size is applicable to Chinese National Standard (CNS) A4 (210 X 297 mm) (Please read the precautions on the back before filling this page) 556212 A8 B8 C8 D8 Information on the scope of the patent application 22. The cache memory as described in item 21 of the patent application scope, wherein the control logic includes-decoding H, the ribs encode the cache line into the cache One of the coding forms of the thread replacement information. For example, the cache memory described in Item 22 of Patent No. 1¾, wherein the encoding form of the replacement information of the cache line includes specifying the index input terminal according to a quasi-recently used financial system. Of the N cache lines selected from one of the plural series, which one is the least recently used information. 24. For example, the cache record described in item 22 of the 4 patent scope, wherein the editor performs a mutex or operation on: a predetermined subset of the line replacement information: produces the encoding form: The cache line replacement information is encoded into the encoding form of the cache line replacement information. 25. The cache memory as described in item 17 of the scope of the patent application, wherein the control logic is further configured to generate an updated line placement information and store it in the selected row of the plurality of rows in the catalog in. 26. The cache as described in item 25 of the scope of the patent application = the signal that generates one of the updated fast_N road eight actions. 27 ::: = The cache memory as described in item 25, which is stored in the cache line, and is given individually. 28. The cache for the quick update as described in item 27 of the scope of patent application. The line replacement capital neighbor Baier Putian Qibajia ^ has been exchanged for shellfish. fl contains only used to update corresponding to the _______34 This paper size is applicable to the Chinese National Standard (CNS) l ^^ iFx 297 public love · (Please read the precautions on the back before filling this page} Order ----- ---- Printed by the Consumers' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, 556212 C8 —_____________ D8 _ 6. The cache line replacement information of the part of the M road specified in the scope of patent application. For example, the 17th in the scope of patent application-month The cache memory according to item 1, where ν is 4. The cache memory according to item 1 of the patent application scope, wherein the control logic includes-encoding logic element for selecting from the selected In each of the N channels of the complex sequence ^, a piece of the replacement information of the cache line is received and encoded into coded information to specify that one of the selected complex sequence depends on the N-path, which-way In fact, it has been the least used recently. 31 · —A kind of four-way associative cache memory, which includes a one-byte array 'with M 歹, J, each-the M column has four-way, and each-way has one A cache line storage component to store a cache line and a directory, coupled to the data array, and There are M rows, each of the μ rows = Gu Rongsi Road, and each road has a mark storage element. For the cache line stored in the -beam array-corresponding to the cache line storage # element, store its- Tag, the tag storage element is further configured to store two bits of cache line replacement information; and an encoder 'is input to the directory for use in the four lanes of the M-selected row, Read the eight bits containing the two bit cache line replacement information from each channel, and encode the eight bits into three bits according to the most recently used encoding method, where the Of the four bits in the selected row of the M column, three bits specify which one is actually the least recently used. 32. The cache memory described in item 31 of the scope of patent application, the encoder uses -A predetermined method is used to perform an exclusive OR operation on the eight bit portions to generate the three bits. 35 This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 public love)- ------ (Please read the notes on the back before filling out this page) Order --------- Intellectual Property of the Ministry of Economic Affairs Printed by the Bureau ’s Consumer Cooperatives, Ministry of Economic Affairs ’Intellectual Property Bureau ’s Consumer Cooperatives’ printed agriculture 556212 S__ VI. Patent Application Scope 33. The cache memory described in Item 31 of the Patent Application Scope also includes: Decoder 'car connected to This directory is used to generate two new bits of cache line replacement information to update the four lanes of the selected rank of the M rank, which is actually the least recently used lane. The cache memory according to item 33, wherein the decoder generates the two new bits according to the four lanes of the selected rank of the M rank that are actually the least recently used. 35. The cache memory as described in item 34 of the scope of the patent application, wherein the decoder is more based on the four lanes taken from the selected rank of the M rank, in fact, the roads that have been dare to use less recently The two bit cache lines replace information to generate the two new bits. 36. The cache memory as described in item 31 of the scope of patent application, further comprising: a replacement circuit generator coupled to the directory for generating a signal that specifies the M column according to the three bits One of the four lanes selected is actually the least recently used. 37 · -A kind of cache memory with -integrated tag and cache line master, which includes ·· An array of age elements of M rows by N, each-storage element is used to store a cache Take the line mark and each channel of replacement information, the array has an input terminal for receiving and indexing, the index is used to select one of the M columns of the array; and control logic, tap to the array, configure In order to encode the selected replacement information of the ▲ of the M column, each channel of the N channel into a replacement element of each column to replace the cache information of the cache line replacement information ------- --- ^ -------- Order --------- (Please read the notes on the back before filling out this page) 36 556212 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs A8 B8 C8 D8: The need for a patent-pending part array. 38. The cache memory according to item 37 of the scope of patent application, wherein the replacement information of each column specifies which of the n channels of one of the selected M columns is actually the least recently used. 39. The cache memory according to item 38 of the scope of the patent application, wherein the control logic is further configured to update information on each of the N channels, which is the most recently used channel. 40. The cache memory as described in item 37 of the patent scope of Shenyan, wherein the control logic decodes each channel of replacement information, so that each channel of replacement information can be individually updated without selecting the selected information. Each peak replacement information in each of the N channels in one of the M columns is updated. 41. The cache memory as described in item 37 of the scope of patent application, further comprising: a second array of storage arrays of M rows by N paths, to the control logic, the storage of each second array The device is used to store a cache line corresponding to the mark stored in the first array. 42 · —A kind of N-way associative cache memory, including: a two-dimensional mark and a least recently used (LRU) array, each of the array is configured to store N marks in the N ways of the column , The bus column of the car 歹 J is further configured to store the exact number (pSeu (j〇—) data. The quasi-LRU information includes N partial injuries distributed on the N road of the column. It specifies which of the N channels is the most recently quasi-reduced, and one of the __N marks corresponds to its own LRU information, and each of the _the N parts can be individually marked with the corresponding mark of the n marks. Updates; and _________ 37 paper sizes · _ _Home Fresh -------------------- IT --------- (Please read the (Please fill out this page again) Sixth, the scope of the patent application ^ logic '_ to the array, shouting to receive N parts of the ^ distributed in the column quasi · wei, and exchange X in the cache memory corresponding to a volume and one of the LRU array In the two-dimensional data array, the N parts of the set, ,, fetch, and spring designate the cache line as the least recently used in the column. • The cache memory as described in item 42 of the scope of the second patent, wherein the N parts of the quasi-Bei Xun are distributed in a predetermined manner in all the N ways in the column. 44. The cache memory according to item 42 of the scope of the patent application, wherein the control logic is configured to update the quasi-LRU according to one of the N ways to load hits, the n parts of the body message Part of it. 45. According to the cache memory described in item # of the scope of patent application, if one of the N channels in the column is invalid, the control logic replaces the invalid cache line instead of the quasi Used cache line. 46 · —A method for updating a cache memory having M rows and N ways, including the following steps: selecting one of the M rows from the cache according to a cache line address; ^ read Take the replacement information of the cache line stored in each of the selected N lanes; 'In response to the read action, select one of the selected N lanes — the road force to replace; ϋ The back should read And choose the action of that path 'to generate a new cache line for processing; and' Stomach 38 papers inverse IKEA Standard (CNS) A4 specification (210 X 297 mm) (Please read the precautions on the back before filling in (This page) * · IIIIIII 』= ° J · 1111111 Printed by the Consumers' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, 556212 8888 ABCD, the patent application scope is 4, and the new rapid transfer will replace Zicheng Xinqi Road. The method described in item 46 of the scope of patent application, wherein the action of updating the road includes updating only the road selected in the N channels of the column to be replaced. 48. The method further includes: at the same time as the operation of replacing the information with the new cache line to update the correction, 'the road is also updated with a new cache line. 49. The method as described in item 46 of the scope of patent application, further comprising: at the same time as replacing the information update secret with the new cache line, updating the road with a new cache line mark. 50. The method as described in item 46 of the scope of patent application, wherein the action of selecting a road to be replaced includes: determining which of the N roads that are selected to be actually used the least recently, and The action of reading the replacement information of the cache line stored in each of the N channels of the selected row should be read. (Please read the precautions on the back before filling this page) Order --------- · Printed by the Consumers' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 39 This paper is suitable for finance ii ^ i ?? CNS) A4 " i ¥ (210: 297 mm)