EP3136199B1 - Fraktionierte bandlücke mit niedriger versorgungsspannung und niedrigem strom - Google Patents

Fraktionierte bandlücke mit niedriger versorgungsspannung und niedrigem strom Download PDF

Info

Publication number
EP3136199B1
EP3136199B1 EP16001859.4A EP16001859A EP3136199B1 EP 3136199 B1 EP3136199 B1 EP 3136199B1 EP 16001859 A EP16001859 A EP 16001859A EP 3136199 B1 EP3136199 B1 EP 3136199B1
Authority
EP
European Patent Office
Prior art keywords
current
resistor
coupled
voltage
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
EP16001859.4A
Other languages
English (en)
French (fr)
Other versions
EP3136199A1 (de
Inventor
William Schnaitter
Steve Wang
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ruizhang Technology Ltd Co
Original Assignee
Ruizhang Technology Ltd Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from CN201510523798.2A external-priority patent/CN106484015A/zh
Application filed by Ruizhang Technology Ltd Co filed Critical Ruizhang Technology Ltd Co
Publication of EP3136199A1 publication Critical patent/EP3136199A1/de
Application granted granted Critical
Publication of EP3136199B1 publication Critical patent/EP3136199B1/de
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/30—Regulators using the difference between the base-emitter voltages of two bipolar transistors operating at different current densities

Definitions

  • Radio-frequency identification RFID
  • smartphones From radio-frequency identification (RFID) to mobile devices such as smartphones, manufacturers are constantly pursuing lower power consumption and smaller footprint designs for all of their electronic components.
  • RFID radio-frequency identification
  • bandgap reference circuit One such component used in electronic devices is the bandgap reference circuit.
  • Bandgap reference circuits are typically used to produce temperature independent reference voltages. Typical bandgap reference circuits may have supply requirements of at least 1.8 V. Attempts to provide designs to utilize less than 1.8V typically require three p-n junctions or the circuit may have three possible stable states.
  • low power three p-n junction bandgap reference circuits are more expensive and complex to manufacture compared to higher power two p-n junction bandgap reference circuits. Therefore, manufacturers must make a tradeoff in design for power versus size and cost.
  • a three-state design creates added complexity when designing and implementing a proper start-up circuit in comparison to start up circuits which may be used with a two state bandgap circuit design.
  • bandgap reference circuits are needed which can have low power usage as well as an efficient footprint.
  • US 2010/301832 A1 a system and a method for generating a curvature compensated bandgap voltage reference are known. This is achieved by injecting a temperature dependent current at different points in the bandgap voltage reference circuit.
  • US 7,768,343 B1 shows a start-up circuit for a bandgap reference circuit that includes a sampling circuit for sampling current through a diode in one of first and second diode/resistor networks that respectively provide complementary PTAT and CTAT characteristics in the bandgap reference.
  • WO 2010/062285 A1 relates to circuits for generating a temperature compensating reference voltage. Such circuits may include a Bandgap reference circuit.
  • a bandgap reference circuit comprising two NMOS transistors, where the first NMOS transistor is driven by a PTAT current source and the second transistor is driven by a PTVBE current source, is disclosed.
  • a reference voltage generating circuit includes a first servo loop (e.g., a PTAT servo loop) comprising a first p-n junction with a first current density and a second p-n junction with a second current density different than the first current density, a second servo loop (e.g., a CTAT servo loop) shares the first or the second p-n junction of the first servo loop, and a resistor coupled to the two servo loops and ground, wherein the voltage across the resistor is the reference voltage output.
  • a first servo loop e.g., a PTAT servo loop
  • a second servo loop e.g., a CTAT servo loop
  • the reference voltage generating circuit includes a start-up circuit to ensure operation in a desired stable state and a gain-boost technique of current mirroring that achieves operation at a low supply voltage.
  • the current from the PTAT servo loop and the current from the CTAT servo loop are combined in a configurable ratio, wherein the configurable ratio determines one or more of: a regulated temperature independent current, a canceling of temperature dependence of the resistor, or a regulated current source with a configurable temperature dependence.
  • a method for provides a reference voltage.
  • the method may include generating a first current with a first servo loop comprising a first p-n junction.
  • the method may also include generating a second current with a second p-n junction, wherein a second servo loop is connected to one of the first or the second p-n junctions of the first servo loop.
  • the method may also include outputting the reference voltage from a resistor coupled to the two servo loops and ground.
  • a reference voltage generating circuit is described herein as a fractional bandgap circuit (referred to herein simply as "FBC") to provide a low-current, low-voltage, and temperature independent reference output.
  • the FBC implements two servo loops, a first of which produces a current that is proportional to absolute temperature (PTAT) and a second that produces a current that is complementary to absolute temperature (CTAT).
  • the two servo loops may be combined with a resistor having a voltage independent of temperature.
  • the CTAT and PTAT are ratioed such that the temperature dependence of the voltage independent resistor is cancelled and the FBC has little to no temperature dependence.
  • the FBC generates a first current PTAT with a first servo loop using two p-n junctions of differing current density. Unlike other bandgap circuit designs utilizing three p-n junctions, the FBC described herein utilizes two p-n junctions which saves area during manufacturing and can leverage lower cost wafer processing.
  • a gain boost servo loop is connected with the PTAT servo loop to allow accurate mirroring at low supply voltage.
  • a third servo loop uses the voltage at one of the first two p-n junctions to generate a second current complementary to absolute temperature (CTAT).
  • CTAT current complementary to absolute temperature
  • Current mirrors that replicate the internal current of the CTAT servo loop do not need a servo to allow accurate mirroring at low supply voltage.
  • the mirrored PTAT and CTAT currents may be combined in a resistor to ground, to generate an output voltage that is a fixed fraction of the silicon bandgap voltage.
  • the output voltage is independent of process, temperature and supply voltage. Trimming techniques (e.g., with spare resistors or current mirrors, or both), may be added to allow trimming to a very accurate level if desired. Other trimming techniques known to those skilled in the art are also possible.
  • the mirrored PTAT and CTAT currents are not equal and are opposite in temperature dependence.
  • the output resistor of the FBC may have some known temperature dependence and the mirrored PTAT and CTAT currents that generate the fixed output reference voltage may be ratioed so that the temperature dependence of the combined currents accurately compensates for that of the output resistor. For example, if the temperature dependence of the output resistor were negative, the ratio of currents may be adjusted to compensate for that dependence by having additional PTAT current. The resulting fractional bandgap output voltage will be temperature-independent.
  • two additional mirrored currents are summed to create a regulated, temperature-independent current.
  • the temperature-independent current is used with further mirroring to provide a regulated temperature-independent bias current utilized by the internal components of the design to maintain accurate performance and reliable circuit behavior.
  • that current is used to generate and provide multiple regulated temperature-independent currents which may be used by other circuits outside the fractional bandgap.
  • the CTAT current may be further mirrored to provide a regulated CTAT current source for an other circuit to use, to compensate for the PTAT dependence of those other circuits.
  • the PTAT current can be further mirrored to provide a regulated PTAT current source for use in other circuits, to compensate for the CTAT dependence of those other circuits.
  • a thermometer circuit may benefit from the regulated PTAT current source because a thermometer circuit may depend on the PTAT loop for the proportional to absolute temperature readings as well as the overall bandgap reference voltage.
  • one mirrored PTAT current and one mirrored CTAT current may be ratioed as desired and combined to generate a current of any temperature-dependence, over a wide range, which may be needed for still other circuits.
  • a wide range might be -40 to 100 oC.
  • a "narrow" range of interest might be the temperature inside a meat storage unit where one wants to know the temperature, for example between -2 and +6 oC, to an accuracy of 0.25 oC.
  • Other implementations or ranges are also possible within the scope of the embodiments described herein.
  • the FBC described herein may have two stable states, which enables use with a wide variety of two state compatible start-up circuits.
  • the FBC assumes either of two stable states, and a novel start-up circuit is provided to ensure that the circuit enters the desirable stable state.
  • the start-up circuit can include a small capacitor and two transistors and may be manufactured with a low area low cost circuit.
  • FBC uses the described start-up circuit to initialize with zero current after startup. Further details of this start-up circuit are described below with regards to FIG. 7 below.
  • a U-shaped resistor element layout technique achieves high resistance in small area by flipping resistor elements.
  • minimizing the size of a circuit is highly beneficial for real world applications in electronic components.
  • resistors may take up a large percentage of the total area of the circuit.
  • the high density layout is achieved by using alternately-flipped "U-shaped" resistor elements to use minimum spacing across the length of the resistor. Further details of this resistor element layout are described below with regards to FIG. 9 .
  • FIG. 1 is a block and circuit diagram of a fractional bandgap circuit, in one embodiment.
  • the FBC 100 uses two servo loops to generate a PTAT (i.e., a first servo loop 110) and a CTAT (i.e., a second servo loop 120) current, respectively. These currents may be mirrored at a desired ratio into a resistor, R 0 (e.g., resistor 130) to ground. The voltage across this resistor is the primary output voltage, vBgf 150.
  • the FBC also generates similarly a temperature-independent current, iZtc 140.
  • the sum of the two currents into R 0 may not be independent of temperature. Rather, the two currents may be setup with a ratio to have a temperature-dependence complementary to that of R 0 , a high-resistivity (e.g., 1000 ⁇ /sq. or other resistance) resistor (e.g., a poly-silicon resistor).
  • a high-resistivity e.g., 1000 ⁇ /sq. or other resistance
  • the two currents summed to create iZtc a temperature independent current, are of equal but opposite temperature coefficient.
  • R 0 is made up of many small identical resistor elements in series.
  • the current from the PTAT servo loop and the current from the CTAT servo loop are combined in a configurable ratio.
  • the configurable ratio determines (i.e., can be used to modify or affect) one or more of: a regulated temperature independent current, a canceling of temperature dependence of the resistor, or a regulated current source with a configurable temperature dependence.
  • FIG. 2 is a block and circuit diagram of a PTAT servo loop, in one embodiment.
  • the PTAT servo loop 200 forces a ratioed pair of currents into a pair of unequal vertical PNP transistors (e.g., as illustrated by Q 1 205 and Q 2 210).
  • These BJT's may be composed of common-centroided identical parallel small elements of a vertical PNP transistor cell: b 1 elements for Q 1 205 the high-current-density device; and b 2 for Q 2 210, the low-current-density device.
  • the current sources into these are made up of pMos transistors with identical, common-centroided elements, m1 transistor elements for the current into Q 1 205 and m 2 elements into Q 2 210.
  • the ratio of current density is (b 2 / b 1 ) ⁇ (m 1 /m 2 ).
  • this ratio is called "gamma,” ⁇ and is independent of process, temperature and supply voltage variations.
  • the illustrated PTAT servo-loop adjusts elemental currents of M 1 and M 2 so that the voltage on the node q 1 215 (V BE1 ) is equal to the voltage on eq 1 220, which is the voltage across the series combination of R 1 225 and Q 2 210.
  • the voltage across R 1 225 is represented by ⁇ V BE , equal to the difference between the V BE voltages on Q 1 205 and Q 2 210.
  • the currents of the resistor and of the current sources are PTAT.
  • Voltages V BE1 and V BE2 on Q 1 205 and Q 2 210 are CTAT, complementary to absolute temperature, given a PTAT current.
  • R 1 225 is made up of segments of identical resistor elements.
  • the R 1 225 resistor elements may be identical to, and common-centroided with, those elements in the main R 0 130 resistor used for the vBgf output voltage 150.
  • the currents through M 1 230 and M 2 235 are at a constant ratio of m 1 /m 2 . This ratio is very accurate when the loop is in regulation, since the drain voltages are then very nearly equal, along with the source, gate and body terminals being tied together.
  • the currents are PTAT, since the M 2 235 current equals the R 1 225 current.
  • currents through M 1 230 and M 2 235 are mirrored in a fixed ratio through two additional transistors, M 3 240 and M 3B 245, to provide two PTAT currents from this module (e.g., as illustrated in FIG. 1 ).
  • transistors M 3 240 and M 3B 245 are also made up of elements identical to, and common-centroided with, those of M 1 230 and M 2 235.
  • FIG. 3 is a block and circuit diagram of a CTAT servo loop, in one embodiment.
  • the CTAT servo loop 300 adjusts the current into another resistor, R 2 , 305 to equate the resistor voltage on the eq 2 node (V R2 ) to the V BE2 on Q 2 generated in the PTAT servo loop 200.
  • V R2 is a CTAT voltage
  • the current of the R 2 305 resistor (and of M 4 310) is CTAT.
  • the R 2 305 resistor illustrated in FIG. 3 is made up of segments of identical resistor elements in series, identical to and common-centroided with those elements in the R 0 130 and R 1 225 resistors of FIG. 1 and 2 respectively.
  • the ratios between the resistors will remain as accurate constants.
  • the servo loop equates the R 2 305 voltage to V BE2 325, a CTAT voltage, the current, 14 330, through the resistor is CTAT, and so also through the transistor M 4 310. In one embodiment, this current is mirrored in a fixed ratio through two additional transistors, M 5 315 and M 5B 320.
  • M 5 315 and M 5B 320 provide the two CTAT currents from this module shown in FIG.1 (One more additional transistor, not shown, can provide an additional mirrored CTAT current, not shown in FIG. 1 , from the CTAT servo loop directly to another integrated circuit outside the FBC.)
  • FIG. 4 is a block and circuit diagram of fractional bandgap circuit, in another embodiment. As illustrated in FIG. 4 , the fractional bandgap circuit 400 includes both the CTAT and PTAT servo loops. From the simplified overall diagram illustrated in FIG.
  • V BE 2 + A ⁇ R 2 B ⁇ R 1 ⁇ V BE V BE2 is a full bandgap expression that is unaffected by the choice of R 0 .
  • the values for A, B, R 2 and R 1 are such that the total voltage in V BE2 + A ⁇ R 2 B ⁇ R 1 ⁇ V BE is temperature independent.
  • the final value of the fractional bandgap output is a fixed fraction of a full bandgap voltage.
  • the magnitude of vBgf 405 may be configured according to the number of resistor elements that make up R 0 410.
  • the value of vBgf may be configured by tapping off the output from the R 0 410 resistor stack (e.g., with additional optional resistor elements) by an analog mux or by metal options (e.g., the amount or configuration of the metal composition) in an integrated circuit fabrication mask.
  • the FBC is configured to produce a fractional bandgap voltage of around 365mV, equally valid fractional bandgap voltages may be created by tapping off the resistor R 0 410.
  • the R 0 410 resistor used to determine the final magnitude of the fractional bandgap output may be a stack of resistor elements in series to allow accurate ratio'ing and common-centroiding.
  • a basic fractional bandgap output of 0.36 V is obtained with 30 resistor elements in R 0 .
  • other additional voltages may be output by tapping off the R 0 stack below the top and adjusting the number of resistor elements.
  • the alternate number of resistor elements can provide other/configurable fractional bandgap output voltages.
  • the R 1 415 resistor in the PTAT servo loop has the delta V BE PTAT voltage, which is not temperature independent.
  • FIG. 5 is a block and circuit diagram of a PTAT servo loop with gain boost, according to an example useful for understanding the present invention, but not falling within the claimed invention.
  • a minimum supply voltage of approximately .68V and a supply current of approximately 190nA may produce a variation over temperature, supply and process of approximately 5%.
  • the output voltage of this example configuration will be approximately 365mV and the resulting FBC design may utilize an area of about 6500 ⁇ m 2 .
  • the PTAT servo loop forward V BE1 voltage (a CTAT voltage) across Q 1 may rise to around 680 mV.
  • the current from M 3 515 of the PTAT servo loop, mirroring from M 1 505 and M 2 510, may become inaccurate.
  • the supply voltage, minus a small overhead voltage needed by M 1 505, would approach V BE1 .
  • One reason for the inaccuracy of the mirroring is that the drain-to-source voltage of M 3 515 (and M 3B 520) may be much greater than that of M 1 505 and M 2 510.
  • a "gain-boost" type loop was added to the circuitry of the PTAT servo loop to improve accuracy of the FBC.
  • the gain-boost loop illustrated in FIG. 5 may control the gates of cascode transistors added in series to the M 3 515 and M 3B 520 output transistors.
  • the gate bias of the cascode transistors affects the VDS of M 3 515 and M 3B 520.
  • servoing the gate bias so that the voltage with respect to vdda at node x 1 525 is matched to the voltage with respect to vdda at node q 1 , enables all terminals of M 3 515 to match those of M 1 505 and the currents will be equal, increasing overall circuit accuracy.
  • the voltage at node x 2 530 should be close to that at x 1 525 and the accuracy of the iPtat2 output 540 is not as critical. Thus, only one servo loop is used. However, in another embodiment, another servo loop could similarly servo the gate of M C2 550 such that the voltage at node x 2 530 is equal to the voltage at node x 1 525.
  • a similar gain boost mechanism is added to the CTAT servo loop, however the accuracy is not as affected at some voltages (e.g., around 700 mV) compared to the PTAT servo loop because the drain/source voltage of M 4 310 will not be nearly as low as for M 1 230 and M 2 235. Therefore, q 2 may be used as the reference for the CTAT servo loop rather than q 1 , which would be a higher voltage. Additionally, a higher reference voltage would require a combination of a larger R 2 or greater resistor current, neither of which is to be desired. Accordingly, in some examples outside the scope of protection, the lower q 2 voltage is utilized as the preferred reference for the CTAT servo loop. As an illustrated example using the example characteristics introduced for the FBC of FIG. 5 , at -40 °C, q 2 voltage may be about (680 mV - (nkT/q)lny, or approximately 613 mV.
  • FIG. 6 is a block and circuit diagram to generate currents with various temperature dependence, for use in other circuits outside the bandgap circuit, according to an example useful for understanding the present invention, but not falling within the claimed invention.
  • a "zero-TC" current with zero temperature dependence is generated.
  • This current may flow into a diode-connected nMos transistor, M N0 .
  • the gate voltage of M N0 is termed “biasN” and will be at a voltage level consistent with the drain current.
  • This gate voltage can be used in current mirroring to M N1 , M N2 , M N3 , etc., with various "m" counts, to generate multiple temperature-independent currents for use in other circuits.
  • the M N1 mirror transistors can be co-located, even commonly-centroided, with M N0 , with the output currents bussed to the other circuits, for better accuracy.
  • adding another PTAT transistor, for example M 3C , with biasPtat on the gate, will create the PTAT current 680 from bandgap circuit 640.
  • a PTAT current could simply go through a resistor to ground. Since the current is simply a multiple of I 2 (i.e., I 2 of FIG. 2 ) and the resistor can be made up of the same elements as R 1 (i.e., R 1 of FIG. 2 ), the voltage with respect to ground across this resistor is proportional to absolute temperature and can form the input to an A-to-D converter with the output being a digital expression of the absolute temperature.
  • FIG. 7 is a block and circuit diagram of start up circuit, in one embodiment.
  • the undesirable stable state is where the op amp outputs are at the vdda rail and no current is produced by the current sources so the op amp inputs are at the ground rail.
  • the op amp output 705 e.g., a differential op amp
  • the capacitor, C 1 720 helps ensure that the node "b" 715 is close to ground during any power-up.
  • M 12 710 As the current in M 12 710 rises, along with the servo-loop current sources, C 1 720 is charged to the supply voltage and M 11 725 (e.g., a PMOS transistor) will be guaranteed to be off.
  • M 11 725 e.g., a PMOS transistor
  • M 12 710 When the power supply voltage is high enough to get current out of PTAT servo loop's I 1 , I 2 , and I 3 , then M 12 710 will also have current because the op amp output is being pulled down to turn on I 1 , I 2 , and I 3 .
  • the start up circuit will turn on M 12 710 which pulls the node "b" 715 up to Vdd, while shutting down M 11 725 after the startup. Therefore, the startup circuit current after startup may be considered zero.
  • the start up circuit 700 of FIG. 7 is considered complete and functional for integration with the FBC with just the three startup components: two transistors (e.g., M 11 725, M 12 710), and a single capacitor (e.g., capacitor C 1 720). Furthermore, during fabrication/manufacture the single capacitor C 1 720 may be physically coupled to the top of M 11 725 and M 12 710 such that the capacitor C 1 720 takes little to no surface area on its own.
  • the startup circuit is implemented for the q 1 and eq 1 of the PTAT servo loop 200.
  • startup circuit 700 may be coupled to the upper op amp of FIG. 4 .
  • the CTAT servo loop 300 is guaranteed to startup correctly as long as the q2 input starts up correctly, therefore the CTAT servo loop may be implemented without a startup circuit.
  • the startup circuit will guarantee the PTAT servo loop starts up correctly at the correct stable point of the two stable points.
  • the FBC with startup circuit utilizes a bias current for the op amps.
  • the FBC itself may be used to generate this bias current.
  • the startup circuit provides the initial bias current by pulling down the gates of the current sources in the two loops, as discussed above. Thus those sources will provide initial current to the biasN node (and to the diode-connected nMos transistor). Once the bandgap circuit stabilizes, including both the PTAT and CTAT servo loops, the biasN node is at a stable voltage and the needed bias currents will thus be generated in the op amps.
  • FIG. 8 is a traditional resistor element layout diagram.
  • the poly-silicon resistor elements 800 are simply long narrow lines with a contact at each end.
  • the line width may be 0.6um or larger.
  • the poly spacing may be forced to a minimum of 0.34um, compared to the design rule for poly spacing, which is only 0.25 um. With these example characteristics, the total resistance/unit area is only about 1.675 k ⁇ /um 2 .
  • FIG. 9 is a flipped U-shaped resistor element layout diagram, in one embodiment.
  • the FBC described herein utilizes very small currents and therefore very large resistors are required to achieve the voltages in the hundreds of mV.
  • a resistor voltage of 350 mV with a current of only 35 nA requires a resistance of 10 M ⁇ .
  • the area of such a 10 M ⁇ resistor may be greater than 42.5k um 2 .
  • resistors R 1 , R 2 , and R 0 in the illustrated examples of FIG. 1-5 may total 29.23 M ⁇ or greater with spares, and may total over 124k um 2 . This may be too large an area for practical application and may be many times the area budget for the entire bandgap circuit.
  • the FBC resistors may use many elements to allow common-centroiding, and reasonable resolution for choosing values for the desired resistor ratios.
  • the resistor element size may be determined as a small fraction of the total resistance of any of the three main resistors discussed above (e.g., R 1 , R 2 , and Ro).
  • the layout of the resistor element of FIG. 9 is a flipped U-shaped configuration and resistor layouts can leverage the compact physical arrangement in alternating orientation, as illustrated. In one embodiment, this U-shaped resistor element design allows the full length of the element to use minimum spacing and reduces the overhead of the end contacts to a small percentage of overall area.
  • the resistor may be connected to the FBC at input 950 and continue with a tap 955 to bring the two resistor elements together.
  • the resistor elements of FIG. 9 may be connected together through a final resistor element and output 960.
  • FIG. 9 is a single resistor, however multiple instances of the resistor of FIG. 9 may be combined, for example in a common centroid pattern as discussed below.
  • the currents are matched to the FBC resistor by centroiding. For example, as illustrated in FIG. 4 , R 1 , R 2 , and R 0 may be arranged in a centroid design with a common array of resistor elements.
  • the technique used in traditional large resister designs results in a density of 1.68 k ⁇ /um 2 .
  • a poly line-width of 0.6 um was used.
  • the layout technique required spacing of 0.34 um, vs. a minimum spacing allowed of 0.25 um.
  • Pushed to the same narrow poly line-width of 0.24 um one can get 6.71 k ⁇ /um 2 .
  • the flipped u-shaped resistor element can achieve 11.4 k ⁇ /um 2 or greater total resistance/unit area. Therefore, a large resistor with this U-shaped design can take up far less real estate on the silicon.
  • the total area of the resistors in the FBC illustrated in FIG. 1 may be about 2800 um 2 .
  • the resistors in the FBC may be laid out in a common-centroid arrangement of numerous smaller resistor elements to maintain maximum matching accuracy in the resistor ratios.
  • three resistors, R 0 , R 1 , and R 2 may be arranged in a sequence of: [R 0 R 1 R 2 R 0 R 1 R 1 R 0 R 2 R 1 R 0 ], where the four R 0 elements would be connected in series, with the geometric center of them in the center of the arrangement.
  • the four R 1 elements above would also be connected in series, with the geometric center of them also in the center of the arrangement.
  • the two R 2 elements above would be connected in series, with the geometric center of them also in the center of the arrangement.
  • the ratio of the resistance of this example common-centroid arrangement above R 0 :R 1 :R 2 would be 2:2:1.
  • a common-centroid arrangement may guard against a linear variation in the resistor value as a function of position. This variation would average out with a presumption that the metal connecting the resistor elements is of negligible resistance.
  • FIG. 10 illustrates a flow diagram of a method to generate a reference voltage, in one embodiment.
  • the embodiment e.g., a method for generating reference voltage implemented by a circuit such as the circuit including the FBC described herein
  • initializes, from a start up circuit e.g., circuit 700
  • a reference voltage generating circuit e.g., the FBC 100.
  • the embodiment generates, within the reference voltage generating circuit, a first current with a first servo loop including a first p-n junction.
  • the first servo loop may be a PTAT servo loop (e.g., PTAT servo loop 110).
  • the embodiment generates, within the reference voltage generating circuit, a second current with a second p-n junction, where a second servo loop shares the first or the second p-n junction of the first servo loop.
  • the second servo loop may be a CTAT servo loop (e.g., CTAT servo loop 120).
  • the embodiment mirrors current from the reference voltage generating circuit with a gain boost servo loop.
  • a gain boost servo loop For example, the gain boost servo loop as illustrated in FIG. 5 .
  • the embodiment outputs reference voltage of the reference voltage generating circuit using a resistor coupled to the first servo loop, second servo loop, and to ground.
  • the voltage is determined according to metal composition of the resistor, or an analog mux.
  • signals may be represented with lines. Some lines may be thicker, to indicate more constituent signal paths, and/or have arrows at one or more ends, to indicate primary information flow direction. Such indications are not intended to be limiting. Rather, the lines are used in connection with one or more exemplary embodiments to facilitate easier understanding of a circuit or a logical unit. Any represented signal, as dictated by design needs or preferences, may actually comprise one or more signals that may travel in either direction and may be implemented with any suitable type of signal scheme.
  • connection means a direct electrical connection between the things that are connected, without any intermediary devices.
  • coupled means either a direct electrical connection between the things that are connected, or an indirect connection through one or more passive or active intermediary devices.
  • circuit means one or more passive and/or active components that are arranged to cooperate with one another to provide a desired function.
  • signal means at least one current signal, voltage signal or data/clock signal.
  • the transistors are metal oxide semiconductor (MOS) transistors, which include drain, source, gate, and bulk terminals. Source and drain terminals may be identical terminals and are interchangeably used herein.
  • MOS metal oxide semiconductor
  • CMOS complementary metal oxide semiconductor
  • transistors for example, Bi-polar junction transistors-BJT PNP/NPN, BiCMOS, CMOS, etc., may be used without departing from the scope of the disclosure.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Nonlinear Science (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Automation & Control Theory (AREA)
  • Control Of Electrical Variables (AREA)

Claims (9)

  1. Schaltung (400) zum Erzeugen einer Referenzspannung, Folgendes umfassend:
    einen Proportional-Zur-Absoluten-Temperatur, (proportional to absolute temperature) PTAT, Regelkreis (200), der folgendes umfasst:
    einen ersten Operationsverstärker (215); eine erste als Diode geschaltete Transistorvorrichtung (Q1) mit einer ersten Stromdichte, die mit einem ersten Eingang des ersten Operationsverstärkers (215) verbunden ist, und eine zweite als Diode geschaltete Transistorvorrichtung (Q2) mit einer von der ersten Stromdichte verschiedenen zweiten Stromdichte, die mit einem zweiten Eingang des ersten Operationsverstärkers (215) verbunden ist;
    einen ersten MOS-Transistor (M1), der mit einem Ausgang des ersten Operationsverstärkers (215) verbunden ist und der mit der ersten Transistorvorrichtung (Q1) verbunden ist;
    einen zweiten MOS-Transistor (M2), der mit dem ersten MOS-Transistor (M1) verbunden ist;
    einen dritten MOS-Transistor (M3), der mit dem zweiten MOS-Transistor (M2) verbunden ist und der dafür vorgesehen ist, einen ersten Strom (iPtat) auszugeben; und
    einen ersten Widerstand (415), der mit der zweiten Transistorvorrichtung (Q2) verbunden ist und der dafür vorgesehen ist, eine erste Spannung (VBE2) auszugeben, wobei das andere Ende des ersten Widerstands mit dem zweiten MOS-Transistor und dem zweiten Eingang des ersten Operationsverstärkers verbunden ist;
    einen Komplementär-Zur-Absoluten-Temperatur, (complementary to absolute temperature) CTAT, Regelkreis (300), der folgendes umfasst:
    einen zweiten Operationsverstärkers (325), der einen ersten Eingang umfasst, der mit dem ersten Widerstand (415) verbunden ist, um die erste Spannung (VBE2) zu empfangen;
    einen vierten MOS-Transistor (M4), der mit einem Ausgang des zweiten Operationsverstärkers (325) verbunden ist und der mit einem zweiten Eingang des zweiten Operationsverstärkers (325) verbunden ist; und
    einen fünften MOS-Transistor (M5), der mit dem vierten MOS-Transistor (M4) verbunden ist und der dafür vorgesehen ist, basierend auf der ersten Spannung (VBE2) einen zweiten Strom (iCtat) auszugeben; und
    wobei die Schaltung zum Erzeugen einer Referenzspannung auch einen zweiten Widerstand (410) umfasst, der mit dem PTAT-Regelkreis und dem CTAT-Regelkreis verbunden ist, um den ersten bzw. den zweiten Strom zu empfangen, sowie mit Masse, wobei ein Spannungsabfall über den zweiten Widerstand eine Referenzspannung (vBgf) ist.
  2. Schaltung nach Anspruch 1, wobei der erste Strom und der zweite Strom im zweiten Widerstand in einem einstellbaren Verhältnis kombiniert werden, um eine oder mehrere der folgenden Funktionen bereitzustellen:
    einen geregelten, temperaturunabhängigen Strom,
    ein Ausgleichen der Temperaturabhängigkeit des Widerstands, oder
    eine geregelte Stromquelle mit einer einstellbaren Temperaturabhängigkeit.
  3. Schaltung nach Anspruch 1, wobei der zweite Widerstand einen Widerstandsstapel umfasst.
  4. Schaltung nach Anspruch 1, außerdem Folgendes umfassend:
    eine Anlaufschaltung (700), die mit dem PTAT-Regelkreis verbunden ist, wobei die Anlaufschaltung (700) Folgendes umfasst:
    einen einzelnen Kondensator (720); und
    zwei Transistoren (710 und 725), die mit dem einzelnen Kondensator verbunden sind.
  5. Schaltung nach Anspruch 1, wobei der zweite Widerstand mehrere Widerstände umfasst, die in einer umgedrehten U-förmigen Konfiguration (910) angeordnet sind.
  6. Verfahren zum Bereitstellen einer Referenzspannung, wobei das Verfahren Folgendes umfasst:
    Erzeugen eines ersten Stroms (iPtat) mit einem Proportional-Zur-Absoluten-Temperatur, (proportional to absolute temperature) PTAT, Regelkreis (200), der folgendes umfasst: einen ersten Operationsverstärker (215); eine erste als Diode geschaltete Transistorvorrichtung (Q1) mit einer ersten Stromdichte, die mit einem ersten Eingang des ersten Operationsverstärkers (215) verbunden ist, und eine zweite als Diode geschaltete Transistorvorrichtung (Q2) mit einer von der ersten Stromdichte verschiedenen zweiten Stromdichte, die mit einem zweiten Eingang des ersten Operationsverstärkers (215) verbunden ist; einen ersten MOS-Transistor (M1), der mit einem Ausgang des ersten Operationsverstärkers (215) verbunden ist, einen zweiten MOS-Transistor (M2), der mit dem ersten MOS-Transistor verbunden ist, und einen dritten MOS-Transistor (M3), der mit dem zweiten MOS-Transistor (M2) verbunden ist; und einen ersten Widerstand (415), der mit der zweiten Transistorvorrichtung (Q2) verbunden ist und der dafür vorgesehen ist, eine erste Spannung (VBE2) auszugeben;
    Erzeugen eines zweiten Stroms (iCtat) basierend auf der ersten Spannung (VBE2) unter Verwendung eines Komplementär-Zur-Absoluten-Temperatur, (complementary to absolute temperature) CTAT, Regelkreises (300), der folgendes umfasst: einen zweiten Operationsverstärkers (325), der einen ersten Eingang umfasst, der mit dem ersten Widerstand (415) verbunden ist, um die erste Spannung (VBE2) zu empfangen; einen vierten MOS-Transistor (M4), der mit einem Ausgang des zweiten Operationsverstärkers (325) verbunden ist; und einen fünften MOS-Transistor (M5), der mit dem vierten MOS-Transistor (M4) verbunden ist; und
    Ausgeben der Referenzspannung (vBgf) von einem zweiten Widerstand (410), der mit dem PTAT-Regelkreis und dem CTAT-Regelkreis verbunden ist, um den ersten bzw. den zweiten Strom zu empfangen, sowie mit Masse.
  7. Verfahren nach Anspruch 6, außerdem Folgendes umfassend:
    Kombinieren des ersten Stroms und des zweiten Stroms entsprechend einem einstellbaren Verhältnis, um eine oder mehrere der folgenden Funktionen bereitzustellen:
    einen geregelten, temperaturunabhängigen Strom,
    ein Ausgleichen der Temperaturabhängigkeit des Widerstands, oder
    eine geregelte Stromquelle mit einer einstellbaren Temperaturabhängigkeit.
  8. Verfahren nach Anspruch 6, außerdem Folgendes umfassend:
    Bestimmen der Referenzspannungsausgabe entsprechend einer Metallzusammensetzung des zweiten Widerstands, oder unter Verwendung einer analogen MUX-Vorrichtung.
  9. Verfahren nach Anspruch 6, wobei der zweite Widerstand mehrere Widerstände umfasst, die in einer umgedrehten U-förmigen Konfiguration (910) angeordnet sind.
EP16001859.4A 2015-08-24 2016-08-24 Fraktionierte bandlücke mit niedriger versorgungsspannung und niedrigem strom Active EP3136199B1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201510523798.2A CN106484015A (zh) 2015-08-24 2015-08-24 基准电压产生电路、及提供基准电压的方法
US14/845,244 US9921601B2 (en) 2015-08-24 2015-09-03 Fractional bandgap circuit with low supply voltage and low current

Publications (2)

Publication Number Publication Date
EP3136199A1 EP3136199A1 (de) 2017-03-01
EP3136199B1 true EP3136199B1 (de) 2022-11-02

Family

ID=56851323

Family Applications (1)

Application Number Title Priority Date Filing Date
EP16001859.4A Active EP3136199B1 (de) 2015-08-24 2016-08-24 Fraktionierte bandlücke mit niedriger versorgungsspannung und niedrigem strom

Country Status (1)

Country Link
EP (1) EP3136199B1 (de)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11029718B2 (en) 2017-09-29 2021-06-08 Intel Corporation Low noise bandgap reference apparatus

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6366071B1 (en) * 2001-07-12 2002-04-02 Taiwan Semiconductor Manufacturing Company Low voltage supply bandgap reference circuit using PTAT and PTVBE current source
CN101901018A (zh) * 2009-05-26 2010-12-01 上海华虹Nec电子有限公司 电压基准电路

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7768343B1 (en) * 2007-06-18 2010-08-03 Marvell International Ltd. Start-up circuit for bandgap reference
TW200910050A (en) * 2007-08-22 2009-03-01 Faraday Tech Corp Bandgap reference circuit
CN102246115B (zh) * 2008-11-25 2014-04-02 凌力尔特有限公司 用于半导体芯片内金属电阻器的温度补偿的电路、调修和布图
US8106707B2 (en) * 2009-05-29 2012-01-31 Broadcom Corporation Curvature compensated bandgap voltage reference

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6366071B1 (en) * 2001-07-12 2002-04-02 Taiwan Semiconductor Manufacturing Company Low voltage supply bandgap reference circuit using PTAT and PTVBE current source
CN101901018A (zh) * 2009-05-26 2010-12-01 上海华虹Nec电子有限公司 电压基准电路

Also Published As

Publication number Publication date
EP3136199A1 (de) 2017-03-01

Similar Documents

Publication Publication Date Title
US11029714B2 (en) Flipped gate current reference and method of using
US10289145B2 (en) Voltage generating circuit
US7750728B2 (en) Reference voltage circuit
JP5996283B2 (ja) 電圧発生回路を備える半導体装置
US7633333B2 (en) Systems, apparatus and methods relating to bandgap circuits
CN109976425B (zh) 一种低温度系数基准源电路
CN108536207B (zh) 电流产生电路和包括其的带隙基准电路及半导体器件
US8922190B2 (en) Band gap reference voltage generator
CN113168200B (zh) 利用修整调节的精确带隙参考
EP2905672A1 (de) Vorrichtung und Verfahren für eine gewünschte Brokaw-Bandlückenreferenzschaltung für verbesserte Niederspannungsversorgung
US10416702B2 (en) Bandgap reference circuit, corresponding device and method
EP2207073A2 (de) Schaltung zur Einstellung des Temperaturkoeffizienten eines Widerstands
EP2555078B1 (de) Referenzschaltungsanordnung und Verfahren zur Erzeugung einer Referenzspannung
EP3136199B1 (de) Fraktionierte bandlücke mit niedriger versorgungsspannung und niedrigem strom
US9304528B2 (en) Reference voltage generator with op-amp buffer
US9921601B2 (en) Fractional bandgap circuit with low supply voltage and low current
JP6288627B2 (ja) 電圧発生回路を備える半導体装置
JP6185632B2 (ja) 電圧発生回路を備える半導体装置
Vail Design of a Bandgap Voltage Reference
Shaodong et al. A bandgap reference circuit with temperature compensation

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE APPLICATION HAS BEEN PUBLISHED

AK Designated contracting states

Kind code of ref document: A1

Designated state(s): AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR

AX Request for extension of the european patent

Extension state: BA ME

RIN1 Information on inventor provided before grant (corrected)

Inventor name: WANG, STEVE

Inventor name: SCHNAITTER, WILLIAM

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: REQUEST FOR EXAMINATION WAS MADE

17P Request for examination filed

Effective date: 20170831

RBV Designated contracting states (corrected)

Designated state(s): AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: EXAMINATION IS IN PROGRESS

17Q First examination report despatched

Effective date: 20180809

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: EXAMINATION IS IN PROGRESS

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: EXAMINATION IS IN PROGRESS

GRAP Despatch of communication of intention to grant a patent

Free format text: ORIGINAL CODE: EPIDOSNIGR1

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: GRANT OF PATENT IS INTENDED

INTG Intention to grant announced

Effective date: 20220513

GRAS Grant fee paid

Free format text: ORIGINAL CODE: EPIDOSNIGR3

GRAA (expected) grant

Free format text: ORIGINAL CODE: 0009210

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE PATENT HAS BEEN GRANTED

AK Designated contracting states

Kind code of ref document: B1

Designated state(s): AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR

REG Reference to a national code

Ref country code: GB

Ref legal event code: FG4D

REG Reference to a national code

Ref country code: CH

Ref legal event code: EP

Ref country code: AT

Ref legal event code: REF

Ref document number: 1529207

Country of ref document: AT

Kind code of ref document: T

Effective date: 20221115

REG Reference to a national code

Ref country code: DE

Ref legal event code: R096

Ref document number: 602016076003

Country of ref document: DE

REG Reference to a national code

Ref country code: IE

Ref legal event code: FG4D

REG Reference to a national code

Ref country code: LT

Ref legal event code: MG9D

REG Reference to a national code

Ref country code: NL

Ref legal event code: MP

Effective date: 20221102

REG Reference to a national code

Ref country code: AT

Ref legal event code: MK05

Ref document number: 1529207

Country of ref document: AT

Kind code of ref document: T

Effective date: 20221102

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: SE

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20221102

Ref country code: PT

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20230302

Ref country code: NO

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20230202

Ref country code: LT

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20221102

Ref country code: FI

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20221102

Ref country code: ES

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20221102

Ref country code: AT

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20221102

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: RS

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20221102

Ref country code: PL

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20221102

Ref country code: LV

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20221102

Ref country code: IS

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20230302

Ref country code: HR

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20221102

Ref country code: GR

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20230203

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: NL

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20221102

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: SM

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20221102

Ref country code: RO

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20221102

Ref country code: EE

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20221102

Ref country code: DK

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20221102

Ref country code: CZ

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20221102

REG Reference to a national code

Ref country code: DE

Ref legal event code: R097

Ref document number: 602016076003

Country of ref document: DE

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: SK

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20221102

Ref country code: AL

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20221102

PLBE No opposition filed within time limit

Free format text: ORIGINAL CODE: 0009261

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT

26N No opposition filed

Effective date: 20230803

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: SI

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20221102

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: MC

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20221102

REG Reference to a national code

Ref country code: CH

Ref legal event code: PL

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: MC

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20221102

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: LU

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20230824

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: LU

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20230824

Ref country code: CH

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20230831

REG Reference to a national code

Ref country code: BE

Ref legal event code: MM

Effective date: 20230831

REG Reference to a national code

Ref country code: IE

Ref legal event code: MM4A

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: IT

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20221102

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: IE

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20230824

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: IE

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20230824

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: BE

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20230831

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: DE

Payment date: 20240828

Year of fee payment: 9

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: GB

Payment date: 20240827

Year of fee payment: 9

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: FR

Payment date: 20240826

Year of fee payment: 9