Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
  • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
  • H01L27/144—Devices controlled by radiation
  • H01L27/146—Imager structures
  • H01L27/14601—Structural or functional details thereof
  • H01L27/14609—Pixel-elements with integrated switching, control, storage or amplification elements
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
  • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
  • H04N25/70—SSIS architectures; Circuits associated therewith
  • H04N25/71—Charge-coupled device [CCD] sensors; Charge-transfer registers specially adapted for CCD sensors
  • H04N25/75—Circuitry for providing, modifying or processing image signals from the pixel array
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
  • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
  • H01L27/144—Devices controlled by radiation
  • H01L27/146—Imager structures
  • H01L27/14601—Structural or functional details thereof
  • H01L27/14638—Structures specially adapted for transferring the charges across the imager perpendicular to the imaging plane
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
  • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
  • H01L27/144—Devices controlled by radiation
  • H01L27/146—Imager structures
  • H01L27/14601—Structural or functional details thereof
  • H01L27/14641—Electronic components shared by two or more pixel-elements, e.g. one amplifier shared by two pixel elements
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
  • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
  • H01L27/144—Devices controlled by radiation
  • H01L27/146—Imager structures
  • H01L27/14643—Photodiode arrays; MOS imagers
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
  • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
  • H04N25/40—Extracting pixel data from image sensors by controlling scanning circuits, e.g. by modifying the number of pixels sampled or to be sampled
  • H04N25/46—Extracting pixel data from image sensors by controlling scanning circuits, e.g. by modifying the number of pixels sampled or to be sampled by combining or binning pixels
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
  • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
  • H04N25/50—Control of the SSIS exposure
  • H04N25/57—Control of the dynamic range
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
  • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
  • H04N25/70—SSIS architectures; Circuits associated therewith
  • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
  • H04N25/77—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
  • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
  • H04N25/70—SSIS architectures; Circuits associated therewith
  • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
  • H04N25/77—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
  • H04N25/778—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising amplifiers shared between a plurality of pixels, i.e. at least one part of the amplifier must be on the sensor array itself

Definitions

• the invention relates to image sensors for acquiring electronic images with a very low level of light, in particular for a night vision in which the energy level captured by the pixels is of the same order as the noise, in particular the noise called shot ("noise shot” in English).
• the number of photons captured by a pixel must be at least 40 photons. If we want to capture an image at a frame rate of 60 frames per second, with F / 1 aperture optics and a signal-to-noise ratio of 10 dB, we need large area pixels, preferably around 100 square microns. ). But then, it is difficult not to saturate the sensor if the light increases significantly, for example in the presence of artificial light sources.
• An object of the invention is also to allow that at low light level the sensor can operate with a principle of correlated double sampling reducing the kTC noise of the pixels and this even in a global exposure mode (as opposed to an electronic rolling shutter mode of exposure, in English "electronic rolling shutter” or ERS).
• the invention proposes a matrix image sensor comprising at least two lines of pixels and comprising means for reading the pixels either individually or by grouping the charges coming from a group of four adjacent pixels belonging to two lines. adjacent and two adjacent columns, characterized in that it comprises, for the group of four pixels:
• a photodiode and a primary transfer gate making it possible to transfer the charges generated by the light in the photodiode to the outside of the photodiode;
• the first multiplication grid being adjacent to the transfer grids of the two pixels of a first column and the second grid being adjacent to the primary transfer grids of the two other pixels of the group belonging to the second one; column, and means for applying to the two multiplication grids an alternation of potentials in phase opposition;
• first load reading means comprising a first charge storage region and a first secondary transfer gate interposed between the first electron multiplication gate and the first charge storage region;
• second charge reading means comprising a second charge storage region and a second secondary transfer gate interposed between the second electron multiplication gate and the second charge storage region; and means for controlling the potentials applied to the transfer gates and the multiplication gates, to execute a simple reading mode and a group reading mode, in which,
• the charges of the photodiodes of the two pixels of the first line are transferred to the first multiplication grid and to the second multiplication grid, these charges are transferred from the multiplication gates to the first and second regions respectively. storing charges and read by the first and second reading means the charges present in these two regions, then repeat these operations for the two pixels of the second line,
• the charges of the two pixels of the first column in the first multiplication grid and the charges of the two pixels of the second column are transferred to the second multiplication grid and, subsequently, the charges present under the multiplication grids to one of the storage regions, and read the charges present in this region.
• the means for applying to the two multiplication grids an alternation of potential in phase opposition can optionally be used in the grouped read mode. They are not used in the simple reading mode.
• the two multiplication grids are preferably separated by an intermediate region maintained at a fixed potential during the multiplication of electrons.
• this intermediate region is constructed as a fixed surface potential photodiode (pinned photodiode): the intermediate region comprises an N-type diffusion covered by a P-type surface semiconductor region maintained at a fixed potential.
• the fixed potential is preferably that of a P-type active layer in which the photodiodes are formed.
• FIG. 1 represents a conventional electrical pixel diagram for MOS technology
• FIG. 2 represents a modified diagram incorporating an electron multiplication structure within the pixel
• FIG. 3 represents a schematic top view of a structure of four adjacent pixels according to the invention, the pixels being able to be read in single reading mode or in group reading mode;
• FIG. 5 represents another variant allowing a grouping of different groups of four pixels around a chosen pixel
• FIG. 6 represents a side sectional view of the structure of FIG. 3 along the line A-A of FIG. 3.
• FIG. 1 the electrical diagram of a conventional active pixel with five transistors of an image sensor in MOS technology and, with reference to FIG. 2, the diagram of FIG. a similar active pixel but further comprising means for multiplying electrons within the pixel.
• the pixel of FIG. 1 comprises a photodiode PH, a capacitive charge storage node ND (represented by a single point in FIG. 1, and realized in practice by an N-type diffusion in a P-type layer), a transistor T1 charge transfer between the cathode of the photodiode and the storage node, a resetting transistor T2 of the potential of the storage node, a photodiode potential resetting transistor T3, a reading transistor T4 mounted as a voltage follower , a line selection transistor T5.
• the transfer transistor T1 is controlled by a transfer signal TR.
• the transistor T2 has its drain connected to a reference potential VREF and it is controlled by a reset control signal RST for resetting the potential of the storage node.
• the transistor T3 is connected between the cathode of the photodiode and a reference potential which may be a supply potential Vdd. It is controlled by a reset signal GR for resetting the potential of the photodiode.
• the follower transistor T4 has its drain connected to a fixed potential which may be the supply Vdd, its source connected to the line selection transistor T5, and its gate connected to the storage node ND.
• the line selection transistor T5 has its gate connected to a line selection conductor which connects all the line selection transistors of the same line of pixels; this conductor is controlled by a line selection signal SEL specific to this line; the drain of the transistor T5 is connected to the source of the follower transistor and its source is connected to a column conductor COL common to all the pixels of the same column of pixels. This conductor transmits a voltage representing the amount of charge of the storage node of a pixel selected by the line conductor SEL.
• the column conductor is connected to a not shown reading circuit specific to the column of pixels at the foot of this column.
• the transfer transistor T1 mentioned in this diagram is in practice carried out by a simple isolated transfer gate separating the photodiode from the storage node, this gate being controlled by a transfer signal TR allowing the electrons to pass or, on the contrary, to forbid the passage.
• a simple isolated transfer gate separating the photodiode from the storage node, this gate being controlled by a transfer signal TR allowing the electrons to pass or, on the contrary, to forbid the passage.
• FIG. 2 represents a principle electrical diagram of the pixel in the case where the pixel comprises means for multiplying electrons inside the pixel.
• the photodiode and the charge storage node ND there is not between the photodiode and the charge storage node ND not a single transfer transistor (or a single gate) T1 but two transfer transistors (or gates) T1 and ⁇ and a multiplication structure of MS electrons between these two transistors or grids.
• the first transfer gate controlled by a control signal TR makes it possible to pass the photogenerated charges from the photodiode to the multiplication structure.
• the second transfer gate controlled by a control signal TR ', makes it possible to pass the electronic charges from the multiplication structure to the storage node ND.
• two adjacent pixels of one same column pour the charges collected by their respective photodiodes, through two respective primary transfer grids, to the same first multiplication grid; the charges collected by this multiplication grid can be multiplied by a multiplication structure which comprises at least this multiplication grid and a second multiplication grid; multiplication (or lack of multiplication) ends with intermediate storage under the second multiplication grid; the charges then contained under the second multiplication grid are read by a read structure (a secondary transfer gate for transferring the charges of the second multiplication gate to a charge storage node, a reset transistor of this node, a follower transistor for copying the potential of the storage node, and a pixel selection transistor for returning the potential of the follower transistor on a column conductor).
• a read structure a secondary transfer gate for transferring the charges of the second multiplication gate to a charge storage node, a reset transistor of this node, a follower transistor for copying the potential of the storage node, and a pixel selection transistor for returning the potential of the follower transistor on a
• This reading structure is common to the two pixels of the column and located between the two pixels. It is possible to choose to read the pixels in simple mode, thus successively, by controlling only a primary transfer gate, or on the contrary to read in grouped mode by simultaneously or successively controlling the transfer of the charges of the two photodiodes towards the first gate of multiplication. But to group the signals of four adjacent pixels in pairs in rows and columns, it is necessary to digitize the signals from the reading and then perform a numerical summation of the results for the pixels of two neighboring columns.
• the multiplication of electrons ends with an intermediate storage under the first multiplication grid if we want to read the charges of the first pixel, but it ends with a storage of charges under the second multiplication grid if we want to read the charges of the second pixel. It can end with a storage of charges under one or the other of the multiplication grids if one wants to read in grouped mode.
• each read structure comprises a secondary transfer gate, a charge storage node, a reset transistor, a voltage follower read transistor, and a line select transistor.
• grouped read mode the charges from adjacent pixels of the same column are grouped before being read and digitized, but to group the charges of the four pixels the grouping must be completed by a numerical summation of the result with the result of reading the signals of the two pixels of the neighboring column.
• the multiplication structure is common to four adjacent pixels and can receive charges of these four pixels.
• FIG. 3 is a top view of a scheme of organization of a group of four adjacent pixels in line and in column, according to the invention making it possible to read the pixels in single reading mode of each pixel or in grouped reading mode.
• four pixels for improved sensitivity, without the need for a numerical summation operation.
• Photodiodes, transfer grids, charge storage nodes, etc. are represented by simple rectangles to simplify the figure, but geometric shapes may be more complex to best fill the available space without increasing the pitch of pixels or reduce the optical aperture of the pixels.
• the electrical connections that appear in the diagram of Figure 2 are not shown.
• a multiplication structure common to the four adjacent pixels is placed in a free space between the four pixels. This structure makes it possible to perform a multiplication of electrons in the case where makes a grouped reading of the electrons accumulated by the four pixels.
• Each of the four pixels comprises a respective photodiode, PH1 1, PH12 for the two pixels of a first line, PH21, PH22 for the pixels of the second line.
• the pixels PH1 1 and PH21 belong to a first column; pixels PH12, PH22 belong to the second column.
• a primary transfer gate G1 1 (acting as transistor T1 of FIG. 2) is adjacent on one side to the photodiode PH1 1 and on the other side to a first multiplication gate GM1 of the multiplication structure associated with the group. four pixels.
• the primary transfer gate G1 1 makes it possible to transfer the charges of the first photodiode PH1 1 into the multiplication structure; these charges arrive by the first multiplication grid GM1.
• a second primary transfer gate G21 is adjacent on one side to the photodiode PH21 and on the other to the same first multiplication gate GM1. It allows the transfer of charges from photodiode PH21 to the first multiplication grid.
• two other primary transfer gates G12 and G22 are adjacent on one side to these two photodiodes, respectively PH21 and PH22, and on the other side to a second multiplication grid GM2 of the multiplication structure. They allow the charge transfer of these two other photodiodes to the second multiplication grid.
• the multiplication structure may comprise, in its preferred version, the two grids GM1 and GM2 and potential switching means for alternately passing one of the grids to a high potential while the other gate is at a low potential and reciprocally.
• the multiplication coefficient of electrons generated by this structure depends on the applied potentials and the number of alternations applied.
• the multiplication grids are separated by an intermediate semiconducting zone ZS maintained at a constant intermediate potential between the high and low potentials applied to the grids.
• this intermediate zone is crossed by the packets of electrons that pass alternately from the first multiplication grid to the second and vice versa.
• the first reading structure comprises a charge storage node ND1, a secondary transfer gate G'1 adjacent to both the first multiplication grid and the storage node ND1.
• This secondary transfer gate makes it possible to transfer to the storage node the quantity of electrons present under the first multiplication grid and having undergone or having not undergone a multiplication step.
• the first reading structure also comprises the following elements: a resetting transistor of the potential of the storage node ND1, not shown and constituted as the transistor T2 of a conventional active pixel; a read transistor constituted and connected as a voltage follower, such as the read transistor T4 of a conventional active pixel; a line selection transistor constituted and connected as the selection transistor T5 of a conventional active pixel. All these elements are part of the first reading structure, which is associated with the two pixels of the first column, that is to say the photodiodes PH1 1 and PH21.
• the second reading structure is associated with the two other pixels belonging to the second column, and therefore with photodiodes PH12 and PH22. It is identical to the first structure and works in the same way. It comprises a charge storage node ND2, a secondary transfer gate G'2 adjacent to the second multiplication gate GM2 and the storage node ND2. It also includes, as the first structure, the following elements not shown: reset transistor the second storage node, read follower transistor, and line select transistor.
• the line selection transistors of the two structures are simultaneously controlled by the same line conductor.
• the structure can operate in a single read mode or a clustered read mode.
• ERS mode electronic rolling shutter
• the duration of integration of the charges is identical for the different lines but offset in the time of a line to the next;
• the photodiodes integrate charges since the end of the previous integration cycle, the integration time beginning at the end of a charge transfer out of the photodiode and ending for each line at the end of a new charge transfer out of the photodiode; the transfer instants are shifted from one line to the next;
• the potential of the storage nodes of the selected line is reset, for example the nodes ND1, ND2 of the first line (photodiodes PH1 1 and PH12);
• the charges of the pixels of the first line are transferred through the primary transfer gates G1 1 and G12, under the multiplication gates GM1 and GM2. respectively ; for this purpose, the multiplication gates GM1 and GM2 are brought to a sufficiently high potential with respect to the intrinsic potential of the photodiode;
• the charges stored under the multiplication gate GM1 are transferred to the storage node ND1, through the secondary transfer gate G'1, and, simultaneously or successively, the charges stored under the multiplication gate GM2 towards the node of ND2 storage, through the secondary transfer gate G'2;
• the intrinsic potential of the ZS zone forms a potential barrier to prevent mixing of the charges present under grids GM1 and GM2;
• step f) repeating the operations a) to e) for the next line comprising photodiodes PH21 and PH22, by controlling the primary transfer gates G21 and G22 in step c) and using the same multiplication grids, the same grids secondary transfer G'1 and G'2 and the same storage nodes ND1 and ND2 as before;
• the multiplication grids have been used as simple intermediate storage grids between the photodiodes and the storage nodes.
• a grouped reading mode the charges of the four photodiodes PH1 1, PH12, PH21, PH22 are collected in the multiplication structure, multiplied, stored under one of the two multiplication gates, and read by reading structure associated with this multiplication grid, for example the reading structure comprising G'1 and ND1 if it is the first multiplication grid GM1.
• the four photodiodes integrate charges preferably in global exposure mode ("Global Shutter” in English) in which the start time of charge integration and the end time The integration of charges is the same for all photodiodes. ; this time is possibly adjustable if there is a transistor (such as T3, fig.2) for resetting the potential of each photodiode, controlled simultaneously for all the photodiodes;
• a multiplication of electrons is carried out by applying an alternation of potentials in opposite phase on the GM1 and GM2 multiplication gates; the multiplication or the absence of multiplication is ended by storing the multiplied charges under one of the two multiplication grids, for example the grid GM1; the phase opposition is non-overlapping in that the two grids must not simultaneously be at the low potential; it may be preferable for this to provide a slight recovery of potentials at the high level;
• both "Global Shutter” operation and a correlated double-sampling read in which the storage node is reset and read before a load transfer to this storage node can be performed. and a reading of this node.
• ERS spalling shutter
• FIG. 3 there is a line of multiplication structures and read structures for two lines of photodiodes.
• FIG. 4 it is possible to provide as many lines of multiplication structures as there are lines of photodiodes, but there is, as in FIG. 3, a single multiplication structure common to two pixels belonging to adjacent lines.
• FIGS. 3 and 4 it is possible to provide, as is shown for example in FIG. 5, that there is a multiplication structure on each side of the photodiode. So, in a line of multiplication structures, there are as many multiplication structures as there are columns of photodiodes. If this arrangement is combined with that of FIG. 4, there is obtained the arrangement of FIG. 5 in which there are four primary transfer gates for each photodiode making it possible to transfer charges respectively to one of four multiplication structures belonging to two adjacent lines and two adjacent columns.
• This embodiment allows, in group playback mode, to choose which adjacent pixels are grouped together. This embodiment is also less compact than that of FIG.
• FIG. 6 represents a technological section of the pixel, showing a way of practically producing the sensor according to the invention.
• FIG. 6 is a side section along the line AA of FIG. 3. This line AA passes through the photodiode PH1 1, the primary transfer gate G1 1, the multiplication gate GM1, the intermediate semiconductor zone ZS with fixed potential, the secondary transfer gate G'2, the storage node ND2.
• FIG. 6 also shows elements that do not appear in FIG. 3, namely a reset transistor of the storage node ND2 which is the transistor T2 of FIG. 2;
• the electrical connection between the storage node ND2 and two transistors T4 and T5 (follower transistor and line selection transistor connected to a column conductor COL) is recalled in accordance with the block diagram of FIG. 2.
• the reset transistor of the photodiode PH1 1 (transistor T3 in FIG. 2) is not shown; it comprises a control gate for discharging into a not shown drain the charges of the photodiode at the beginning of
• the pixel is formed in a substrate 10 which preferably comprises a P-type semiconductor active layer 12 with little doping or P- (the P-symbol is used to designate this weak doping) formed on the surface of a more doped layer (P + ).
• the pixel is isolated from neighboring pixels by an insulating barrier 13 which completely surrounds it. This barrier may be a superficial insulating trench over a P type box.
• the pixel comprises the photodiode region PH1 1 whose perimeter follows the contour of an N-type semiconductor region 14 implanted in a part of the depth of the active layer 12.
• This implanted region is surmounted by a surface region 16 of the P + type. which is maintained at a zero reference potential.
• the zero reference potential is that which is applied to the active layer P-.
• the charge storage node ND2 is an N-type diffusion in the active layer 12.
• a contact is formed on the storage node, to enable the potential of this region to be applied to the gate of a follower transistor (T4), in order to convert the amount of charge contained in the storage node into an electric voltage level.
• the gate of transistor T2 makes it possible to empty the charges from the storage node to a drain drain 20 which is an N + type region connected to a positive reset potential Vref.
• the multiplication structure MS comprises the isolated grids GM1 and GM2 separated by the semiconductor zone ZS.
• This zone is constituted as the photodiode (but not necessarily with the same doping), by a diffused region 34 of N type in the active layer 12, this region being covered by a surface region 36 of P + type.
• This region 36 is maintained at the zero reference potential, for example by touching, which is not seen in FIG. 6, a deep region of P + type joining the substrate, similar to the region 15 which touches the region 16 of the photodiode.
• the ZS region is at an internal potential known as "buit-in potential", which is fixed by maintaining the region 36 at the reference potential of the active layer 12, in this case that of the substrate 10.
• the primary transfer gate G1 1 is an insulated gate of the active layer 12; it is located between the photodiode PH1 1 and the multiplication gate GM1 and it allows the charge transfer from the photodiode to the gate GM1.
• the secondary transfer gate G'2 is an isolated gate located between the multiplication gate GM2 and the storage node ND2.
• the GM1 and GM2 multiplication grids are also grids isolated from the active layer. They are respectively separated from the gate G1 1 and the gate G'2 by a narrow interval (as narrow as possible in view of the technology used) in which the semiconductor may not be doped specifically, that is to say say can be constituted directly by the active layer 12.
• Potential switching means are provided for directly applying to the multiplication gates GM1 and GM2 high (greater than zero) or low (less than zero) potentials depending on the transfer or amplification phase concerned. These switching means are not shown because they are not located in the pixel.
• the potential present under this gate and under the primary transfer gate G1 1 is lowered by raising their potential.
• ZS zone with fixed potential is a potential barrier that prevents the passage of these charges to the grid GM2.
• a multiplicity (several tens, hundreds, or even thousands) of alternations of potentials in phase opposition with the gates GM1 and GM2 is applied, leaving the zone ZS at an intermediate potential between a high potential and a potential. bottom of this alternation.
• the charges stored under the gate GM1 are alternately switched from the gate GM1 to the gate GM2 and vice versa.
• the electric fields undergone by the electrons are strong enough to accelerate the electrons and then create electron-hole pairs, thus extra electrons at each alternation.
• the electron gain during an alternation is very small but is multiplied by the number of alternations.
• the potential of the primary and secondary transfer grids is a low potential during multiplication, creating a potential barrier preventing charges from exiting the multiplication structure and confining these charges alternately under the gate GM1 and under the gate GM2.
• the charges remain stored under the gate GM2 if we stop the alternation on a high potential of the gate GM2; they could remain stored under the grid GM1 otherwise. If the charges remain under the gate GM2, the secondary transfer gate G'2 is temporarily carried at a high potential allowing the discharging of the charges to the storage node ND2 for the purpose of reading these charges by the transistor T4 and the transistor T5 according to a classical reading process.

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