EP3038069B1 - Circuit d'attaque, dispositif maître de bus, système de détection d'incendie et système d'alarme antivol utilisant ledit circuit d'attaque - Google Patents

Circuit d'attaque, dispositif maître de bus, système de détection d'incendie et système d'alarme antivol utilisant ledit circuit d'attaque Download PDF

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Publication number
EP3038069B1
EP3038069B1 EP14199619.9A EP14199619A EP3038069B1 EP 3038069 B1 EP3038069 B1 EP 3038069B1 EP 14199619 A EP14199619 A EP 14199619A EP 3038069 B1 EP3038069 B1 EP 3038069B1
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EP
European Patent Office
Prior art keywords
bus
master device
driver circuit
bus master
switching elements
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
EP14199619.9A
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German (de)
English (en)
Other versions
EP3038069A1 (fr
Inventor
Robin Janßen
Heiner Politze
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Novar GmbH
Original Assignee
Novar GmbH
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Filing date
Publication date
Application filed by Novar GmbH filed Critical Novar GmbH
Priority to EP14199619.9A priority Critical patent/EP3038069B1/fr
Priority to ES14199619.9T priority patent/ES2632464T3/es
Priority to EP15202102.8A priority patent/EP3038070A1/fr
Publication of EP3038069A1 publication Critical patent/EP3038069A1/fr
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Publication of EP3038069B1 publication Critical patent/EP3038069B1/fr
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Classifications

    • G—PHYSICS
    • G08—SIGNALLING
    • G08B—SIGNALLING OR CALLING SYSTEMS; ORDER TELEGRAPHS; ALARM SYSTEMS
    • G08B25/00—Alarm systems in which the location of the alarm condition is signalled to a central station, e.g. fire or police telegraphic systems
    • G08B25/01—Alarm systems in which the location of the alarm condition is signalled to a central station, e.g. fire or police telegraphic systems characterised by the transmission medium
    • G08B25/04—Alarm systems in which the location of the alarm condition is signalled to a central station, e.g. fire or police telegraphic systems characterised by the transmission medium using a single signalling line, e.g. in a closed loop
    • G08B25/045—Alarm systems in which the location of the alarm condition is signalled to a central station, e.g. fire or police telegraphic systems characterised by the transmission medium using a single signalling line, e.g. in a closed loop with sensing devices and central station in a closed loop, e.g. McCullough loop
    • G—PHYSICS
    • G08—SIGNALLING
    • G08B—SIGNALLING OR CALLING SYSTEMS; ORDER TELEGRAPHS; ALARM SYSTEMS
    • G08B26/00—Alarm systems in which substations are interrogated in succession by a central station
    • G08B26/001—Alarm systems in which substations are interrogated in succession by a central station with individual interrogation of substations connected in parallel
    • G—PHYSICS
    • G08—SIGNALLING
    • G08B—SIGNALLING OR CALLING SYSTEMS; ORDER TELEGRAPHS; ALARM SYSTEMS
    • G08B29/00—Checking or monitoring of signalling or alarm systems; Prevention or correction of operating errors, e.g. preventing unauthorised operation
    • G08B29/02—Monitoring continuously signalling or alarm systems
    • G08B29/06—Monitoring of the line circuits, e.g. signalling of line faults
    • G—PHYSICS
    • G08—SIGNALLING
    • G08B—SIGNALLING OR CALLING SYSTEMS; ORDER TELEGRAPHS; ALARM SYSTEMS
    • G08B29/00—Checking or monitoring of signalling or alarm systems; Prevention or correction of operating errors, e.g. preventing unauthorised operation
    • G08B29/12—Checking intermittently signalling or alarm systems
    • G08B29/123—Checking intermittently signalling or alarm systems of line circuits

Definitions

  • the present invention is directed to a driver circuit, a bus master device, a fire detections system and a burglar alarming system using the driver circuit.
  • Alarm systems which have a control module or bus master device to which subscribers are connected by means of a two-wire line, said subscribers receiving from the control module, via the two-wire line operated as a field bus, both a power supply voltage and communication messages in the form of pulse trains impressed on the power supply voltage as voltage modulation.
  • the two-wire line to which the subscribers are connected in parallel may have a length of between 1000 and 2000 m, for example, and is frequently routed in a loop or ring shape, i.e. it starts and ends at the bus master device.
  • the two-wire line is also referred to simply as a field bus.
  • the subscribers may be sensors, e.g. fire or burglar alarms, and/or actuators, such as light-signal or sound-signal generators.
  • the power supply voltage for the subscribers may be in the range from 20 to 40 volts, for example, at the start of the two-wire line.
  • the communication between the bus master device and the subscribers is handled on the basis of a digital communication protocol.
  • the communication protocol defines time slots or time windows which are used to transmit pulses and pulse trains as data messages which represent addresses, commands and reports, in particular.
  • the pulses may comprise starting pulses with a length of 1 ms, for example, synchronization or separating pulses with a length of 0.5 ms, for example, and pulse trains representing bit-coded messages, with a single pulse length of between 100 and 200 ⁇ s, for example.
  • Each subscriber has a communication interface connected to the two-wire line, e.g. a UART interface for its microcontroller, which microcontroller detects and processes the pulses and pulse trains.
  • a communication interface connected to the two-wire line, e.g. a UART interface for its microcontroller, which microcontroller detects and processes the pulses and pulse trains.
  • Such a system is disclosed for example in DE 102011010922.6 A1 .
  • This document shows a bus master device having subscribers connected to it by a two-wire line.
  • the subscribers receive via the two-wire line both a power supply voltage and communication messages in the form of pulse trains impressed on the power supply voltage as voltage modulation.
  • the subscribers are provided with a transformer, which is provided to reduce power supply voltage of an internal value which is lower than the power supply voltage at least by the voltage swing of the pulses of the communication messages on the two-wire line.
  • a simple in-phase regulator is used as transformer.
  • bus master device are equipped with a class A, B or AB power amplifier with additional drive level/discharge circuitry, resulting in the following disadvantages.
  • the protocol/communication level cannot be generated universally (e.g. software defined), they are usually fixed and dependent on hardware. Rise and fall times and thus the transmission frequency are also hardware dependent.
  • the power dissipation of the output transistors is very high.
  • the efficiency is only about 50 % to 70 %.
  • EP 2 428 942 A1 discloses a circuit with a plurality of bus members wherein the connection and disconnection of the bus members are controlled from a central unit by switches.
  • the present invention has been made in order to overcome the above problems.
  • a driver circuit for a two wired loop bus comprising a first capacitance element connected between two input voltage supplies, a second capacitance element connected between two output voltage supplies, a first series connection of two switching elements connected between the two input voltage supplies, a second series connection of two switching elements connected between the two output voltage supplies, and an inductance, one end of which being connected between the two switching elements of the first series connection, and the other end thereof being connected between the two switching elements of the second series connection.
  • the driver circuit comprises four diodes each being connected so as to bridge one of the switching elements.
  • a bus master device for a two wired loop bus comprising a drive circuit as recited above, a current measuring element for measuring the current through the drive circuit, a controller for controlling the switching of the switching elements.
  • the bus master device can be configured so that the controller controls the switching of the switching elements with different pre-set timings, so as to provide different voltage levels on the two wired loop bus.
  • the bus master device is configured so as to switch the first switch of the first series connection and the second switch of the second serious connection synchronously.
  • a further aspect of the invention is directed to a fire detection system comprising a bus master device as recited above and a two wired loop bus comprising a plurality of fire detecting devices connected between the two wires of the bus.
  • the invention provides a burglar alarm system comprising a bus master device as recited above and a two wired loop bus comprising a plurality of burglar detecting devices and/or alarming devices connected between the two wires of the bus.
  • the alarm systems comprises a control center or bus master device 29 (possibly also subordinate control centers).
  • the bus master device 29 has both the start and the end of a two-wire line 11, 13 connected to it.
  • the two-wire line 11, 13 has numerous subscribers T01, T02, ... T10 electrically connected to it in parallel at intervals.
  • the two-wire line 11, 13 provides the power supply voltage for the subscribers T01, T02, ... T10 and is simultaneously used for bidirectional communication between the bus master device 29 and the subscribers T01, T02,... T10.
  • the two-wire line 11, 13 is therefore also referred to as a ring or loop bus for short.
  • the subscribers T01, T02, ... T10 can be e.g. fire detectors, burglar detectors, alarming devices and so on.
  • FIG 1 is a simplified figure showing the configuration of such an alarm system.
  • the loop bus can connect up to 123 subscribers T01, T02, ... T10 and supplies the corresponding operating voltage.
  • the loop bus is also configured to allow a digital communication between the subscribers T01, T02, ... T10 and the bus master device, e.g. by means of a pulse modulation technique.
  • the subscribers can have the function of detectors or may have the function of alarming devices, like flash lights or acoustic alarms.
  • FIG. 2 shows the bus master device 29 in more detail.
  • the bus master device 29 mainly comprises a controller 25 for controlling the operation of the bus master device 29 and of the loop bus, a memory 17 for storing operation data and control data for the bus master device 29, a driver circuit 19for providing the operation voltage and the control signals for the loop bus and switching units 21, 23 for the connection of the output of the driver circuit 19 with the input side of the two wires 11, 13 of the loop bus. Additionally the bus master device might comprise a current detector 15 for detecting the current output by the driver circuit 19.
  • the bus master device 29 can be connected on a primary side, opposite to the loop bus side, with a communication bus, which in turn might be connected to a central control controlling a plurality of bus master devices. Additionally the bus master device is connected to a power supply and comprises a power converter to provide an internal operation voltage, e.g. 42 V, which is supplied to the input side of the driver circuit 19.
  • the bus master device 29 can comprise further elements dedicated to different control operations and to the internal operation of the bus master device 29. Which will not be explained in further detail in this application.
  • Figure 3 shows in more detail the driver circuit 19 of Figure 2 .
  • the input side of the driver circuit 19 is connected between ground 3 and an internal voltage line 5 of the bus master device 29, which form input voltage supplies of the driver circuit.
  • the output side of the driver circuit is connected between ground 7 and an output voltage line 9 of the bus master device 29, which together form output voltage supplies.
  • the output voltage supplies 7, 9 are connected with respective wires of the loop bus 11, 13.
  • a first capacitance element C1 is connected between ground 3 and the internal voltage line 5.
  • the capacitor C1 is not specially limited to a particular capacitor type.
  • any type of switch like transistors, can be used.
  • the transistors are not limited to a particular transistor type. For example the use of FETs or of bi-polar n-channel or p-channel transistors is possible.
  • a respective diode D1, D2 connected parallel to a respective switch S1, S2.
  • the diodes are provided with the identical orientation and so as to block a current flowing from the internal voltage line 5 to ground 3, while allowing the flow of a current in the opposite direction.
  • a second capacitance element C2 is connected between ground 7 and the output voltage line 9.
  • the capacitor C2 is not specially limited to a particular capacitor type.
  • any type of switch like transistors, can be used.
  • the transistors are not limited to a particular transistor type. For example the use of FETs or of bi-polar n-channel or p-channel transistors is possible.
  • a respective diode D3, D4 connected parallel to a respective switch S3, S4.
  • the diodes are provided with the identical orientation and so as to block a current flowing from the output voltage line 9 to ground 7, while allowing the flow of a current in the opposite direction.
  • the switching elements S1 to S4 are operated under the control of the control unit 25 of the master bus device 29.
  • the switching elements S1 and S4 are operated at the same timing.
  • the switching elements S1 and S4 are in the open state, while the switching elements S2 and S3 are closed, the internal voltage of the master bus device 29 will charge the capacitor C1.
  • the output voltage line 9 will be supplied with the energy stored in the inductance L1 and the capacitor C2.
  • T is the sum of t on (S1, S4) and t off (S1, S4)
  • t on (S1, S4) is the time during which the switching elements S1 and S4 are closed while t on (S1, S4) / t off (S1, S4) is the time during which S1 and S4 are open.
  • the duty cycle dc will be T/t on (S1, S4).
  • the driver circuit operates as a buck-boost converter.
  • the two operating states of a buck-boost converter are: a) when the switching elements S1, S4 are turned on, the input voltage source supplies current to the inductance L1, and the capacitor C2 supplies current to the loop bus (output load). When the switching elements S1, S4 are opened, the inductance supplies current to the bus loop.
  • the bus master device can be used for a plurality of different loop buses having different bus protocols regarding the voltage levels, slew rates and so on, without a modification of the hardware, simply by controlling the switching of the switching elements S1 to S4.
  • a switched mode driver circuitry is used instead of using the former described type of amplifier, i.e. A, B or AB power amplifier with additional drive level/discharge circuitry.
  • the basic principle is well known and used for example in switching voltage regulators. But is has never been used as driver for two wired loop systems.
  • the invention uses a cascaded buck-boost topology with four switches/transistors, four diodes (in case of FETs the bulk diodes can be used) and one inductor.
  • the communication levels can be easily set.
  • the output voltage is only dependent on the input voltage, which can be assumed as nearly constant in this application, and the turn on/off time of the switching element pair S1, S4.
  • the solution offers software defined protocol/communication levels and the reduction of the transmission frequency/slew rate if necessary.
  • a further advantage is a highly reduced power dissipation (efficiency > 90 %), a good energy recovery and an integrated current measurement with the current detector 15.

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Security & Cryptography (AREA)
  • Business, Economics & Management (AREA)
  • Emergency Management (AREA)
  • Dc-Dc Converters (AREA)
  • Alarm Systems (AREA)
  • Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)

Claims (7)

  1. Circuit d'attaque pour un bus (88, 106) en boucle à deux fils comprenant :
    un premier élément (C1) de capacité monté entre deux sources (3, 5) de tension d'entrée ;
    un deuxième élément (C2) de capacité monté entre deux sources (7, 9) de tension de sortie ;
    un premier montage série de deux éléments (S1, S2) de commutation monté entre les deux sources (3, 5) de tension d'entrée ;
    un deuxième montage série de deux éléments (S3, S4) de commutation monté entre les deux sources (3, 5) de tension de sortie et
    une inductance (L1), dont une extrémité est montée entre les deux éléments (S1, S2) de commutation du premier montage série et dont l'autre extrémité est montée entre les deux éléments (S3, S4) de commutation du deuxième montage série.
  2. Circuit d'attaque suivant la revendication (1) comprenant, en outre :
    quatre diodes (D1 à D4), chacune montée de manière à shunter l'un des éléments (S1, S4) de commutation.
  3. Dispositif maître de bus pour un bus en boucle à deux fils, le dispositif maître de bus comprenant :
    un circuit (19) d'attaque suivant la revendication 1 ou 2 ;
    un élément (15) de mesure du courant pour mesurer le courant passant dans le circuit d'attaque ;
    une unité (13) de commande pour commander la commutation des éléments (S1, S4) de commutation.
  4. Dispositif maître de bus suivant la revendication 3, dans lequel
    l'unité (13) de commande est configurée de manière à commander la commutation des éléments (S1, S4) de commutation à des cadences différentes fixées à l'avance, de manière à donner des niveaux de tension différents sur le bus en boucle à deux fils.
  5. Dispositif maître de bus suivant la revendication 4, dans lequel
    l'unité (13) de commande est configurée de manière à commuter le premier interrupteur (S1) du premier montage série et le deuxième interrupteur (S4) du deuxième montage série en synchronisme.
  6. Système de détection d'incendie comprenant :
    un dispositif (29) de maître de bus suivant l'une quelconque des revendications 3 à 5 et
    un bus (11, 13) en boucle à deux fils comprenant une pluralité de dispositifs (T01 à T10) de détection d'incendie montés entre les deux fils du bus.
  7. Système d'alerte antivol comprenant :
    un dispositif maître de bus suivant l'une quelconque des revendications 3 à 5 et
    un bus (11, 13) en boucle à deux fils comprenant une pluralité de dispositifs (15) antivol et/ou de dispositifs d'alerte montés entre les deux fils du bus.
EP14199619.9A 2014-12-22 2014-12-22 Circuit d'attaque, dispositif maître de bus, système de détection d'incendie et système d'alarme antivol utilisant ledit circuit d'attaque Active EP3038069B1 (fr)

Priority Applications (3)

Application Number Priority Date Filing Date Title
EP14199619.9A EP3038069B1 (fr) 2014-12-22 2014-12-22 Circuit d'attaque, dispositif maître de bus, système de détection d'incendie et système d'alarme antivol utilisant ledit circuit d'attaque
ES14199619.9T ES2632464T3 (es) 2014-12-22 2014-12-22 Circuito de excitación, dispositivo maestro de bus, sistema de detecciones de incendios y sistema de alarma antirrobo que usan el circuito de excitación
EP15202102.8A EP3038070A1 (fr) 2014-12-22 2015-12-22 Circuit d'attaque, dispositif maître de bus, système de détection d'incendie et système d'alarme antivol utilisant ledit circuit d'attaque

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP14199619.9A EP3038069B1 (fr) 2014-12-22 2014-12-22 Circuit d'attaque, dispositif maître de bus, système de détection d'incendie et système d'alarme antivol utilisant ledit circuit d'attaque

Publications (2)

Publication Number Publication Date
EP3038069A1 EP3038069A1 (fr) 2016-06-29
EP3038069B1 true EP3038069B1 (fr) 2017-04-12

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EP14199619.9A Active EP3038069B1 (fr) 2014-12-22 2014-12-22 Circuit d'attaque, dispositif maître de bus, système de détection d'incendie et système d'alarme antivol utilisant ledit circuit d'attaque
EP15202102.8A Pending EP3038070A1 (fr) 2014-12-22 2015-12-22 Circuit d'attaque, dispositif maître de bus, système de détection d'incendie et système d'alarme antivol utilisant ledit circuit d'attaque

Family Applications After (1)

Application Number Title Priority Date Filing Date
EP15202102.8A Pending EP3038070A1 (fr) 2014-12-22 2015-12-22 Circuit d'attaque, dispositif maître de bus, système de détection d'incendie et système d'alarme antivol utilisant ledit circuit d'attaque

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EP (2) EP3038069B1 (fr)
ES (1) ES2632464T3 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11367339B2 (en) 2018-06-21 2022-06-21 Autronica Fire & Security As System and method for startup of a detector loop

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106130857A (zh) * 2016-08-26 2016-11-16 深圳市嘉泰智能股份有限公司 两线供电及通信系统及方法

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5406254A (en) * 1992-11-25 1995-04-11 Borg-Warner Security Corporation Alarm system with remote module and associated alarm
DE102009004974A1 (de) * 2009-01-14 2010-07-15 Ic - Haus Gmbh Busteilnehmer mit geregelter Sendestromquelle
DE102010044892A1 (de) * 2010-09-09 2012-03-15 Novar Gmbh Gefahrenmeldeanlage mit zwei Datenübertragungsgeschwindigkeiten
DE102011010922B4 (de) 2011-02-10 2012-08-30 Novar Gmbh Gefahrenmeldeanlage

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
None *

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11367339B2 (en) 2018-06-21 2022-06-21 Autronica Fire & Security As System and method for startup of a detector loop

Also Published As

Publication number Publication date
EP3038069A1 (fr) 2016-06-29
ES2632464T3 (es) 2017-09-13
EP3038070A1 (fr) 2016-06-29

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