EP3037792B1 - Method for manufacturing an optical interferometer - Google Patents

Method for manufacturing an optical interferometer Download PDF

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Publication number
EP3037792B1
EP3037792B1 EP14837699.9A EP14837699A EP3037792B1 EP 3037792 B1 EP3037792 B1 EP 3037792B1 EP 14837699 A EP14837699 A EP 14837699A EP 3037792 B1 EP3037792 B1 EP 3037792B1
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EP
European Patent Office
Prior art keywords
semiconductor
wall portion
mask
insulating layer
main surface
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EP14837699.9A
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German (de)
English (en)
French (fr)
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EP3037792A4 (en
EP3037792A1 (en
Inventor
Tomofumi Suzuki
Yoshihisa Warashina
Kohei KASAMORI
Tatsuya Sugimoto
Jo Ito
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Hamamatsu Photonics KK
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Hamamatsu Photonics KK
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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01B—MEASURING LENGTH, THICKNESS OR SIMILAR LINEAR DIMENSIONS; MEASURING ANGLES; MEASURING AREAS; MEASURING IRREGULARITIES OF SURFACES OR CONTOURS
    • G01B9/00—Measuring instruments characterised by the use of optical techniques
    • G01B9/02—Interferometers
    • G01B9/02049—Interferometers characterised by particular mechanical design details
    • G01B9/02051—Integrated design, e.g. on-chip or monolithic
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01J—MEASUREMENT OF INTENSITY, VELOCITY, SPECTRAL CONTENT, POLARISATION, PHASE OR PULSE CHARACTERISTICS OF INFRARED, VISIBLE OR ULTRAVIOLET LIGHT; COLORIMETRY; RADIATION PYROMETRY
    • G01J3/00—Spectrometry; Spectrophotometry; Monochromators; Measuring colours
    • G01J3/02—Details
    • G01J3/0256—Compact construction
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01J—MEASUREMENT OF INTENSITY, VELOCITY, SPECTRAL CONTENT, POLARISATION, PHASE OR PULSE CHARACTERISTICS OF INFRARED, VISIBLE OR ULTRAVIOLET LIGHT; COLORIMETRY; RADIATION PYROMETRY
    • G01J3/00—Spectrometry; Spectrophotometry; Monochromators; Measuring colours
    • G01J3/28—Investigating the spectrum
    • G01J3/45—Interferometric spectrometry
    • G01J3/453—Interferometric spectrometry by correlation of the amplitudes
    • G01J3/4532—Devices of compact or symmetric construction
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01J—MEASUREMENT OF INTENSITY, VELOCITY, SPECTRAL CONTENT, POLARISATION, PHASE OR PULSE CHARACTERISTICS OF INFRARED, VISIBLE OR ULTRAVIOLET LIGHT; COLORIMETRY; RADIATION PYROMETRY
    • G01J3/00—Spectrometry; Spectrophotometry; Monochromators; Measuring colours
    • G01J3/28—Investigating the spectrum
    • G01J3/45—Interferometric spectrometry
    • G01J3/453—Interferometric spectrometry by correlation of the amplitudes
    • G01J3/4535—Devices with moving mirror

Definitions

  • the present invention relates to a method of manufacturing an optical interferometer using MEMS technology.
  • Patent Literature 1 a micro-machined interferometer is disclosed.
  • This interferometer includes optical components such as a beam splitter, an electrostatic actuator, a movable mirror movable by the electrostatic actuator, and a fixed mirror.
  • a method of manufacturing such an interferometer is disclosed in Patent Literature 1.
  • a portion serving as each optical component is formed on an insulating layer by etching a silicon layer of an SOI wafer.
  • metal coating is selectively performed on a portion formed of a movable mirror or a fixed mirror through sputtering using a shadow mask.
  • YU K ET AL "Micromachined Fourier transform spectrometer on silicon optical bench platform”
  • SENSORS AND ACTUATORS A PHYSICAL, vol. 130-131, pages 523-530
  • a miniaturized Fourier transform spectrometer implemented on a silicon optical bench platform.
  • Both optical and opto-mechanical components of a Michelson interferometer, including a silicon beam splitter, micromirrors, MEMS actuators, and fiber U-grooves, are simultaneously fabricated by micromachining of the device layer of a silicon-on-insulator wafer.
  • Patent Literature 1 Japanese Unexamined Patent Publication No. 2008-102132
  • an objective of an aspect of the present invention is to provide a method of manufacturing an optical interferometer capable of suppressing the degradation of optical use efficiency due to an extension of an optical path length.
  • the first wall portion is arranged between the first semiconductor portion for the beam splitter and the second semiconductor portion for the movable mirror.
  • the metal film is formed on the second side surface of the second semiconductor portion using the shadow mask.
  • the metal film is formed, the first side surface is masked using the first wall portion while the second side surface is exposed from the first opening portion of the shadow mask.
  • the first and second semiconductor portions may be formed by etching a semiconductor layer formed on the main surface and the first insulating layer in the first step and the second step may be performed by forming the first wall portion on the main surface and the first insulating layer by the etching.
  • the first and second semiconductor portions and the first wall portion can be collectively formed.
  • the first wall portion can also be removed when the first insulating layer is etched to form a hollow structure such as a movable mirror.
  • the first side surface may be masked by the mask portion and the first wall portion by joining a back surface of the mask portion to a top portion of the first wall portion in the third step. In this case, the first side surface is reliably masked.
  • the second wall portion extending along the back surface may be formed on the back surface of the mask portion, and a bottom portion of the second wall portion may be joined to the top portion of the first wall portion in the third step.
  • the first wall portion formed on the main surface of the support substrate and the second wall portion formed on the shadow mask can be used in the mask of the first side surface.
  • a second insulating layer may be formed on the back surface of the mask portion, and the back surface of the mask portion may be joined to the top portion of the first wall portion through the second insulating layer in the third step.
  • the shadow mask can be easily removed by etching the second insulating layer.
  • the first insulating layer and the second insulating layer can be etched by the same etching agent, it is possible to simultaneously perform the formation of a hollow structure such as the movable mirror, the removal of the first wall portion, and the removal of the shadow mask through one etching process on the first and second insulating layers.
  • a third semiconductor portion for a deflection mirror may be formed on the main surface and the first insulating layer in the first step, a third wall portion extending along the main surface may be disposed between a third side surface of the third semiconductor portion at the side of the first semiconductor portion and the first semiconductor potion may be arranged in the second step, a mirror surface may be formed in the third semiconductor portion by forming a second metal film on the third side surface using the shadow mask in the third step, the shadow mask may have a second opening portion formed in the mask portion, and a side surface of the first semiconductor portion at the side of the third semiconductor potion may be masked by the mask portion and the third wall portion and the second metal film may be formed in a state in which the third side surface is exposed from the second opening portion in the third step.
  • the beam splitter and the deflection mirror can be formed to be
  • an optical interferometer capable of suppressing the degradation of optical use efficiency due to an extension of an optical path length.
  • Fig. 1 is a schematic plan view of an optical interferometer to be manufactured by a method according to the present embodiment.
  • Fig. 2 is a schematic end view taken along line II-II of Fig. 1 .
  • An optical interferometer 1 illustrated in Figs. 1 and 2 is an optical interferometer using MEMS technology, and, for example, is configured as a Michelson interferometer.
  • the optical interferometer 1 includes a support substrate 10, a beam splitter 12, an actuator 13, a movable mirror 14, a fixed mirror 15, and deflection mirrors 16 and 17.
  • the support substrate 10 has a main surface 10s.
  • the support substrate 10 is formed of silicon.
  • the support substrate 10 is a silicon substrate in an SOI substrate.
  • An insulating layer (first insulating layer) 21 is formed in a region of a part of the main surface 10s.
  • the insulating layer 21, for example, is formed by etching an insulating layer (sacrificial layer) of the SOI substrate.
  • the insulating layer 21 is formed of, for example, a silicon oxide (for example, SiO 2 ) or a silicon nitride (for example, SiN).
  • the beam splitter 12, the actuator 13, the movable mirror 14, the fixed mirror 15, and the deflection mirrors 16 and 17, for example, are formed on the main surface 10s of the support substrate 10 through etching or the like of the silicon layer of the SOI substrate.
  • the beam splitter 12, the fixed mirror 15, and the deflection mirrors 16 and 17 are formed on the main surface 10s and the insulating layer 21 (that is, the insulating layer 21 is interposed between them and the main surface 10s).
  • a part of the actuator 13 and the movable mirror 14 float over the main surface 10s (that is, the insulating layer 21 is not interposed between them and the main surface 10s) and have a hollow structure.
  • the beam splitter 12 is a light transmission component which transmits light of a predetermined wavelength.
  • the beam splitter 12 has a side surface 12a and a side surface (first side surface) 12b opposite to the side surface 12a.
  • the side surfaces 12a and 12b extend in a direction along the main surface 10s and a direction orthogonal to the main surface 10s.
  • the side surface 12a is a surface at the side of the deflection mirror 16 (in particular, a side surface 16a to be described below) and the side surface 12b is a surface at the side of the movable mirror 14 (in particular, a side surface 14a to be described below).
  • the side surface 12a is a half-mirror surface (semi-transmission/reflection surface) which reflects some of arriving light and transmits the remainder.
  • a silicon oxide film, a silicon nitride film, etc. can be formed on the side surface 12a.
  • the side surface 12b is a light transmission surface.
  • an anti-reflection film (AR film) including a silicon nitride film can be formed on the side surface 12b.
  • the actuator 13 includes a comb-tooth portion formed in a comb-tooth shape, a support portion for supporting the comb-tooth portion on the main surface 10s, and another comb-tooth portion formed in a comb-tooth shape to be arranged between comb teeth of the comb-tooth portion (the illustration of each portion is omitted).
  • No insulating layer is interposed between the comb-tooth portion and the main surface 10s, and the comb-tooth portion is supported by the support portion in a state in which the comb-tooth portion floats over the main surface 10s.
  • the actuator 13 is configured to change (control) a space between comb teeth in a direction along the main surface 10s by causing an electrostatic force between the comb-tooth portion and the other comb-tooth portion.
  • an electrode (not illustrated) for applying a voltage is formed in the actuator 13.
  • the movable mirror 14 has a side surface (second side surface) 14a.
  • the side surface 14a is a surface at the side of a side surface 12b of the beam splitter 12.
  • the side surface 14a extends in a direction along the main surface 10s and a direction orthogonal to the main surface 10s.
  • a metal film (first metal film) 31 is formed on the side surface 14a.
  • the side surface 14a is configured as a mirror surface (reflection surface) which totally reflects arriving light.
  • the movable mirror 14 is connected to one end portion of the actuator 13.
  • no insulating layer 21 is interposed between the movable mirror 14 and the main surface 10s and the movable mirror 14 floats over the main surface 10s. Accordingly, the movable mirror 14 is movable by the actuator 13 in the direction along the main surface 10s.
  • the fixed mirror 15 has a pair of side surfaces 15a and 15b opposite to each other.
  • the side surfaces 15a and 15b extend in the direction along the main surface 10s and extend in the direction approximately orthogonal to the main surface 10s.
  • the side surface 15a is a surface at the side of the side surface 12a of the beam splitter 12 and the side surface 15b is a surface opposite to the side surface 15a.
  • a metal film 32 is formed on the side surface 15b. Thereby, the side surface 15b is configured as a mirror surface which totally reflects arriving light.
  • the deflection mirror 16 has a side surface 16a.
  • the side surface 16a is a surface at the side of the side surface 12a of the beam splitter 12.
  • the side surface 16a extends in the direction along the main surface 10s and a direction tilted 45 degrees with respect to a direction orthogonal to the main surface 10s.
  • a metal film (second metal film) 33 is formed on the side surface 16a.
  • the side surface 16a is configured as a mirror surface which totally reflects arriving light.
  • the deflection mirror 16, for example, is an incident mirror, and is a 90-degree deflection mirror which deflects light incident from the direction orthogonal to the main surface 10s in the direction along the main surface 10s.
  • the side surface 12a of the beam splitter 12 is tilted with respect to an optical path of light deflected by the deflection mirror 16 when viewed from the direction orthogonal to the main surface 10s.
  • the deflection mirror 17 has a side surface 17a.
  • the side surface 17a is a surface of the beam splitter 12 at the side of the side surface 12b.
  • the side surface 17a extends in the direction along the main surface 10s and the direction tilted 45 degrees with respect to the direction orthogonal to the main surface 10s.
  • a metal film (second metal film) 34 is formed on the side surface 17a.
  • the side surface 17a is configured as a mirror surface which totally reflects arriving light.
  • the deflection mirror 17, for example, is an emission mirror, and is a 90-degree deflection mirror which deflects light from a direction along the main surface 10s in the direction orthogonal to the main surface 10s.
  • light L1 incident on the optical interferometer 1 is deflected 90 degrees by the side surface 16a of the deflection mirror 16 and incident on the side surface 12a of the beam splitter 12.
  • Light L2 which is some of the light L1 incident on the side surface 12a is reflected by the side surface 12a, incident on the fixed mirror 15 from the side surface 15a, and reflected by the side surface 15b.
  • Light L3 reflected by the side surface 15b is incident on the side surface 12a of the beam splitter 12 again.
  • light L4 which is the remainder of the light L1 incident on the side surface 12a, is transmitted through the side surface 12a, emitted from the side surface 12b, and reflected by the side surface 14a of the movable mirror 14.
  • Light L5 reflected by the side surface 14a is incident on the side surface 12b again and reaches the side surface 12a.
  • the light L5 reflected by the side surface 14a and reaching the side surface 12a is combined with the light L3 which is reflected by the fixed mirror 15 and is incident on the side surface 12a, and emitted as interference light L6 from the side surface 12b.
  • the interference light L6 emitted from the side surface 12b is deflected 90 degrees in the direction orthogonal to the main surface 10s by the side surface 17a of the deflection mirror 17 and output outside the optical interferometer 1.
  • Figs. 3 to 5 are schematic end views illustrating main steps of the method of manufacturing the optical interferometer according to the present embodiment.
  • a substrate formed by layering a semiconductor layer through an insulating layer (sacrificial layer: first insulating layer) on the main surface 10s of the support substrate 10 is first provided.
  • This substrate for example, is an SOI substrate.
  • the insulating layer is formed of, for example, a silicon oxide (for example, SiO 2 ) or a silicon nitride (for example, SiN).
  • the semiconductor layer is formed of, for example, silicon.
  • a semiconductor portion (first semiconductor portion) 52 for the beam splitter 12, a semiconductor portion 53 for the actuator 13, and a semiconductor portion (second semiconductor portion) 54 for the movable mirror 14 are formed as illustrated in Fig. 3(a) by etching the semiconductor layer formed on the main surface 10s and the insulating layer (step S101: first and second steps).
  • the insulating layer 21 is formed by removing a part of the insulating layer.
  • a semiconductor layer S including the semiconductor portions 52 to 54 is formed on the main surface 10s and the insulating layer 21.
  • the semiconductor portion 52 includes the side surfaces 12a and 12b and the semiconductor portion 54 includes the side surface 14a.
  • step S101 an insulating layer between a region for a movable portion including a comb-tooth portion of the semiconductor portion 53 and the main surface 10s is removed by removing a part of the insulating layer and forming the insulating layer 21, and these float over the main surface 10s (that is, a hollow structure is formed).
  • the insulating layer (insulating layer 21) remains between the semiconductor portions 52 and 54 and the main surface 10s.
  • the semiconductor portions 52 to 54 are formed by etching the above-described semiconductor layer and a wall portion (first wall portion) 61 is formed on the main surface 10s and the insulating layer 21 by the etching.
  • the wall portion 61 is formed between the side surface 12b of the semiconductor portion 52 at the side of the semiconductor portion 54 and the side surface 14a of the semiconductor portion 54 at the side of the semiconductor portion 52 so that the wall portion 61 extends in the direction along the main surface 10s and the direction orthogonal to the main surface 10s. That is, in this step S101, the wall portion 61 extending along the main surface 10s is disposed between the side surface 12b of the semiconductor portion 52 and the side surface 14a of the semiconductor portion 54.
  • the wall portion 61 is formed at the side of the side surface 12b rather than at a center position between the side surface 12b of the semiconductor portion 52 and the side surface 14a of the semiconductor portion 54. That is, the wall portion 61 is arranged at a position closer to the semiconductor portion 52 than the semiconductor portion 54. In addition, because the wall portion 61 is formed along with the semiconductor portions 52 to 54 by etching the semiconductor layer, the height of the wall portion 61 from the main surface 10s is substantially the same as the height of the semiconductor portions 52 to 54 from the main surface 10s.
  • this wall portion 61 is used to separately protect a portion such as the side surface 12b of the semiconductor portion 52 (non-metallized portion) in which a metal film is not formed from a portion such as the side surface 14a of the semiconductor portion 54 (metallized portion) in which a metal film is formed (that is, used to mask a non-metallized portion).
  • the semiconductor portions 52 to 54 and the wall portion 61 can be collectively formed by forming a pattern for the wall portion 61 in addition to a pattern for the semiconductor portions 52 to 54 to a mask to be used at the time of etching the semiconductor layer.
  • the semiconductor layer S includes the wall portion 61.
  • a shadow mask 70 is provided (step S102).
  • the shadow mask 70 for example, a silicon wafer or a glass wafer can be used.
  • the shadow mask 70 has a mask portion 71 and an opening portion (first opening portion) 72 formed in the mask portion 71.
  • the mask portion 71 includes a first region 75 which covers the side surface 12b of the semiconductor portion 52 and the wall portion 61 and a second region 76 which defines the opening portion 72 with the first region 75 when viewed from the direction orthogonal to the main surface 10s.
  • the mask portion 71 includes a front surface 71a and a back surface 71b opposite to the front surface 71a.
  • the back surface 71b is a surface located at the side of the main surface 10s and the semiconductor layer S rather than the front surface 71a (that is, a surface opposite to the main surface 10s) when the shadow mask 70 is arranged on the main surface 10s and the semiconductor layer S in a subsequent step.
  • a wall portion (second wall portion) 78 extending along the back surface 71b is formed on the back surface 71b.
  • the wall portion 78 is formed for the back surface 71b in the first region 75.
  • an insulating layer (sacrificial layer: second insulating layer) 22 is formed on an external surface including a front surface 71a and a back surface 71b of the mask portion 71 (that is, the insulating layer 22 is also formed on the external surface of the wall portion 78).
  • the insulating layer 22 is formed of, for example, a silicon oxide (for example, SiO 2 ) or a silicon nitride (for example, SiN).
  • the insulating layer 22 is formed of a silicon oxide
  • the insulating layer 22 for example, is formed by thermal oxidation.
  • the shadow mask 70 is arranged on the main surface 10s and the semiconductor layer S and joined to the semiconductor layer S (step S103: third step).
  • the shadow mask 70 is arranged on the main surface 10s and the semiconductor layer S so that the side surface 12b of the semiconductor portion 52 is masked by (here, covered with) the first region 75 of the mask portion 71 and the wall portion 61 and the side surface 14a of the semiconductor portion 54 is exposed from the opening portion 72 (that is, so that the side surface 14a of the semiconductor portion 54 is included in the opening portion 72 when viewed from the direction orthogonal to the main surface 10s).
  • the shadow mask 70 is joined to the semiconductor layer S by joining a bottom portion (bottom surface) 78s of the wall portion 78 to a top portion (top surface) 61c of the wall portion 61. Because the shadow mask 70 is joined to the semiconductor layer S in a wall portion 78 protruding from the back surface 71b as described above, a major portion of the back surface 71b is separated from the semiconductor layer S.
  • the bottom portion 78s of the wall portion 78 is joined to the top portion 61c of the wall portion 61, so that a continuous wall portion 65 extending from the main surface 10s to the back surface 71b of the mask portion 71 (more specifically, a flat portion other than the wall portion 78 on the back surface 71b) is configured by the wall portion 61 and the wall portion 78.
  • the side surface 12b of the semiconductor portion 52 is masked using the wall portion 65. That is, here, a wall portion for masking the side surface 12b is provided on both the main surface 10s of the support substrate 10 and the shadow mask 70.
  • the insulating layer 22 is formed on the back surface 71b of the mask portion 71. Therefore, in this step S103, the back surface 71b of the mask portion 71 is joined to the top portion 61c of the wall portion 61 throught the insulating layer 22. In this joining, for example, surface activation joining can be used.
  • a metallization step is performed. That is, a mirror surface is formed on the semiconductor portion 54 by forming the metal film 31 on the side surface 14a of the semiconductor portion 54 using the shadow mask 70 (step S104: third step). More specifically, the side surface 12b of the semiconductor portion 52 is masked by the first region 75 of the mask portion 71 and the wall portion 61 (more specifically, the wall portion 65 constituted of the wall portions 61 and 78) and the metal film 31 is formed on the side surface 14a in a state in which the side surface 14a is exposed from the opening portion 72 (metallization is performed). In the formation of the metal film 31, for example, sputtering can be used. In this case, a metal target is arranged on the surface 71a of the mask portion 71 and metal particles M are scattered toward the mask portion 71.
  • the metal particles M are incident from the opening portion 72 and a metal material is deposited on the side surface 14a which is a metallized portion, so that the metal film 31 is formed.
  • the metal material is also deposited on the side surface of the wall portion 61 at the side of the semiconductor portion 54 according to an incident direction of the metal particles M, so that the metal film 35 is formed.
  • the metal material is also partially deposited on the main surface 10s of the support substrate 10 and the metal film 36 is formed.
  • the side surface 12b of the semiconductor portion 52 which is a non-metallized portion is masked by the first region 75 of the mask portion 71 and the wall portion 61 (wall portion 65), the metal particles M do not reach it and the metal film is not formed.
  • the wall portion 61 (wall portion 65) functions as a shielding body of the metal particles M from the metal target.
  • an opening located on a non-movable portion of the actuator 13 is further provided in the mask portion 71 of the shadow mask 70. Accordingly, in step S103, simultaneously with the formation of the metal films 31 and 36, the metal material is also deposited on the non-movable portion of the actuator 13 and the metal film (not illustrated) is formed. As described above, this metal film is used as an electrode when a voltage is applied to the actuator 13 for generating an electrostatic force between comb teeth.
  • step S105 fourth step.
  • the wall portion 61 is removed from the support substrate 10 and the shadow mask 70 is removed from the semiconductor layer S by etching the insulating layers 21 and 22 (sacrificial layer etching) (step S105: fourth step).
  • the insulating layer 21 and the insulating layer 22 include a silicon oxide, it is possible to remove the insulating layer 21 between the wall portion 61 and the main surface 10s and remove the insulating layer 22 between the wall portion 61 and the wall portion 78 through etching using hydrofluoric acid and simultaneously remove the wall portion 61 and the shadow mask 70.
  • this step it is possible to remove the insulating layer 21 between the semiconductor portion 54 and the main surface 10s by etching the insulating layer 21 and form the movable mirror 14 in a state in which the semiconductor portion 54 floats over the main surface 10s. That is, in this step S105, the formation of the hollow structure (movable mirror 14) in the optical interferometer 1 and the removal of the wall portion 61 and the shadow mask 70 are simultaneously performed.
  • the wall portion 61 peeled from the main surface 10s of the support substrate 10 remains within the optical interferometer 1, this may cause damage of an optical component, a movable component, or the like of the optical interferometer 1.
  • the wall portion 61 is removed in this step S105, the main surface 10s is directed to the bottom in a vertical direction and the wall portion 61 peeled from the main surface 10s (and the shadow mask 70 peeled from the semiconductor layer S) is considered to fall in a predetermined saucer A as illustrated in Fig. 5 .
  • the MEMS technology is based on high-precision alignment technology and high-precision structure formation technology using semiconductor photolithography technology and is useful as technology for manufacturing an optical interferometer, a diffraction grating, or the like configured to process light as waves.
  • MEMS processing using the silicon substrate has many advantages. As an example of the advantages, the low cost of a material itself, good mechanical characteristics due to an excellent elastic material, the manufacturing of a highly reliable sensor or actuator, and the development of technology for forming a trench of a high aspect ratio to be substituted for tilted surface formation using the crystal anisotropy of a material or a Bosch process, etc. are included.
  • the MEMS technology may be used to manufacture an optical interferometer or the like for an acceleration sensor, a pressure sensor, a pixel mirror (DMD or the like) of a projector, and a Fourier transform infrared (FTIR) spectrometer.
  • FTIR Fourier transform infrared
  • applications for the optical interferometer of the MEMS technology are wide and the optical interferometer of the MEMS technology is applied to optical coherent tomography (OCT), film thickness measurement, surface roughness measurement, etc. as well as FTIR spectroscopy and therefore is considered to implement the reduction of the size and cost of the above-described measuring devices.
  • the optical interferometer using the MEMS technology when the optical interferometer 100 is manufactured, an optical component such as a beam splitter 101 or a movable mirror 102 and an actuator (drive portion) 103 for generating an optical path difference may be formed on the same substrate using photolithography and Si etching.
  • an optical component such as a beam splitter 101 or a movable mirror 102 and an actuator (drive portion) 103 for generating an optical path difference may be formed on the same substrate using photolithography and Si etching.
  • the optical interferometer 100 has an optical component which transmits light of the beam splitter 101 or the like, patterning is essential in metallization for the optical interferometer for improving optical use efficiency.
  • a side surface 102s of the movable mirror 102 serving as a target of formation of a metal film for configuring the mirror surface is a side surface formed by Si etching
  • the formation of a pattern of a metal by the photolithography is difficult.
  • the use of a metallization technique using a hard mask called the shadow mask is considered.
  • the side surface 101s of the beam splitter 101 is a half-mirror surface in Fig. 6 and a light transmission surface in Fig. 7 , both of which are non-metallized portions.
  • the optical use efficiency is degraded by an extension of the optical path length because the optical interferometer formed by Si etching has a small optical effective size.
  • the optical interferometer formed by Si etching has a small optical effective size.
  • Fig. 8 is a diagram illustrating an example of metallization using the shadow mask.
  • a distance between the shadow mask 144 and a metal target 146 is shortened from D2 to D1 and the horizontal-direction components of metal particles M from the metal target 146 is increased to form a uniform metal film 142 for a side surface 140a formed by Si etching.
  • High-energy sputtering rather than resistance deposition or EB deposition is suitable for such metallization.
  • the side surface 140a located around an opening portion 144a of the shadow mask 144 is a metallized portion serving as a mirror surface of a movable mirror and side surfaces 140b and 140c of both sides, for example, are non-metallized portions serving as half-mirror surfaces, light transmission surfaces, or the like.
  • the metal film 142 is also formed on a part of the side surface 140b which is a non-metallized portion. Accordingly, the side surface 140b is required to be away from the side surface 140a to prevent the metal film 142 from being formed on the side surface 140b.
  • the metal film is considered not to be formed on the side surface 140c.
  • a direction in which the metal particles M are directed becomes uniform by rotating the wafer 140 to uniformly form the metal film. That is, the metal film is actually formed even on the side surface 140c located at the side of the metal target 146 rather than the side surface 140a in Fig. 8 .
  • the side surface 140c is also required to be away from the side surface 140a to prevent the metal film from being formed on the side surface 140c.
  • the beam splitter and the movable mirror are not required to be away from each other according to an optical design of the optical interferometer, they are required to be away from each other because of the process design and a total optical path length of the optical interferometer is extended.
  • a spread angle of the beam (numerical aperture NA) is converted into 1/m. Because the creation of the parallel light indicates that the spread angle is reduced, it can be seen that it is only necessary to increase the image magnification m. In contrast, this indicates that it is not possible to generate parallel light having a smaller beam diameter from light having a predetermined spread angle in a certain diameter.
  • the beam diameter is 20 mm which is 100 times 2 ⁇ m.
  • a size of an optical surface formed by MEMS technology is 100 ⁇ m to about several hundreds of ⁇ m as an example, a major part of parallel light having a beam diameter of 20 mm is lost.
  • a decrease of a spread angle is limited, it is important to make the optical path length of the optical interferometer as short as possible to suppress the degradation of optical use efficiency by reducing the loss.
  • the wall portion 61 is arranged between the semiconductor portion 52 for the beam splitter 12 and the semiconductor portion 54 for the movable mirror 14.
  • the metal film 31 is formed on the side surface 14a of the semiconductor portion 54 using the shadow mask 70 (metallization is performed).
  • the side surface 12b of the semiconductor portion 52 which is the non-metallized portion is masked using the wall portion 61 (wall portion 65) while the side surface 14a of the semiconductor portion 54 which is the metallized portion is exposed from the opening portion 72 of the shadow mask 70.
  • the mirror surface by forming the metal film 31 on the side surface 14a which is the metallized portion while preventing the metal film from being formed on the side surface 12b which is the non-metallized portion even when the semiconductor portion 52 and the semiconductor portion 54 are close to each other. Therefore, the extension of the optical path length in the optical interferometer 1 can be suppressed because the beam splitter 12 and the movable mirror 14 can be formed to be close to each other. Consequently, it is possible to manufacture the optical interferometer 1 capable of suppressing an increase of loss due to the extension of the optical path length and suppressing the degradation of optical use efficiency.
  • the semiconductor portions 52 to 54 are formed by etching the semiconductor layer formed on the main surface 10s of the support substrate 10 and the insulating layer and the wall portion 61 is formed in step S101.
  • the semiconductor portions 52 to 54 are formed by etching the semiconductor layer formed on the main surface 10s of the support substrate 10 and the insulating layer and the wall portion 61 is formed in step S101.
  • the wall portion 78 protruding from the back surface 71b is formed on the back surface 71b of the mask portion 71 and the bottom portion 78s of the wall portion 78 is joined to the top portion 61 c of the wall portion 61 in step S103.
  • the side surface 12b of the semiconductor portion 52 can be masked by the wall portion 65 constituted of the wall portion 61 and the wall portion 78. Consequently, because the height of the wall portion to be used in the mask of the side surface 12b can be further decreased than when the wall portion is formed on any one of the main surface 10s of the support substrate 10 and the shadow mask 70, the formation of the wall portion is facilitated.
  • the insulating layer 22 is formed on the back surface 71b of the mask portion 71 and the back surface 71b of the mask portion 71 (more specifically, the bottom portion 78s of the wall portion 78) is joined to the semiconductor layer S via the insulating layer 22 in step S103.
  • the insulating layer 21 and the insulating layer 22 can be etched by the same etching agent, according to the present invention, it is possible to simultaneously perform the formation of the hollow structure such as the movable mirror 14, the removal of the wall portion 61, and the removal of the shadow mask 70 through one etching process on the insulating layers 21 and 22.
  • step S101 by etching the semiconductor layer formed on the main surface 10s of the support substrate 10 and the insulating layer, the semiconductor portions 52 to 54 are formed and the semiconductor portion (not illustrated) for the fixed mirror 15 and the third semiconductor portion (not illustrated) for the deflection mirrors 16 and 17 can be further formed on the main surface 10s and the insulating layer 21.
  • the third semiconductor portion is a portion serving as the deflection mirrors 16 and 17, the third semiconductor portion includes side surfaces 16a and 17a tilted 45 degrees with respect to a direction orthogonal to the main surface 10s. Therefore, in this case, the etching of the semiconductor layer in step S101 may include a plurality of etching processes.
  • the third wall portion (not illustrated) can be further formed by etching the semiconductor layer formed on the main surface 10s of the support substrate 10 and the insulating layer.
  • the third wall portion is arranged between the third semiconductor portion and the semiconductor portion 52 so that the third wall portion extends in a direction along the main surface 10s and a direction orthogonal to the main surface 10s.
  • the third wall portion is formed between the third semiconductor portion for the deflection mirror 16 and the semiconductor portion 52, the third wall portion is arranged between the side surface (third side surface) 16a of the third semiconductor portion at the side of the semiconductor portion 52 and the side surface 12a of the semiconductor portion 52 at the side of the third semiconductor portion.
  • the third wall portion is used to separately protect the side surface 12a which is the non-metallized portion from the side surface 16a which is the metallized portion in a subsequent metallization step (step S104).
  • the third wall portion is formed between the third semiconductor portion for the deflection mirror 17 and the semiconductor portion 52
  • the third wall portion is arranged between the side surface (third side surface) 17a of the third semiconductor portion at the side of the semiconductor portion 52 and the side surface 12b of the semiconductor portion 52 at the side of the third semiconductor portion.
  • the third wall portion is used to separately protect the side surface 12b which is the non-metallized portion from the side surface 17a which is the metallized portion in a subsequent metallization step (step S104).
  • the shadow mask 70 to be used in the metallization step can further include a second opening portion (not illustrated) formed in the mask portion 71.
  • the shadow mask 70 is arranged on the main surface 10s and the semiconductor layer S and joined to the semiconductor layer S so that the side surfaces 12a and 12b of the semiconductor portion 52 are masked by the mask portion 71 and the third wall portion and the side surfaces 16a and 17a of the third semiconductor portion are exposed from the second opening portion.
  • step S104 the mirror surface is formed in the third semiconductor portion by further forming the metal films 33 and 34 on the side surfaces 16a and 17a of the third semiconductor portion using the shadow mask 70. More specifically, the side surfaces 12a and 12b of the semiconductor portion 52 are masked by the mask portion 71 and the third wall portion and the metal films 33 and 34 are formed (metallized) on the side surfaces 16a and 17a in a state in which the side surfaces 16a and 17a are exposed from the second opening portion. Thereafter, in step S105, the second wall portion is further removed. Also, the formation of the metal films 33 and 34 can be performed simultaneously with the formation of the metal film 31.
  • the mirror surface can be formed by forming the metal films 33 and 34 on the side surfaces 16a and 17a which are metallized portions while preventing the metal film from being formed on the side surfaces 12a and 12b which are non-metallized portions. Therefore, because the beam splitter 12 can be formed to be close to the deflection mirrors 16 and 17, the extension of the optical path length in the optical interferometer can be further suppressed.
  • Fig. 9 is a schematic end view illustrating a modified example of a shadow mask illustrated in Fig. 3 .
  • Fig. 9(a) it is not necessary to form an insulating layer on an external surface of the mask portion 71 of the shadow mask 70.
  • the bottom portion 78s of the wall portion 78 is directly joined to the top portion 61c of the wall portion 61 (without using the insulating layer), so that the shadow mask 70 can be joined to the semiconductor layer S.
  • the wall portion 78 is not provided on the back surface 71b in the first region 75 of the mask portion 71 and only a protruding portion 71p may be provided.
  • the back surface 71b in the first region 75 of the mask portion 71 is separated from the top portion 61c of the wall portion 61.
  • the side surface 12b of the semiconductor portion 52 is masked by only the first region 75 of the mask portion 71 and the wall portion 61 (that is, without using the wall portion 78).
  • Fig. 10 is a schematic end view illustrating a modified example of the shadow mask illustrated in Fig. 3 .
  • the shadow mask 70 may have a wall portion (first wall portion) 79 formed on the back surface 71b so that the shadow mask 70 extends along the back surface 71b of the mask portion 71 instead of the wall portion 78.
  • the wall portion 79 protrudes from the back surface 71b to reach the main surface 10s.
  • the shadow mask 70 is arranged on the main surface 10s and the semiconductor layer S so that the wall portion 79 is arranged between the semiconductor portion 52 and the semiconductor portion 54 in step S103.
  • the wall portion 79 extending along the main surface 10s is arranged between the side surface 12b of the semiconductor portion 52 and the side surface 14a of the semiconductor portion 54.
  • the side surface 12b of the semiconductor portion 52 is masked by the wall portion 79 and the mask portion 71. That is, in this case, in step S101, the wall portion 61 for masking the side surface 12b is not formed.
  • the wall portion for separately protecting the non-metallized portion such as the side surface 12b of the semiconductor portion 52 from the metallized portion such as the side surface 14a of the semiconductor portion 54 only a wall portion formed on the support substrate 10 (via the insulating layer 21) can be used like the wall portion 61, a wall portion formed on the shadow mask 70 like the wall portion 78 and the wall portion 61 can be used together, or only the wall portion formed on the shadow mask 70 can be used like the wall portion 79.
  • the insulating layer 22 may be provided on an external surface as illustrated in Fig. 10(a) or no insulating layer may be provided as illustrated in Fig. 10(b) .
  • the bottom portion (bottom surface) 79s of the wall portion 79 is joined to the main surface 10s of the support substrate 10 via the insulating layer 22, so that the shadow mask 70 is supported on the main surface 10s.
  • the shadow mask 70 is supported on the main surface 10s by joining the bottom portion 79s of the wall portion 79 to the insulating layer 21.
  • a method of manufacturing an optical interferometer includes the following aspects. That is, the shadow mask has a first wall portion formed on a back surface so that the shadow mask extends along the back surface of the mask portion and the shadow mask is arranged on the main surface so that the first wall portion is arranged between the first semiconductor portion and the second semiconductor portion in the second step. Therefore, the first wall portion extending along the main surface may be arranged between the first side surface of the first semiconductor portion and the second side surface of the second semiconductor portion.
  • the second insulating layer may be formed on the back surface of the mask portion and the bottom portion of the first wall portion may be joined to the main surface via the second insulating layer in the third step.
  • the bottom portion of the first wall portion may be joined to the main surface via the first insulating layer.
  • an optical interferometer capable of suppressing the degradation of optical use efficiency due to an extension of an optical path length.

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  • Physics & Mathematics (AREA)
  • Spectroscopy & Molecular Physics (AREA)
  • General Physics & Mathematics (AREA)
  • Spectrometry And Color Measurement (AREA)
  • Instruments For Measurement Of Length By Optical Means (AREA)
  • Micromachines (AREA)
  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Mechanical Light Control Or Optical Switches (AREA)
EP14837699.9A 2013-08-19 2014-07-31 Method for manufacturing an optical interferometer Active EP3037792B1 (en)

Applications Claiming Priority (2)

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JP2013169479 2013-08-19
PCT/JP2014/070219 WO2015025691A1 (ja) 2013-08-19 2014-07-31 光干渉計を製造する方法

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JP6026597B1 (ja) * 2015-07-06 2016-11-16 浜松ホトニクス株式会社 光干渉計
JP5839759B1 (ja) * 2015-07-30 2016-01-06 浜松ホトニクス株式会社 光干渉計
WO2017218778A1 (en) * 2016-06-15 2017-12-21 Si-Ware Systems Integrated spectral unit
JP6814076B2 (ja) 2017-03-14 2021-01-13 浜松ホトニクス株式会社 光モジュール
WO2019009396A1 (ja) * 2017-07-06 2019-01-10 浜松ホトニクス株式会社 光学デバイス
WO2019009395A1 (ja) 2017-07-06 2019-01-10 浜松ホトニクス株式会社 光学デバイス
US11187872B2 (en) 2017-07-06 2021-11-30 Hamamatsu Photonics K.K. Optical device
WO2019009394A1 (ja) 2017-07-06 2019-01-10 浜松ホトニクス株式会社 光学デバイス
CN110799881B (zh) 2017-07-06 2021-12-07 浜松光子学株式会社 反射镜组件和光模块
JP7112876B2 (ja) 2017-07-06 2022-08-04 浜松ホトニクス株式会社 光学デバイス
CN110799882A (zh) 2017-07-06 2020-02-14 浜松光子学株式会社 光学器件
WO2019097772A1 (ja) 2017-11-15 2019-05-23 浜松ホトニクス株式会社 光学デバイスの製造方法

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US5784158A (en) 1995-11-22 1998-07-21 Lastek Laboratories Pty. Ltd. Broad spectrum spectrometer apparatus
US7405861B2 (en) * 2004-09-27 2008-07-29 Idc, Llc Method and device for protecting interferometric modulators from electrostatic discharge
CN1755502A (zh) * 2004-09-27 2006-04-05 Idc公司 用于防止干涉式调制器静电放电的方法及装置
JP2006332256A (ja) * 2005-05-25 2006-12-07 Canon Inc 配線基板の製造方法
US7796267B2 (en) 2006-09-28 2010-09-14 Si-Ware Systems System, method and apparatus for a micromachined interferometer using optical splitting
JP5302020B2 (ja) * 2009-01-26 2013-10-02 浜松ホトニクス株式会社 光モジュール
EP2545406B1 (en) * 2010-03-09 2015-02-11 SI-Ware Systems A technique to determine mirror position in optical interferometers
JP5736672B2 (ja) 2010-06-03 2015-06-17 株式会社ニコン 光学部品及び分光測光装置
JP5739224B2 (ja) * 2011-05-16 2015-06-24 浜松ホトニクス株式会社 光学部品の製造方法及び光学部品
JP5715481B2 (ja) * 2011-05-16 2015-05-07 浜松ホトニクス株式会社 光モジュール及びその製造方法
US9046690B2 (en) * 2011-10-20 2015-06-02 Si-Ware Systems Integrated monolithic optical bench containing 3-D curved optical elements and methods of its fabrication
US8922787B2 (en) * 2013-01-07 2014-12-30 Si-Ware Systems Spatial splitting-based optical MEMS interferometers

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WO2015025691A1 (ja) 2015-02-26
CN105492879A (zh) 2016-04-13
JP6295257B2 (ja) 2018-03-14
US9618323B2 (en) 2017-04-11
CN105492879B (zh) 2017-07-28
JPWO2015025691A1 (ja) 2017-03-02
EP3037792A4 (en) 2017-07-05
KR102153771B1 (ko) 2020-09-08
EP3037792A1 (en) 2016-06-29
US20160202037A1 (en) 2016-07-14
KR20160045755A (ko) 2016-04-27

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