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Definitions

• the current disclosure relates to methods of fabricating silicon nanowires, including ultra-thin and ultra-dense silicon nanowires.
• the disclosure also relates to methods of disposing such nanowires on layers and to devices containing silicon nanowires.
• Nanowires are an important class of nano-structured materials that have interesting physical and chemical properties. Silicon nanowires (SiNWs) have received extensive attention in the past decade due to the use of silicon in the semiconductor industry and also its high availability as the second most abundant element on Earth. Silicon nanowires show promise for use in a variety of SiNWs.
• nanoelectronics including nanoelectronics, opto-electronics, electromechanical devices, energy conversion and storage, biological and chemical sensors, and drug delivery devices.
• the present disclosure relates to a method of fabricating a silicon nanowire having a width of 100 nm or less by depositing a metal film on a silicon-containing layer, treating the metal film using a wet process to produce an interconnected metal network having gaps on the silicon-containing layer, and etching the silicon- containing layer with a metal-assisted etching process to form a silicon nanowire having a width of 100 nm or less, especially 50 nm or less.
• the present disclosure also relates to lithium ion batteries, thermoelectric materials, solar cells, chemical and biological sensors, and drug delivery devices containing silicon nanowires.
• FIGURE 1 A illustrates a silicon-containing layer with a metal film.
• FIGURE IB illustrates a silicon-containing layer with a metal network.
• FIGURE 1C illustrates a silicon-containing layer with silicon nanowires.
• FIGURE 2 presents a scanning electron microscope (SEM) image of silicon nanowires.
• FIGURE 3 presents a transmission electron microscope (TEM) image of a silicon nanowires.
• FIGURE 4 presents an SEM image of ultra-dense silicon nanowires.
• FIGURE 5 presents an SEM image of collapsed silicon nanowires.
• FIGURE 6 presents an SEM image of porous silicon nanowires.
• FIGURE 7 presents a TEM image of porous silicon nanowires.
• FIGURE 8 presents SEM images of patterned silicon nanowires.
• FIGURE 9 presents an SEM image of detached silicon nanowires.
• FIGURE 10 presents an SEM image of bunched silicon nanowires.
• FIGURE 11 illustrates a lithium ion battery having an anode containing silicon nanowires.
• FIGURE 12 illustrates a thermoelectric device containing silicon nanowires.
• FIGURE 13 illustrates a solar cell containing silicon nanowires.
• FIGURE 14 illustrates a biological sensor containing silicon nanowires.
• FIGURE 15 provides an SEM image of 20 nm wide silicon nanowires.
• FIGURE 16 provides an SEM image of 40 nm wide silicon nanowires.
• FIGURE 17 provides an SEM image of interconnected silicon nanowires.
• FIGURE 18 provides an SEM image of a silicon wafer after cycling in a lithium ion battery.
• FIGURE 19 provides an SEM image of silicon nanowires after cycling in a lithium ion battery.
• the current disclosure relates to methods of fabricating silicon nanowires, particularly ultra-think and ultra-dense silicon nanowires. In a specific embodiment, it relates to methods of fabricating silicon nanowires with a width of 100 nm or less, particularly 50 nm or less, or even 30 nm or less.
• the current disclosure further relates to methods of fabricating interconnected silicon nanowires, sometimes called silicon nanofences.
• the current disclosure additionally relates to methods of disposing such nanowires on layers and to a variety of devices containing silicon nanowires.
• width refers to either the average width of a silicon nanowire or a collection of silicon nanowires, as indicated by context.
• length refers to either the average length of a silicon nanowire or a collection of silicon nanowires, as indicated by context.
• silicon nanowires may be formed by depositing a metal film 10a on a silicon-containing layer 20 as shown in FIGURE 1A.
• metal film 10 may be treated to form interconnected metal network 10b with gaps 30 as shown in FIGURE IB.
• a silicon etching process in which the metal network 10b serves as a catalyst may be used to etch away silicon beneath the metal, producing silicon nanowires 40 where gaps 30 were previously located.
• the width of silicon nanowires 40 may be controlled by controlling the width of gaps 30.
• the length of silicon nanowires 40 may be controlled by controlling the etching time and etching conditions, e.g. temperature and etching solution concentration, etc.
• the silicon-containing layer 20 may be polycrystalline silicon or amorphous silicon. It may be, but need not be, a single crystalline silicon wafer. It may be, but need not be, any combinations of polycrystalline silicon, amorphous silicon and single crystalline silicon. In some embodiments, as metal or other conductor layer may be attached to the silicon-containing layer 20 on the opposite side of metal film 10a.
• the metal film 10a may be deposited by physical vapor deposition such as e-beam evaporation, thermal evaporation, sputtering. In some embodiments, the metal film 10a may be deposited by chemical vapor deposition. In a specific embodiment, the metal film may be gold (Au). The thickness of the metal film 10a, along with the wet process treatment time as described below both influence the width of resulting silicon nanowires 40. In a specific embodiment, the metal film may be between 0.1 nm and 200 nm, between 0.5 nm and 100 nm, or between 1 nm and 40 nm. The overall processing temperature during metal film deposition depends on the deposition approach. It can be several hundred degrees Celsius or higher. It may also be 150 °C or less, or even 100 °C or less. For example, it may be performed at room temperature by using e-beam evaporation.
• the metal film 10a may be treated by a wet process to form interconnected metal network 10b.
• it may be treated with a solution containing hydrogen peroxide (H 2 0 2 ) and sulfuric acid (H 2 S0 4 ), such as piranha solution.
• H 2 0 2 hydrogen peroxide
• H 2 S0 4 sulfuric acid
• the Piranha solution may be a mixture of 96 wt% sulfuric acid and 30 wt% hydrogen peroxide with a volume ratio of 1 :2.
• the weight percent for H 2 S0 4 in the solution may vary from 96 to 2 or less.
• the weight percent for H 2 0 2 in the solution may vary from 30 to 2 or less.
• Treatment with the Piranha solution may last for the length of time necessary to obtain gaps 30 corresponding to the desired with of the silicon nanowires 40.
• the length of time will be less.
• the length of time will be greater.
• the length of time with Piranha solution or another wet process may be between 1 second and 60 minutes. In a more specific embodiment, it will be between 1 minute and 20 minutes.
• the wet process may be performed at a temperatures of 150 °C or less. For example, it may be performed at room temperature.
• the hydrogen peroxide in piranha solution may be replaced by other oxidizers such as pure oxygen bubble, ozone, chlorine, iodine, ammonium perchlorate, ammonium permanganate, barium peroxide, bromine, calcium chlorate, calcium hypochlorite, chlorine trifluoride, chromic acid, chromium trioxide (chromic anhydride), peroxides such as hydrogen peroxide, magnesium peroxide, dibenzoyl peroxide and sodium peroxide, dinitrogen trioxide, fluorine, perchloric acid, potassium bromate, potassium chlorate, potassium peroxide, propyl nitrate, sodium chlorate, sodium chlorite, sodium perchlorate, and combinations thereof.
• oxidizers such as pure oxygen bubble, ozone, chlorine, iodine, ammonium perchlorate, ammonium permanganate, barium peroxide, bromine, calcium chlorate, calcium hypochlorite, chlorine trifluoride,
• the sulfuric acid in piranha solution may be replaced by one or more other acids, such as nitric acid, hydrochloric acid, hydrobromic acid, sulfurous acid, phosphoric acid, phosphorous acid, boric acid, silicic acid, and combinations thereof.
• acids such as nitric acid, hydrochloric acid, hydrobromic acid, sulfurous acid, phosphoric acid, phosphorous acid, boric acid, silicic acid, and combinations thereof.
• piranha solution is a 3 : 1 mixture of ammonium hydroxide (NH 4 OH) with hydrogen peroxide, also known as base piranha. This solution may be heated to 60°C to start the reaction.
• NH 4 OH ammonium hydroxide
• base piranha hydrogen peroxide
• the silicon etching process may be any metal-assisted etching (MAE) process.
• MAE metal-assisted etching
• it may be performed by exposing the silicon- containing layer 20 with metal network 10b to an etching solution, such as a solution containing hydrofluoric acid (HF) and an oxidizing agent, such as H2O2.
• H2O2 include Fe(N0 3 ) 3 , and other alternatives indicated for piranha solution above.
• the duration of the etching process determines the length of resulting silicon nano wires.
• the etching time may be 1 second and 10 hours. In a more specific embodiment, it will be between 1 minute and 60 minutes.
• the etching process may be performed at a temperatures of 100 °C or less. For example, it may be performed at room temperature.
• the metal After etching, the metal remains around the bottom of the nano wires.
• an optional etching step may be applied to remove the metal.
• the metal may be removed by wet etching.
• the etchant may be Aqua Regia which is a mixture of HCl and HN0 3 with a ratio around 1 :3.
• the etchant may be a solution of KI and I2 with various ratios. It may also be any other gold etchant.
• Silicon nanowires 40 resulting from this process may be anchored to the silicon base.
• the silicon base is attached to a metal or other conductor prior to etching, the silicon nanowires may be attached to the conductor.
• the silicon base which may be in the form of a film, may also be attached to an insulator or another semiconductor prior to etching. Then the silicon nanowires may be attached to the insulator (for example, the silicon nitride shown in FIGURE 9) or another semiconductor.
• Silicon nanowires 40 may have a width of 100 nm or less, 90 nm or less, 50 nm or less, 30 nm or less, or even 15 nm or less.
• silicon nanowires 40 resulting from a single process on a single piece of silicon-containing layer 20 may have a variation in width among wires of 5 nm or less. They may also have a variation in length among wires of 1 nm or less.
• the process described above may result in silicon nanowires with a width of 18 nm with a variation of less than 5 nm among wires and a substantially uniform length as detected by a scanning electron microscope (SEM). .
• SEM scanning electron microscope
• the process described above may result in silicon nanowires with a width of 15 nm as detected by a transmission electron microscope (TEM).
• TEM transmission electron microscope
• Silicon nanowires produced by processes of the present disclosure may be ultra-dense while they remain attached to the underlying silicon (or, if a conductor is present, the underlying conductor).
• the nanowires density may be as high as 10 11 silicon nanowires/cm 2 .
• the density may be 10 8 silicon nanowires/cm 2 .
• the silicon nanowires when they are sufficiently long and thin, they may collapse into a coat on the silicon (or underlying conductor, insulator or semiconductor, if present) surface, as shown in FIGURE 5.
• porous silicon nanowires may be formed using the above methods.
• silicon-containing layer 20 may be doped with a material known as dopant.
• silicon-containing layer 20 may be doped with n-type dopants such as P, As, Sb, or p-type dopants such as B, Ga, In.
• the amount of dopant, along with the etching time, may determine the porosity of the resulting porous silicon nanowires. In specific embodiments, between 5% to 70% of the silicon nanowire volume, on average, may be occupied by pores.
• Example porous silicon nanowires are presented in FIGURE 6 and FIGURE 7.
• the etching process may require more time than non-porous silicon nanowires.
• the etching time may be between 1 second and 10 hours.
• the etching time may depend on dopant concentration, etching solution concentration, etching temperature, and other factors. In general, longer etching times and higher dopant concentrations yield more porous nanowires.
• Silicon nanowires may also be formed on the silicon-containing layer 20 (or underlying conductor, insulator or semiconductor, if present) in patterns by first patterning the deposited metal film 10a.
• Example patterned nanowires are shown in FIGURE 8.
• a thin metal film 10a may be applied to the silicon-containing layer 20.
• the metal film may be 4 nm thick or less.
• silicon nanowires may be formed on another film by placing the silicon-containing layer 20 on the film, such as silicon nitride (SiN x ).
• the silicon nanowires will have a length generally equal to the thickness of the silicon-containing layer 20.
• the silicon-containing layer was 1.4 ⁇ thick and the resulting silicon nanowires were 1.4 ⁇ long. If the silicon- containing layer does not adhere well with the underlying film, such as SiN x , the silicon nanowires after formation may leave the film and become free silicon nanowires, as shown in FIGURE 9.
• silicon nanowires may be removed from the silicon-containing layer and placed on a metal or other conductor film by transferring the silicon nanowires or by breaking them off the layer, then attaching them to the conductor.
• the silicon nanowires may be formed on a sacrificial layer, such as silicon nitride. In another embodiment, sonication may be used to free silicon nanowires.
• fragmented silicon nanowires which may be in the form of nanowires shorter than those originally formed, or silicon nanoparticles having a length comparable to their width may be formed by subjecting silicon nanowires to sonication, typically to a degree greater than that required simply to remove silicon nanowires from the silicon-containing layer. These fragmented nanowires may also be porous.
• a silicon nanowire containing electrode may be formed by attaching silicon nanowires to a conductive film using a binder.
• the binder may also contain conductors, such as carbon particles, tin particles.
• Silicon nanowires may tend to form bunches, as shown in FIGURE 10, after wetting. Long, thin silicon nanowires may be particularly prone to bunching.
• Nanowire bunching may be decreased or avoided by using critical point drying to avoid surface tension when drying the nanowires. It may also be decreased or avoided by using a liquid with low surface tension for a final nanowire cleaning step. For example, ethyl alcohol has a lower surface tension (22.3 dynes/cm) than water (72.8 dynes/cm) at 20 °C and therefore might make a suitable final cleaning agent. Nanowire bunching may also be decreased or avoided by applying electricity to the silicon nanowires, which will then acquire a charge and repel one another.
• FIGURE 11 illustrates the components of a lithium ion battery 100.
• the battery contains cathode 110, anode 120, and electrolyte 130.
• lithium ions (Li ) 140 move between cathode 110 and anode 120 through electrolyte 130 while electrons more through external circuit 150 in the form of an electric current.
• a separator (not shown) between cathode 110 and anode 120 allows lithium ions 140 to pass, but is electrically insulative, such that electrons must flow through external circuit 150.
• the example lithium ion battery 100 illustration presented in FIGURE 11 is from Teki, R., M. K. Datta, et al., "Nanostructured Silicon Anodes for Lithium Ion Rechargeable Batteries.” Small 5(20): 2236-2242 (2009), incorporated in material part by reference herein.
• Cathode 110 may include any cathode material suitable for use in a lithium ion battery.
• it may include a lithium metal oxide (LiM0 2 ), such as lithium cobalt oxide (LiCo0 2 ), or a lithium metal phosphate (LiMP0 4 ), such as lithium iron phosphate (LiFeP0 4 ).
• Cathode 110 may contain non electrochemically active materials, such as binders and conductors, in addition to electrochemically active materials.
• Electrolyte 130 may be any electrolyte containing lithium ions and suitable for use with the cathode and anode combination.
• it may include a lithium salt in an organic solvent.
• it may include a non-coordinating anion salt, such as lithium hexafluorophosphate (LiPF 6 ), lithium hexafluoroarsenate monohydrate (LiAsF 6 ), lithium perchlorate (L1CIO 4 ), lithium tetrafluoroborate (L1BF 4 ), and lithium triflate (L1CF3SO3).
• Suitable organic solvents include organic carbonates, such as ethylene carbonate or diethyl carbonate.
• Anode 120 may contain silicon nanowires formed as described above.
• silicon is a promising anode material for lithium ion batteries due to its theoretical capacity of 4200 mAh/g, as compared to the 372 mAh/g capacity of current graphite anodes. Its potential has not been realized due to a tendency of silicon to crack due to volume changes as lithium ions enter and leave the anode. This cracking impeded the performance of and may ultimately destroy the anode, thereby limiting the number of recharge cycles for the battery. Silicon nanowires may avoid or significantly decrease this cracking problem, greatly improving the number of possible recharge cycles and overall battery life. In one embodiments, silicon nanowires may avoid cracking due to the presence of free space between the nanowires and their ability to move. Porous nanowires may provide even greater strain relaxation capacity.
• the ability of silicon nanowires to be produced in very dense configurations may allow improvements in power or energy per unit area in lithium ion batteries as compared to those using traditional silicon anode materials. Porous nanowires may also provide improved power density. The pores in the porous silicon nanowires provide more free space and may further reduce the pulverization (e.g. cracking) of a silicon anode.
• silicon nanowires may be placed in electrical contact with a conductive metal film, such as copper foil, or other conductive film in anode 120. Any silicon-containing layer from which the nanowires are formed may interfere with electrical contact. This interference may be avoided in at least three ways. First, the silicon nanowires may be formed from a silicon-containing layer that is on a metal film prior to etching. Second, the silicon nanowires may be etched from a silicon-containing layer, then transferred to a metal film, for example with the remaining silicon-containing layer intact. In a third process, the silicon nanowires may be formed from a silicon-containing layer, then removed from the layer, for example by being broken off using sonication or other methods. The free silicon nanowires may then be mixed with other anode materials for form a composite anode material on the conductive film. Fragmented silicon nanowires or nanoparticles may be used to form a composite anode material in a similar way.
• a conductive metal film such as copper foil, or other conductive film
• Silicon nanowires with a width of 20 nm or less may improve battery cycling performance.
• thermoelectric devices have wide applications in energy harvesting and electrical cooling. Improved thermoelectric devices may greatly reduce energy loss in these processes. For example, 90% of the world's power is generated through heat generation. 60-70% of this heat is lost to the environment. Theremoelectic devices have the ability to recapture some of this wasted heat, thereby reducing energy loss. Conventional thermoelectric devices, however, are too expensive to be put to this use. Silicon nanowires made according to the above processes, however, are relatively cheap. Furthermore, due to increased surface scattering when compared to silicon wafers, even conventional silicon nanowires have a figure of merit (ZT) 100 times higher. Additional improvements in figure of merit may be achieved using nanowires produced according to the above processes because such wires may be thinner than conventional silicon nanowires and because they may be porous, both properties serving to further increase surface scattering.
• ZT figure of merit
• silicon nanowires may be placed in areas of heat loss in power generators and connected to electrical supplies to supply additional power. Silicon nanowires may also be used in other thermoelectric applications.
• thermoelectric device containing silicon nanowires is illustrated in FIGURE 12.
• the thermoelectric device 200 may contain top contact 210, silicon nanowires 220, and silicon layer/contact 220.
• the example thermoelectric device illustration presented in FIGURE 12 is from Curtin, B., E. Fang, et al., "Highly Ordered Vertical Silicon Nanowire Array Composite Thin Films for Thermoelectric Devices.” Journal of Electronic Materials 41(5): 887-894 (2012), incorporated in material part by reference herein. Use of Silicon Nanowires in Solar Cells
• silicon nanowires may be used in the place of high quality silicon. These nanowires may obtain high energy conversion efficiency even when made from metallurgical grade silicon or other silicon with high impurity levels. Silicon nanowires may further improved solar cell performance by increasing light absorption through increased surface area. The width of silicon nanowires may be adjusted using the methods described herein to obtain optimal solar cell efficiency.
• FIGURE 13 An example solar cell containing silicon nanowires is illustrated in FIGURE 13.
• the solar cell 300 may contain vertically aligned silicon nanowires 310 which receive photons 320.
• the example solar cell illustration presented in FIGURE 13 is from Kayes, B. M., M. A. Filler, et al., "Radial PN junction, wire array solar cells.” Photovoltaic Specialists Conference, 2008. PVSC '08. 33rd IEEE, incorporated in material part by reference herein.
• FETs Silicon nanowire field effect transistors
• the abilities of FETs are due largely to the large surface area-to-volume ratio of silicon nanowires as well as their comparability in size to chemical and biological molecules.
• FETs may provide ultra high sensitivity, label- free detection, and direct electrical real time readouts.
• the width of silicon nanowires may be adjusted using the methods described herein to optimize sensitivity for different chemical and biological molecules.
• ultra-thin silicon nanowires may be able to sense some molecules at low concentrations that are no detectable using silicon nanowires fabricated using conventional methods.
• doped silicon nanowires which are sometimes useful in FETs, are easier to obtain using the present methods as compared to conventional methods, such as chemical vapor deposition methods.
• FIGURE 14 An example biological sensor containing silicon nanowires is shown in FIGURE 14.
• the biological sensor 400 contains two sets of electrodes 410 electrically contacting with a set of nano wires 420 with receptors 430 attached to the nanowires 420. When target biological molecules 440 bind to receptors 430, conductance between the sets of electrodes 410 through nanowires 420 is changed.
• the example biological sensor illustration presented in FIGURE 14 is from Patolsky, F., G. Zheng, et al., "Nanowire sensors for medicine and the life sciences.”
• Silicon nanowires and particularly porous silicon nanowires prepared according to the methods of this disclosure may be used to deliver drugs within a patient.
• the drugs may be attached to or located within the pores of the silicon nanowires.
• the silicon nanowires may be detached from the silicon-containing layer prior to drug delivery. Silicon nanowires provide enhanced abilities to deliver drugs locally and even into cells. This may improve drug efficacy, lower drug toxicity, or both.
• each long silicon nanowire may be fragmented into nanowires with shorter lengths.
• the fragmented nanowires may be nanoparticles.
• porous or non-porous fragmented nanowires, or porous or non-porous nanoparticles may be used as drug carriers to improve drug efficacy, lower drug toxicity, or both.
• Silicon nanowires may be used as nanocarriers as generally described in Peer, D. et al, "Nanocarriers as an emerging platform for cancer therapy," Nature Nanotechnology 2: 751-760 (2007), incorporated in material part by reference herein.
• a 25 nm gold film was deposited on silicon and treated for 3 minutes with Piranha solution and the resulting metal network and silicon were etched in a metal- assisted etching process.
• a 25 nm gold film was treated for 15 minutes with Piranha solution and the resulting metal network and silicon were etched in a metal-assisted etching process.
• the resulting nanowires as shown in FIGURE 16, had a width of 40 nm.
• a 3 nm gold film was treated for 3 minutes with Piranha solution and the resulting metal network and silicon were etched in a metal-assisted etching process.
• the resulting nanowires were interconnected, as shown in FIGURE 17.
• Example 2 Silicon Nanowire Anode for a Lithium Ion Battery
• Silicon nanowires with a width of 30 nm or less were fabricated using a highly Sb-doped N-type silicon wafer layer to form a silicon nanowire anode.
• the resulting nanowires were about 5 ⁇ long.
• the resistivity of the silicon nanowire anode was 0.008-0.02 ohm-cm.
• the anode was combined with a lithium cobalt oxide (LiCo0 2 ) cathode in a test cell and cycled. Although the silicon wafer exhibited substantial cracking after cycling (FIGURE 18), the silicon nanowires showed no damage (FIGURE 19).

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