Classifications

• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C27/00—Electric analogue stores, e.g. for storing instantaneous values
  • G11C27/02—Sample-and-hold arrangements
  • G11C27/024—Sample-and-hold arrangements using a capacitive memory element

Definitions

• the present invention relates to a compact sample-and-hold device. It applies in particular to the input stages of fast analog-digital converters.
• the performance of the converters therefore closely depends on the performance of the sample-and-hold device.
• Sampling-blocking consists in charging a so-called holding capacity during a first phase of tracking ("track”) or sampling ("sample”) of the input signal, and isolating this capacity from the signal of input that can continue to vary, thereby blocking the value of the voltage across the capacity.
• track tracking
• sample sampling
• the quantization of the signal can be performed.
• a problem that arises is to perform this switching so that the sampled signal reproduces as faithfully as possible the input signal at the moment of blocking.
• a first solution is the diode bridge, particularly described in JR Gray and SC Kitsopoulos "A Precision Sample-and-Hold Circuit with Subnanosecond Switching". IEEE Transactions on Circuit Theory, CT1 1, September 1964, pages 389-396, with multiple variants.
• a switched follower solution requiring only a current source is preferred in integrated circuits. It is described in particular in US36431 10, multiple variants being used.
• the subject of the invention is a sample-and-hold device comprising a holding capacitor C H , said sample-and-hold device operating in a tracking phase during which the voltage at the terminals of said capacitor follows the input signal Vin of said sampler -blocker and according to a holding phase during which the capacitance is isolated from said input signal Vin, the sample-and-hold device comprising at least:
• a third bipolar transistor Q3 whose base is connected to the collector of the transistor Q2 and the emitter is connected to the base of the transistor Q2, the signal present on the emitter of the transistor Q3 forming the output signal Vout of said sample-and-hold device;
• said differential pair Q1, Q2 being supplied by a current 21, the transistor Q2 being charged by said current source (20) and by the holding capacitor C H ,
• the charging current of the holding capacitor C H opposite the current of said source is for example obtained by switching a portion of the current 21 supplying the differential pair to said capacitance.
• the portion of the current 21 is for example equal to half of the current 21 supplying the differential pair.
• the current source 21 of the differential pair in the tracking phase is formed by two bipolar transistors Q4, Q6 in series each with a current source, the collectors of transistors Q4 and Q6 being connected to the emitters of transistors Q1, Q2 of said differential pair, the transistors Q4 and Q6 being controlled at the opening during the tracking phase and at the closing during the holding phase;
• the source of current in the holding phase being formed by another bipolar transistor Q5 in series with the current source of the transistor Q4, the collector of the transistor Q5 being connected to the holding capacitor C H , the transistor Q5 being controlled by the opening during the holding phase and closing during the monitoring phase.
• the sample-and-hold circuit comprises, for example, a bipolar transistor Q7 connected in series with the current source of the transistor Q6, the transistor Q7 being controlled at the opening during the holding phase and at the closing during the tracking phase.
• a differential pair of bipolar transistors Q8, Q9 is connected in series with the transistor Q7, the base and the collector of the transistor Q8 being connected to the emitters of the transistors Q1 and Q2, the collector of the transistor Q9 being connected at the collector of transistor Q1 and its base being connected to the base of transistor Q2.
• a bipolar transistor Q10 is interposed between the input point able to receive the input signal Vin and the base of the transistor Q1, the emitter of the transistor Q10 being connected on the base of the transistor Q1 , the input signal (Vin) being applied on the basis of the transistor Q10.
• a transistor Q1 1 is connected between the holding capacitor (C H ) and the transistor Q5, the emitter of transistor Q1 1 being connected to the collector of transistor Q5.
• FIG. 2 the principle of producing a sample-and-hold device according to the invention
• FIGS. 3a and 3b illustrations of the respective operations in follower mode and in maintenance mode
• FIG. 4 a first exemplary embodiment of a sampler according to the invention
• FIGS. 5 to 7 alternative embodiments of the sample-and-hold device as shown in FIG. 4.
• FIG. 1 illustrates the principle of sampling-blocking consisting in charging a so-called holding capacity C H during a first phase of monitoring the input voltage Vin, and in isolating this capacitance from this same input signal during a second phase of maintenance.
• Figure 1 shows a basic exemplary embodiment used in most sample-and-hold systems, using diode switching, or base-emitter junction.
• the diode 1 is passing in tracking phase, or "track" mode, the output voltage Vout being equal to the input voltage Vin at the junction voltage near.
• a capacitor C H connected between the cathode of the diode and a reference potential, charges at the output voltage Vout.
• the diode is locked in the holding phase, "hold” mode, isolating the capacity of the input voltage, phase during which the voltage across the capacitors, equal to Vout, remains maintained at the value of the input voltage at the time of diode switching, switching from the off state to the off state.
• the transition to the off state is controlled by a reverse voltage applied between the anode and the cathode of the diode. The control of this reverse voltage allows the control of the sampling-blocking.
• a diode switching device As previously indicated, a diode switching device, or base-emitter junction, is highly nonlinear. In particular, when the reverse voltage is applied, there is injection of charges into the holding capacitor C H , introducing a parasitic voltage which is added to the signal. Of moreover, the isolation between the input and output is low because of the junction capacity of the diode 1, especially at high frequencies. Finally, it is recalled that such a diode switching device must be preceded by an input stage in order to isolate it and an output stage in order to isolate the capacitance. These stages result in additional energy consumption and additional nonlinearities.
• FIG. 2 illustrates the principle of producing a sample-and-hold device according to the invention.
• the invention includes charging and discharging the holding capacitance through a current source controlled by the input signal, so that the output voltage across the holding capacitance follows the input signal, and to cut off the power source during the blocking phase.
• the charging and discharging of the holding capacity is carried out only by current sources.
• a sample-and-hold device comprises a differential pair Q1, Q2, composed of two bipolar transistors, of the NPN type, connected in common emitters.
• the input of the signal Vin is based on the first transistor Q1.
• the collector of the second transistor Q2 is connected to the holding capacitor C H.
• the base of the second transistor of the pair, Q2 is looped back on the emitter of a third bipolar transistor Q3, NPN type, mounted in follower mode.
• This transistor Q3 has the particular function of following the voltage present on the collector of Q2, its base being connected thereto.
• the differential pair is supplied with a current 21 by a channel 21, the transistor Q2 being charged by a source of current I and by the holding capacitor C H.
• the invention consists in particular in charging the holding capacitor C H through a current source controlled by the input signal Vin, so that the output voltage Vout 'across the terminals of the holding capacitance C H follows the input signal Vin.
• the transition from the follower mode to the locked mode, corresponding to the holding phase, is performed by cutting the channel 21 of the current 21 supplying the differential pair Q1, Q2 and diverting one half towards the holding capacity by another way 22 so as to that this capacity is charged by two currents of the same value, constant, and opposite.
• the voltage at the terminals of the capacitance is then maintained at the value Vout ', equal to the value Vin at the moment of the switching of the channels 21, 22, increased by the base-emitter voltage of Q3.
• the output voltage Vout is taken at the output of the emitter of the transistor Q3 which follows the voltage present on the collector of Q2, therefore the voltage present on the holding capacitor C H , and finally Vin.
• a third channel 23 is for example provided to drive the other half of the unused current 21 for blocking the capacitance voltage.
• Current sources 220, 230 are connected in series on the channels 21, 22, 23 depending on whether the device is in follower mode or in maintenance mode.
• a residual current from the emitter of transistor Q3 is regulated in a current source 300 connected in series on the emitter of transistor Q3.
• the set of components is connected to the terminals of a power source Vcc, the currents being supplied by the latter. More particularly, the collectors of transistors Q1 and Q3 are connected to the positive terminal of Vcc.
• the current source 20 is connected between the positive terminal of Vcc and the transistor Q2.
• the voltage references are taken with respect to the negative terminal of Vcc.
• the invention makes it possible to obtain a structure that combines the switching device, the input stage and the output stage.
• the invention thus advantageously makes it possible to produce a compact sample-and-hold device while having very good energy and linearity performances.
• FIGS. 3a and 3b respectively show the equivalent electrical diagram of the device of FIG. 2 for the follower mode and for the hold mode, for establishing the voltage across the capacitors C H.
• the differential pair Q1, Q2 is supplied by a current 21 via the channels 21, 22, the transistor Q2 being charged by a current I and by the holding capacitor C H whose voltage at the terminals follows the input voltage Vin.
• the channels 21, 22, 23 have been switched so as to cut off the current 21 supplying the differential pair, the latter being no longer powered.
• One half of the current is diverted to the holding capacitor C H by the channel 22 so that this capacitance is charged by two opposite constant currents, the current I supplied by the source connected to the collector of the transistor Q2 and the current I traveling to the source 220 of track 22.
• FIG. 4 shows an exemplary possible embodiment of a sample-and-hold device according to the invention operating according to the principle of the diagram of FIG. 2.
• the current source 21 which supplies the differential pair Q1, Q2 is performed by two transistors Q4, Q6. These two transistors are connected to the differential pair via the current supply channel 21. More particularly, the collector of the transistor Q4 and the collector of the transistor Q6 are connected to the emitters of the transistors Q1, Q2.
• the current source 21 is formed of two current sources I, made one by the transistor Q4 in series with a first source 220 and the other by the transistor Q6 in series with a second source 230. To represent the formation of these sources, the latter are represented symbolically in FIG. 4 and connected to transistors Q4 and Q6.
• the emitter of the transistor Q4 is connected to the first current source 220 and the emitter of the transistor Q6 is connected to the second current source 230.
• the current source I is made by a transistor Q5 which deflects a portion of the current 21 which supplies the differential pair.
• the collector of the transistor Q5 is connected to a terminal of the holding capacitor C H and its emitter is connected in series with the first current source 220 mentioned above, the transistors Q4 and Q5 being connected in common emitters.
• the other terminal of the capacitor C H is connected to the reference potential of the source Vcc.
• a transistor Q7 makes it possible to deflect the other half of the current 21, which is not assigned to the holding capacitance C H , during the holding mode.
• the collector of the transistor Q7 is connected to the positive terminal of the power supply Vcc and its emitter is connected to the second power source 230 mentioned above, the transistors Q6 and Q7 being connected in common transmitters.
• Signals 31, 32, 33 control the bases of transistors Q4, Q5, Q6 and Q7 to control switching from one mode to another.
• a signal 31 controls the transistors Q4 and Q6 on opening while a signal 32 controls the transistors Q5 and Q7 on closing.
• Current 21 then supplies the differential pair.
• FIG. 5 shows an alternative embodiment of the embodiment of FIG. 4.
• the emitter voltage of the differential pair Q1, Q2 is kept constant during the holding phase so that the transistors are effectively blocked.
• This emitter voltage is kept constant by the addition of a differential pair composed of a transistor Q8 and a transistor Q9, the base and the collector of Q8 being connected to the emitters of Q1 and Q2, the collector of Q9 being connected at the positive terminal of Vcc, the base of Q9 being connected to the base of Q2, the emitters of Q8 and Q9 being connected to the collector of the transistor Q7.
• the current I flows in the transistor Q7 and in the transistor Q9.
• the emitter voltage of the transistors Q1 and Q2 is kept constant, equal to the output voltage Vout via the base-emitter voltages of the transistors Q8 and Q9.
• FIG. 6 shows another variant with respect to the embodiment of FIG. 4.
• a follower stage is added as input.
• This follower stage replicates the output follower stage and therefore makes the entire device symmetrical.
• a follower transistor Q10 is interposed between the input of the signal Vin and the base of the transistor Q1. More particularly, the input signal Vin arrives at the base of transistor Q10, the Q10 collector being connected to the positive terminal of Vcc and its emitter being connected to the base of transistor Q1. To symmetry the assembly and control the current, the emitter of the transistor Q10 is also connected to a current source 600, similar to the source 300 connected to the output follower.
• FIG. 7 shows another variant with respect to the embodiment of FIG. 4.
• a transistor Q1 1 is cascode-mounted with transistor Q5 so as to further isolate the holding capacitance C H from the variations of FIG. control 31, 32.
• the collector of the transistor Q1 1 is connected to the holding capacitor C H and its emitter is connected to the collector of the transistor Q5.
• the transistor Q1 1 is controlled at the opening by means of a voltage V caS cod e connected between its base and the reference potential.
• V caS cod e connected between its base and the reference potential.

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