Classifications

• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L25/00—Baseband systems
  • H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
  • H04L25/40—Transmitting circuits; Receiving circuits
  • H04L25/49—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems
  • H04L25/4904—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using self-synchronising codes, e.g. split-phase codes
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
  • H03M5/00—Conversion of the form of the representation of individual digits
  • H03M5/02—Conversion to or from representation by pulses
  • H03M5/04—Conversion to or from representation by pulses the pulses having two levels
  • H03M5/06—Code representation, e.g. transition, for a given bit cell depending only on the information in that bit cell
  • H03M5/12—Biphase level code, e.g. split phase code, Manchester code; Biphase space or mark code, e.g. double frequency code
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L1/00—Arrangements for detecting or preventing errors in the information received
  • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
  • H04L1/0045—Arrangements at the receiver end
  • H04L1/0047—Decoding adapted to other signal detection operation

Definitions

• the present invention relates to a method and a device for demodulating at least one received frame, the frame consisting of a succession of bits coded according to a Manchester code.
• the Manchester code is a code in which the value of a bit is encoded by a falling or rising edge.
• the binary value "0” is encoded by a falling edge and the binary value "1" is encoded by a rising edge.
• the Manchester code is often used in data transmissions between a transmitter and a receiver interconnected by capacitive or magnetic coupling.
• the Manchester code is simple to implement but is sensitive to spurious pulses that create rising and falling edges on the transmitted signal.
• These parasitic pulses are for example created by mechanical vibrations and / or electromagnetic interference.
• a conventional solution is to add, in the transmitted data frame, redundancy data so as to correct the errors caused during decoding. by the spurious pulses or to add in the transmitted data frame parity data which makes it possible to detect at least one error during the decoding. In very noisy environments, it is then necessary to add a large amount of redundancy or parity data. This has the effect of increasing the size of the frame or reducing the amount of useful data included in the frame if the size of the frame is fixed.
• the object of the present invention is to solve the disadvantages of the prior art by proposing a method and a device for demodulating at least one frame consisting of a succession of bits encoded according to a Manchester code which makes it possible to detect effectively any demodulation errors related to the presence of spurious pulses in the received signal.
• the invention proposes a method for demodulating a received frame, the frame being constituted by a succession of a predetermined number of bits coded according to a Manchester code, characterized in that the method includes the steps of:
• the present invention also relates to a device for demodulating at least one received frame, the frame consisting of a succession of a predetermined number of bits coded according to a Manchester code, characterized in that the demodulation device comprises:
• - demodulation means for each determined time, if the determined time is greater than the first predetermined value and is less than the second predetermined value, of at least one binary value of the frame from the determined time and from a previously determined binary value.
• the determined binary value is dependent on the previously determined binary value.
• the method further comprises the step of reinitializing the decoding of the frame if the value of the second counter is greater than the second predetermined threshold.
• a predetermined number of frames is received, the frames being spaced apart temporally and the demodulation device:
• the present invention makes it possible to detect the spurious pulse, to reset the decoding so as to be ready to decode the frame.
• the validation of the communication being done frame by frame it is thus possible, for example when several parasitic pulses are present in the received signal, to receive a partial communication with a part of the validated frames. Since the time spacing between the different frames is defined by a duration greater than the maximum duration expected between two interruptions within the same frame, the demodulation algorithm is reset by this dead time, which makes it possible to have an algorithm reset at the start of the next frame, regardless of the previous frame validation.
• the frames include a label or are numbered.
• This information makes it possible, in the event of partial recovery of the communication, that is to say in the event of loss of frame induced by the presence of a spurious pulse, to identify the correctly received frames and to correctly interpret the data received without data assignment error.
• the present invention is particularly well suited to configurations in which it is difficult to accurately predict the time period within which a frame arrives.
• the present invention does not require a window in time which restricts the moment at which the different frames are received.
• the demodulation device :
• the third predetermined threshold being representative of a maximum time for the decoding of all the frames
• the frames not received at the end of the demodulation are considered invalid because the time required to receive said frames is greater than a maximum time expected for the reception of said frames.
• the first counter is an asynchronous cyclic counter of the other counters, of less duration than the duration of the reception of the frames and a third counter counts the number of exceeding of the capacity of the first counter.
• the third counter is reset each time a minimum of one binary value is demodulated.
• the time determined between each interruption and used to demodulate the frame is then corrected by the value of the third counter, in order to take into account the cyclic aspect of the first counter.
• each frame furthermore comprises information enabling verification of whether the bits of a decoded frame have been correctly decoded.
• the front is a falling edge.
• FIG. 1 shows an exemplary embodiment of a frame demodulation device according to the present invention
• Figs. 2a to 2c show a frame demodulation algorithm according to the present invention
• FIG. 3a shows a first example of a portion of a bit frame received by the frame demodulation device according to the present invention
• FIG. 3b is a second example of a portion of a bit frame received by the frame demodulation device according to the present invention.
• Fig. 1 shows an exemplary embodiment of a frame demodulation device according to the present invention.
• the frame demodulation device 10 is adapted to perform, from one or more software modules, the steps of the algorithm as described with reference to FIGS. 2a, 2b and 2c.
• the frame demodulation device 10 comprises a communication bus 101 to which are connected a processor 100, a non-volatile memory 102, a random access memory 103 and three counters, a first counter Te, a second counter Ext and a third counter NOVFLW.
• the non-volatile memory 102 stores the software module (s) implementing the invention, as well as the data enabling the algorithms to be implemented as described with reference to FIGS. 2a to 2c.
• This storage means is readable by the microprocessor 100.
• This storage means is integrated or not to the frame demodulation device 10 and can be removable.
• the software module (s) according to the present invention is or are transferred (s) into the random access memory 103 which then contains the executable code according to the present invention as well as the data necessary for the implementation of the invention.
• the first counter CT is a sixteen-bit cyclic counter which counts from 0 to FFFF in hexadecimal over a period of the order of 118 ms.
• the CT counter resets to zero when the FFFF value is reached and automatically resumes counting.
• the third counter NOVFLW counts each time the counter TC reaches the value FFFF.
• the counter NOVFLW is reset to the zero value on instruction of the processor 100. It should be noted here that the counter NOVFLW is here in the form of a component, the counter NOVFLW can alternatively be implemented in software form.
• the counters TC and NOVFLW make it possible to determine whether the time between two consecutive interrupts is not greater or less than it should be in operation without stray pulses in the signal.
• the second counter Ext is, for example, initialized to a predetermined value and counts down to zero.
• the countdown between the predetermined value and the zero value is carried out over a duration of the order of two one hundred milliseconds which represents the maximum duration allocated to the reception of the different frames.
• the parameters of the counter Ext allow to define the maximum time for the decoding of the bit frames received.
• the frame input interface 108 for example at each falling edge of the received binary signal, generates an interrupt for the processor 100.
• the frame input interface 108 generates an interrupt to the processor 100 at each rising edge of the received binary signal.
• the frame input interface 108 generates an interrupt to the processor 100 at each edge of the received binary signal.
• the frame demodulation device 10 may consist of one or more electronic component (s).
• Figs. 2a to 2c show a frame demodulation algorithm according to the present invention.
• the present algorithm is executed by the processor 100 of the frame demodulation device 10.
• the present algorithm is described in an exemplary embodiment in which the interrupts are generated at each falling edge of the received signal.
• the modulated frames according to the present invention are, in a particular embodiment, a sequence of three frames consisting of 28 bits coded with a Manchester code. The first bit of each frame is at zero, the next two bits identify each of the frames, 00 for the first frame, 01 for the second, and 10 for the third frame. The next 24 bits are binary data and the last bit is a parity bit that detects whether an error exists in the demodulation of the frame.
• a bit time is equal to 256 microseconds, each frame has a duration of 7.168 ms and is separated by a time of the order of 16 ms.
• step E200 the processor 100 detects an interrupt generated by the frame input module 108 and increments a variable Intc by one unit.
• step E201 the processor 100 checks whether the value of the counter NOVFLW is zero or equal to one.
• step E202 If the value of the counter NOVFLW is zero or equal to one, the processor 10 proceeds to step E202. If the value of the counter NOVFLW is equal to or greater than 2, the processor 100 proceeds to step E212. If the value of the counter NOVFLW is equal to or greater than 2, the time between the two interrupts is greater than the maximum duration between two interrupts generated by the data coded according to the Manchester code.
• step E202 the processor 100 sets the variable CPT2 to the value of the counter TC.
• NOVFLW is the value of the NOVFLW counter
• FFFF is expressed in hexadecimal
• CPT1 is a variable. This calculation makes it possible to take into account the actual duration between the two interrupts taking into account the cyclic counting of the counter TC. It should be noted here that the counter Ext is completely asynchronous, the exceeding of the first counter TC can potentially be reached between two.
• the processor 100 sets the value of the variable CPT1 to the value of CPT2.
• variable CPT1 The value of the variable CPT1 will be, at the next execution of the present algorithm, representative of the moment when the previous interruption was detected.
• the processor 100 checks whether the counter Ext is at zero. If the Ext counter is at zero, the maximum time allocated for communication has been reached.
• step E210 If the counter Ext is at zero, the processor 100 proceeds to step E210. If not, the processor 100 proceeds to step E206.
• step E206 the processor 100 checks whether the variable Intc is greater than unity.
• variable Intc is greater than unity, at least two interrupts have been detected, it is then possible to determine the time between these two interruptions, the value of DT is correct, the processor 100 goes to step E207. If the variable Intc is equal to the unit, a single interrupt has been detected, the value of DT is incorrect because the value of the variable CPT1 used in the calculation in step E203 is not representative of a previous rising edge or interrupt, it is then not possible to determine the time between these two interruptions, the processor 100 goes to step E240 of FIG. 2c.
• step E207 the processor 100 increments the Bitindex variable by one.
• the bitindex variable varies between 0 and 27 and is representative of the number of bits of a demodulated frame.
• the processor 100 checks whether the variable DT is between 3/4 of T BIT and 5/4 of T BIT , where T BIT is the duration of one bit of the received frame.
• the duration between two falling edges is equal to a bit time or 1.5 bit time or two bit times depending on the consecutive bit values.
• processor 100 proceeds to step E209. If not, processor 100 proceeds to step E220 of FIG. 2b.
• step E209 the processor 100 sets the variable Cbit to the value of the variable
• the processor 100 stores the torque Cbit and Bitindex.
• step E210 the processor 100 interrupts the demodulation.
• the countdown between the predetermined value and the null value is greater than the maximum time for receiving three frames.
• the Ext counter reaches zero, at least one of the three frames has not been received.
• the processor 100 resets the counter NOVFLW to zero. Indeed, at least one bit has been correctly demodulated.
• the next interrupt is waited for in order to restart the algorithm in order to decode at least one new binary value of the current frame.
• step E212 the processor 100 resets all the variables used in the present algorithm and proceeds to the next step E211 already described.
• step E220 of FIG. 2b the processor 100 checks whether the variable DT is between 5/4 of T B n and 7/4 of T Bn -.
• step E22 If the variable DT is between 5/4 of T B n and 7/4 of T B n, the processor 100 proceeds to step E221. If not, the processor 100 proceeds to step E230 of the
• step E221 the processor 100 checks whether the value of the variable Pbit is zero.
• the duration between two falling edges is equal to 1.5 bit duration
• the duration is representative of the bit sequence 01 or 110.
• step E222 If the value of the variable Pbit is zero, the processor 100 proceeds to step E222.
• step E222 the processor 100 sets the CBit variable to the value 1.
• the processor 100 stores the torque Cbit and Bitindex and proceeds to the step E240 of FIG. 2c.
• step E223 the processor 100 sets the variable Cbit to the value 1.
• the processor 100 sets the Nbit variable to zero.
• the value of the Nbit variable is the bit value of the bit following the Cbit bit in the frame being decoded.
• the processor 100 increments the Bitindex variable by one unit and stores the torque Nbit and Bitindex and the value of Cbit.
• the processor 100 then proceeds to step E240 of FIG. 2c.
• step E230 of FIG. 2c the processor 100 checks whether the variable DT is between 7/4 of T B rr and 9/4 of ⁇ ⁇ ⁇ ⁇
• processor 100 proceeds to step E231. If not, processor 100 proceeds to step E235 of FIG. 2c.
• step E231 the processor 100 checks whether the value of the variable Pbit is zero.
• the duration between two falling edges is equal to 2 bit times, the duration is representative of the bit sequence 010.
• step E232 If the value of the variable Pbit is zero, the processor 100 proceeds to step E232. If not, the processor 100 proceeds to step E235.
• step E232 the processor 100 sets the variable Cbit to the value 1.
• the processor 100 stores the pair Cbit and Bitindex.
• the processor 100 sets the value of the variable Pbit to zero.
• the processor 100 sets the variable Nbit to zero.
• step E234 the processor 100 increments the Bitindex variable by one unit and stores the torque Nbit and Bitindex.
• step E235 the processor 100 resets all the variables used in the present algorithm and proceeds to the next step E240.
• step E240 the processor 100 checks whether the value of the bitindex variable is equal to 27.
• step E241 If the value of the Bitindex variable is equal to 27, the processor 100 proceeds to step E241. If not, the processor proceeds to step E244.
• step E241 the processor 100 interrupts the demodulation.
• the processor 100 sets the Bitindex variable to zero.
• step E243 the processor 100 notifies the control device that the frame has been correctly decoded and transfers, to the control device, the table consisting of all the values of the stored pairs Nbit and Bitindex.
• the table includes all the demodulated bit values of a frame as well as the value of a frame counter representative of the number of tables transferred since the previous reset of the present algorithm.
• a new table similar to that transferred to the control device is initialized and the frame counter is incremented.
• step E244 the processor 100 resets the counter NOVFLW to 0.
• Fig. 3a shows a first example of a portion of a bit frame received by the frame demodulation device according to the present invention.
• a reduced sequence of seven bits is shown for the sake of simplification.
• a frame is composed of a 28-bit binary sequence.
• the binary sequence 0100110 is modulated with the Manchester code.
• an interrupt is triggered by the frame input module 108.
• the interrupts are denoted IT1, IT2, IT3, IT4 and IT5.
• the processor 100 determines the time between each interrupt and correctly demodulates the Manchester coded bit sequence as a function of time determined as described with reference to Figs. 2a to 2c.
• Fig. 3b is a second example of a portion of a bit frame received by the frame demodulation device according to the present invention.
• the received frame comprises the binary sequence 0100110 modulated according to the Manchester code and a parasitic pulse.
• an interrupt is triggered by the frame input module 108.
• the processor 100 determines the time interval ⁇ between the interrupts ⁇ and IT'2.
• the time interval T '1 is less than 3 / 4T BIT , the tests E208, E220 and E235 are negative and the processor 100 resets in step E235.
• the processor 100 determines the time between each interrupt IT "1, IT" 2, IT “3 and IT” 4 and decodes the Manchester coded bit sequence 00110.
• the processor 100 determines the time between the IT interrupt "4 and the first interrupt triggered upon receipt of the next frame." The determined time is greater than 9 / 4T BIT , the tests E208, E220 and E235 are negative and the processor 100 resets in step E235.
• the processor 100 resets in step E212.

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