EP2894665B1 - Herstellungsverfahren einer mikroelektronischen Vorrichtung - Google Patents

Herstellungsverfahren einer mikroelektronischen Vorrichtung Download PDF

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EP2894665B1
EP2894665B1 EP15150205.1A EP15150205A EP2894665B1 EP 2894665 B1 EP2894665 B1 EP 2894665B1 EP 15150205 A EP15150205 A EP 15150205A EP 2894665 B1 EP2894665 B1 EP 2894665B1
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Prior art keywords
layer
metal layer
forming
layers
sacrificial
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French (fr)
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EP2894665A1 (de
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Claire Fournier
Frédéric-Xavier Gaillard
Fabrice Nemouchi
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Commissariat a lEnergie Atomique et aux Energies Alternatives CEA
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Commissariat a lEnergie Atomique CEA
Commissariat a lEnergie Atomique et aux Energies Alternatives CEA
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials

Definitions

  • the present invention relates to a method for manufacturing microelectronic devices of different types on the same plate and, more particularly, to a method for forming identical or different metal layers and thus contact layers of said microelectronic devices different by making the contact layers more homogeneous and uniform in terms, for example, of thickness, composition, and roughness, etc.
  • CMOS complementary Metal Oxide Semiconductor
  • the performance of microelectronic devices CMOS is closely related to the reduction of the resistance of electrical contacts.
  • the improvement of the self-aligned silicidation process is one of the key points to achieve the characteristics required for the future technological node.
  • the silicidation process is in fact a reaction between a metal layer and a semiconductor layer making it possible to limit the resistance to access the source and drain of a transistor.
  • the material of the metal layer can be chosen from metals and alloys such as a nickel-based alloy.
  • the metal layer allowing the siliciding reaction is generally produced by physical vapor deposition (PVD, acronym for “physical vapor deposition”) on the entire continuous upper surface of the support wafer. devices to be manufactured. Then, under the effect of a heat treatment, the metal layer reacts preferentially with semiconductor zones rather than with dielectric ones. At this stage, the annealing for the formation of a silicide layer is carried out.
  • PVD physical vapor deposition
  • Selective removal is then preferably performed chemically to remove the portion of the unreacted metal layer.
  • a new heat treatment is carried out in order to directly obtain a layer of an intermetallic compound or of a solid solution, which is the most interesting phase from a metallurgical and electrical point of view.
  • Another solution proposes a method of forming a metal layer by the chemical route and more particularly by the autocatalytic method without input of current (from the English “electroless deposition”). also called the unassisted electrochemical route, instead of the PVD process.
  • This process makes it possible to deposit a metallic layer (or a layer of an alloying material) at low cost on the top surface of the wafer or within complex structures. Moreover, this process makes it possible, under certain specific conditions, to deposit not one metal layer but two different metal layers selectively depending on the substrate used.
  • the present invention makes it possible to remedy all or part of the drawbacks of currently known techniques.
  • the invention relates to a method of manufacturing a microelectronic device according to claim 1.
  • This method comprises, on the basis of a substrate, forming a first layer of a first semiconductor material on a first region of a top surface of the substrate; forming a second layer of a second semiconductor material, on a second zone, distinct from the first zone, of the upper surface of the substrate; forming a first metal layer on top of the first layer; forming a first contact layer of a first intermetallic compound or solid solution comprising at least a portion of the first layer and at least a portion of the first metallic layer; forming a first sacrificial layer by oxidation of an upper portion of the first contact layer, and a second sacrificial layer by oxidation of an upper portion of the second layer; performing a removal of all of the second sacrificial layer so as to expose a residual portion of the second layer and partial removal of the first sacrificial layer; forming a second metallic layer over said residual portion; forming a
  • a potential advantage of the invention is to alleviate at least in part the problems mentioned above by depositing two identical or different metal layers and by uniformizing the layers of different semiconductor materials on the same wafer; for example, to form two p-type CMOS transistors and of type n, the invention allowing an advantageous advantage of depositing two different metal layers of which the difference between the value of the valence band for a p-type semiconductor and the value of the output work of the silicide is less than half a gap (or "half band gap") of this same semiconductor or of which the difference between the value of the output work of the silicide and the value of the conduction band for an n-type semiconductor is less than half a gap of this same semiconductor.
  • the invention relates to the manufacture of any device such as in particular those indicated above. These fabrications involve substrates defined here as structures with at least one layer of material, very advantageously of the semiconductor type, and forming a stack or even a wafer of semiconductor material (s).
  • the substrate can form all or part of the final microelectronic device or be an intermediate element at least partially removed during manufacture, for example by serving as a support or handle for the production and / or transfer of functional layers.
  • upper surface of the substrate is meant a portion of the substrate exposed to the outside and typically one of the two faces delimiting the thickness of the substrate.
  • the upper surface is advantageously non-planar due to the presence of parts of devices or even of masks, for example.
  • a portion or area of the upper surface may therefore be recessed or protruding relative to other portions or areas of the upper surface.
  • the term “thickness” is used to define a dimension in the direction of the stacks of the layers of the manufactured device.
  • width is used to describe a dimension oriented transversely to the thickness.
  • the figures 1a and 1b summarize steps 210 to 300 for manufacturing microelectronic devices according to the method of the invention.
  • the figures 2a to 2i illustrate the main steps 210 to 300 of manufacturing transistors of two different types on the same plate, also called a substrate according to a first embodiment of the invention.
  • Two transistors 101 and 102 respectively of the NMOS type and of the PMOS type, will be illustrated in the figures 2a to 2i in order to facilitate understanding.
  • the invention is not limited to the number of transistors illustrated and some of the layers mentioned below may not be present or other layers may be added without thereby departing from the scope of the present invention.
  • the figure 2a shows the starting structure of a substrate 112 according to a first embodiment of the invention.
  • Integrated circuits such as transistors 101, 102 can be made from a starting substrate, very generally made of solid silicon and often referred to as “bulk” or an elaborate substrate of the so-called SOI type, acronym.
  • SOI semiconductor on insulator
  • the SOI type substrate 112 comprising an initial substrate 113 surmounted by an insulating layer 114 and a surface layer 146.
  • the initial substrate 113 is most often a homogeneous wafer of silicon.
  • the insulating layer 114 is preferably a buried oxide layer 114 which insulates the components which will be manufactured in the thin surface layer 146 of semiconductor present on the buried layer 114.
  • the surface layer 146 is most often made up of monocrystalline silicon.
  • the insulation of the transistors 101, 102 is completed by the production of lateral insulation trenches called STI 239, acronym for “shallow trench insulation”, that is to say “shallow insulation trenches”. They reach the buried oxide layer 114 to encompass each of the transistors in a continuous oxide layer 114. These trenches, which are not necessary for understanding the invention, are not shown in detail.
  • a stack of grids 160a, formed on the surface layer 146, comprises at least one grid 124a, a hard mask (not shown in the figures) covering the upper surface of the grid 124a and spacers 410a covering the sides of the grid 124a.
  • a stack of grids 160b, also formed on the surface layer 146, comprises at least one grid 124b, a hard mask (not illustrated in the figures) covering the upper surface of the grid 124b and spacers 410b covering the sides of the grid 124b.
  • Said hard masks are configured to protect the gates 124a, 124b during the formation of sources and drains such as layers 201, 202 (illustrated later) by epitaxy or the implantation of the n and p junctions.
  • Said Hard masks are also used when performing step 230 (illustrated later) of forming an intermediate coating 205.
  • the material of the grid 124a may be different from that of the grid 124b.
  • the material of the spacers 410a may also be different from that of the spacers 410b.
  • the invention is not limited to the previous examples of the preparation of the substrate 112, of the STIs 239, of the formation of the grid stacks 160a, 160b and of the preparation of the upper surface of the surface layer 146 of the substrate 112.
  • the figure 2b shows the structure obtained at the end of step 210 of forming a first layer 201 of a first semiconductor material and of a second layer 202 of a second semiconductor material, respectively on a first zone for transistor 101 and a second zone for transistor 102.
  • step 210 consists first of depositing a mask (not illustrated in figure 2b ) and then forming the first layer 201 on the first area of the upper surface of the substrate 112 outside the stack of grids 160a.
  • a mask not illustrated in figure 2b
  • step 210 consists first of depositing a mask (not illustrated in figure 2b ) and then forming the first layer 201 on the first area of the upper surface of the substrate 112 outside the stack of grids 160a.
  • the term “zone” can be applied to any part of the surface of all shapes and sizes suitable for the application. It can be in one or more spaced portions.
  • a mask is preferably deposited outside the first zone of the upper surface of the substrate 112 so that the first layer 201 is formed only in the first zone of the upper surface of the substrate 112. More precisely, the mask is preferably deposited on a second zone of the upper surface of the substrate 112 to completely cover and thus protect the stack of gates 160b and the second zone of the upper surface of the surface layer 146.
  • the material of the mask is for example SiO 2 .
  • the formation of the first layer 201 is then carried out on the first zone by a method such as the selective epitaxy of the first semiconductor material.
  • This first layer 201 is intended to participate in the formation of a first contact layer 281 (described later).
  • This first semiconductor material is advantageously different from a second semiconductor material used to subsequently form another contact layer 282 (described later).
  • the first layer 201 is composed either of n-type silicon (Si) or of a solid solution containing carbon (C), a second layer 202 being composed of Si p-type or SiGe.
  • the first layer 201 is composed of p-type Si or SiGe, the second layer 202 being composed of n-type Si or a solution of Si containing carbon.
  • the invention is not limited to the order in which the layers 201 and 202 are produced, nor to the examples above.
  • the first and second semiconductor materials can be identical or different depending on the production methods of the layers 201 and 202 or / and the functions of the transistors 101 and 102.
  • At least one of the first and second semiconductor materials is chosen from the following materials: silicon, a solid solution of silicon containing carbon, germanium, silicon-germanium, materials composed of elements from columns III and / or V of the periodic table of the elements of the elements, as required.
  • the first layer 201 is formed on either side of the stack of gates 160a on the first zone of the substrate 112.
  • the thickness of the first layer 201 is from 5 to 20 nm. (nanometers).
  • the mask is then removed after the formation of the first layer 201.
  • the second layer 202 can be produced in the same way as the first layer 201 is formed.
  • Step 210 therefore consists in then depositing a mask (not illustrated in figure 2b ) and forming the second layer 202 on the second area of the upper surface of the substrate 112 outside the stack of grids 160b.
  • a mask is preferably deposited outside the second zone of the upper surface of the substrate 112 so that the second layer 202 is formed only in the second zone of the upper surface of the substrate 112. More specifically, the mask is preferably deposited on a first zone of the upper surface of the substrate 112 to completely cover and thus protect the stack of gates 160a and the first zone of the upper surface of the surface layer 146.
  • the material of the mask is for example SiO 2 .
  • the formation of the second layer 202 is then carried out in such a way that the selective epitaxy of the second semiconductor material.
  • the second semiconductor material is advantageously different than the first semiconductor material.
  • the second layer 202 is formed on either side of the stack of grids 160b on the second region of the substrate 112.
  • the thickness of the second layer 202 is from 5 to 20 nm. .
  • the mask is removed after the formation of the second layer 202.
  • the invention is not limited to the production of masks or to the embodiments of the first and second layers 201 and 202.
  • the figure 2c shows the structure obtained at the end of step 240 of forming a metal layer 207a for transistor 101.
  • step 240 a step 230 of preparing the upper surfaces of the first and second layers 201 and / or 202 is performed before step 240.
  • step 230 is optional depending on the nature of the first material and the types of devices to be produced.
  • An example of the performance of step 230 composed of four steps 310 to 340 will be illustrated below.
  • the invention is not limited to the embodiments of optional step 230; that is, step 230 does not necessarily include all four steps 310 to 340 and could be performed otherwise.
  • Step 310 consists in cleaning the upper surface of the structure obtained after carrying out step 220 comprising the upper surfaces of the first and second layers 201 and / or 202.
  • a cleaning solution for example of hydrofluoric acid, is used at this step.
  • Step 320 of sensitizing the upper surfaces of the first and second layers 201 and / or 202 is carried out using a sensitization solution, for example an acid solution of tin salt.
  • This sensitizing solution can also contain an additive modifying the adsorption properties of tin ions.
  • composition of the sensitizing solution is described in the table below: Aqueous solution SnCl 2 (tin (II) chloride), 2H 2 O HCI (hydrogen chloride) H 2 O 2.26 g (gram) 0.8 ml (milliliter) 100 ml
  • Step 330 of activating the upper surfaces of the first layer 201 and / or of the second layer 202 is then carried out using an activation solution, for example of palladium.
  • the composition of the activation solution can be varied and adapted according to the nature of a first semiconductor material to be used.
  • the selectivity of a deposition of a metallic layer formed subsequently can be adjusted via an activation bath used. at this stage, either by modifying the composition of the bath, or by modifying the concentrations of the reagents.
  • activation solutions that can be used to prepare the upper surfaces of the first and second layers 201 and / or 202 for nickel deposition.
  • Three examples of the formation of the composition of the activation solution are described in the three tables below to explain in which cases the activation solutions are used according to their activation properties on various materials:
  • the activation solution is advantageously configured to activate the zones of the upper surface of one of the first and second layers 201 and 202 on which two metal layers 207a, 207b are to be formed, and, preferably not to activate zones such as the dielectric parts and the upper surface of the other of the layers 201, 202. This allows the formation of the first and second metal layers 207a, 207b to be made selective. Then, step 340 of post-activation rinsing of the upper surfaces of the first and / or second layers 201 and / or 202 is carried out.
  • This step 340 can be carried out in different ways such as an EDI rinsing (short for “Electrodesionization”) only, an EDI rinsing under ultrasound, or a rinsing carried out in successive baths of EDI / HF / EDI.
  • This step 340 makes it possible to optimize the performance of the next step 240 comprising for example a deposition of nickel (Ni) by an unassisted electrochemical route and this as a function of the integration and of the substrate.
  • the step 240 of forming a first metal layer 207a for the transistor 101 is performed.
  • This step 240 consists in forming the first metal layer 207a above the first layer 201, in a preferential but nonlimiting manner, by unassisted electrochemical means (standing for “electroless deposition”).
  • a solution used in a bath containing, for example, a metal salt, a reducing agent, a complexing agent and a stabilizer is employed in order to carry out a chemical reaction to then form the first metal layer 207a.
  • the first metal layer 207a of material based on nickel (Ni) is obtained at the end of the production of a nickel bath by unassisted electrochemical means using a solution such as a commercial solution comprising a salt. metal, a reducing agent, a complexing agent and a stabilizer.
  • a deposit of a nickel alloy based on rare earths will advantageously be used in weight proportions preferably between 0-20%.
  • the conditions for making a bath such as temperature and pH, depend on the factors of the commercial solution or the formulated solution such as composition of the bath, the concentrations of the various constituents of the bath, etc. Let us take the example above, the chemical reaction is carried out between 60 and 80 ° C according to the substrates 112 employed and preferably between 70 and 75 ° C.
  • the material of the first metallic layer 207a can be a metal or an alloy, depending on the chosen solution to be applied.
  • the thickness of the first metal layer 207a is determined as a function of that of the first layer 201. More precisely, the thickness of the first metal layer 207a should be less than that of the first layer 201.
  • the thickness of the first metal layer 207a is preferably greater than a threshold thickness (i.e. between 1 to 20 nm).
  • one possibility is to calculate the volume V at i of an atom of the material for each layer i such as an upper portion (RI) of the first layer 201 intended to make reacting with the first metal layer 207a, the first metal layer (CM) 207a, and the first contact layer (CC) 281 (formed subsequently in step 250).
  • the values V at i for the three layers above are therefore respectively represented as V at RI , V at CM , V at CC .
  • the values V at RI , V at CM , V at CC can be obtained and, consequently, said threshold thickness of the first metal layer 207a can be obtained by calculating the volume ratio such as V at CM / V at RI presented in the table below: RI (top portion (RI) of the first layer 201) + CM (first metallic layer 207a) ⁇ CC (first contact layer 281) V at RI V at CM V at CC 1 V at CM / V at RI V at CC / V at RI
  • the table below shows more examples in figures if the first semiconductor material of the first layer 201 is silicon: RI (top portion (RI) of the first layer 201) CM (first metallic layer 207a) CC (first contact layer 281) / silicide formed Yes Or NiSi 1 0.55 1.2 2 If Or NiSi 2 1 0.27 1.97 Yes 2 Pd Pd 2 Si 1 1.47 1.76 Yes Pt PtSi 1 0.74 1.47 Yes 2 Co Co 2 Si 1 1.1 1.61 2If Ti TiSi 2 2.24 0.45 1.11
  • the table below shows examples in figures if the first semiconductor material of the first layer 201 is germanium: RI (top portion (RI) of the first layer 201) CM (first metallic layer 207a) CC (first contact layer 281) / Germaniide formed Ge Or NiGe 1 0.46 0.41 Ge 2 Ni Ni 2 Ge 1 0.97 0.62 Ge Pd Ceo 1 0.65 0.43 Ge Pt PtGe 1 0.67 0.45
  • Fluid application begins with acid and ends with deionized water (EDI) or H 2 O water.
  • EDI deionized water
  • Aqueous solution HF 1% Sn 2+ H 2 O Pd 2+ H 2 O HF0.1% H 2 O Neither 2+ H 2 O Duration (seconds) 10 600 10 30 10 10 10 10 20 10 Temperature (° C) Ambient temperature (TA) YOUR YOUR YOUR YOUR YOUR YOUR YOUR YOUR 75 YOUR
  • the third example is a first example.
  • this step 340 several functions, such as the elimination of the residues of the solution used (ie the first example), the elimination of the palladium (ie the second example) on the silicon oxide (SiO x ) or silicon nitride (Si X N Y ) to obtain nickel deposition only on semiconductor substrates (Si, SiGe), and improving the quality such as lower thickness and roughness of the first metallic layer 207a formed subsequently (by deposition of nickel for example), are obtained according to different embodiments.
  • the first metallic layer 207a is therefore formed by selective deposition outside zones comprising dielectric zones of the upper surface of the substrate 112 and the second layer 202 of the second semiconductor material; more precisely, the first metal layer 207a is positioned above the first layer 201 of the first semiconductor material and formed around the stack of gates 160a and not on the second layer 202 and dielectric elements such as STIs 239, the spacers 410a, 410b and the hard masks covering the grids 124a, 124b.
  • the selectivity depends on the Pd solution used and / or the associated rinsing such as the three rinses mentioned above in the description concerning step 340.
  • the stacks of grids 160a, 160b are preferably not covered by the first metallic layer 207a, which makes it possible to reduce the amount of material of the lost metallic layer compared to a known method.
  • the grid stacks are completely covered by a metal layer.
  • the parts of the metal layer covering the stacks of grids will not react with dielectric zones such as the spacers 410a, 410b and the hard masks (not shown in the figures). respectively covering the upper surfaces of the grids 124a, 124b; that is, said parts of the metal layer are unwanted and will be lost, which will result in unnecessary consumption of the material of the metal layers during the annealing step.
  • the manufacturing sequence of the devices is simplified because the method of the invention no longer systematically requires removing said parts of the metallic layer which have not reacted.
  • the invention is not limited to the materials or to the method of making the first metal layer 207a.
  • the figure 2d shows the structure obtained at the end of step 250 of forming a first contact layer 281 for transistor 101.
  • This contact layer 281 generally forms portions of devices, advantageously serving for electrical conduction, from of the method of the invention.
  • Step 250 consists in preferentially carrying out a heat treatment so as to form the first contact layer 281 of a first intermetallic compound or solid solution, composed of the following two materials: the material of the first metallic layer 207a and of the first semi-metallic material. -conductor of at least an upper portion of the first layer 201.
  • the parameters of this annealing are determined according to the first semiconductor material and / or the material of the first metal layer 207a used.
  • the first intermetallic compound or solid solution obtained can be either an intermetallic compound (between a metal and a semiconductor material) or a metal / semiconductor alloy. It can typically be a silicidation when the first semiconductor material is or comprises silicon.
  • the heat treatment is carried out for example at a temperature 150 ° C to 500 ° C for 10 to 120 seconds to cause a siliciding reaction and thereby obtain the first intermetallic compound or solid solution.
  • the invention is not limited to the method of making the first contact layer 281.
  • the figure 2e shows the structure obtained at the end of step 260 of forming the first and second sacrificial layers 271a, 271b by oxidation.
  • This step 260 consists in preferentially carrying out a heat treatment in order to oxidize respectively an upper portion of the first contact layer 281 and an upper portion of the second layer 202, so as to respectively form the first sacrificial layer 271a with a thickness e 1 and the second sacrificial layer 271b with a thickness e 2 .
  • the parameters of this annealing are determined according to several factors, such as the rate of oxidation of the first contact layer 281 and that of the second layer 202, the material obtained from the first contact layer 281 and / or the second semi material. -conductor of the second layer 202, etc.
  • the rate of oxidation of the first contact layer 281 must be faster than that of the second layer 202, in order to form the thickness e 1 which is greater than the thickness e 2 .
  • the thickness e 2 of the second sacrificial layer 271b can be very thin compared to the thickness e 1 of the first sacrificial layer 271a, which is for example at least twice that of e 2
  • the thicknesses e 1 and e 2 obtained at the end of the heat treatment depend on the duration of the heat treatment and / or on the applied temperature and / or on the applied pressure. Two examples are described below.
  • the first contact layer 281 is made of NiSi 2 and the second layer 202 is made of silicon.
  • the oxidation of silicide ie NiSi 2
  • Silicide is faster than that of silicon carried out at the same temperature and in the same duration of the heat treatment.
  • the heat treatment is carried out for example at a temperature between 800 ° C and 1200 ° C and preferably between 700 ° C and 900 ° C. In one example, the heat treatment is carried out at 700 ° C. for 20 hours so as to form the first and second sacrificial layers 271a and 271b respectively having a thickness of 50 nm and that of 17 nm.
  • the first contact layer 281 is in CoSi 2 and the second layer 202 is in silicon.
  • the oxidation rate of CoSi 2 is about twice that of Si under the same pressure.
  • a heat treatment is carried out for example under 1 Torr for one hour so as to form the first and second sacrificial layers 271a and 271b respectively having a thickness of 36 nm and 18 nm.
  • the thickness of a residual portion of the second layer 202 is effectively less than the thickness of the second layer 202 obtained at the end of step 220.
  • Step 270 consisting in completely removing the second sacrificial layer 271b and partially removing the first sacrificial layer 271a is then carried out so as to expose the residual portion of the second layer 202.
  • an upper surface of the residual portion of the second layer 202 is thus exposed while keeping in place a residual thickness of the first sacrificial layer 271a, as illustrated in figure 2f .
  • the upper surface of said residual portion is therefore ready for carrying out the next step 280 (described later) of forming a second metal layer 207b.
  • the two sacrificial layers 271a and 271b are removed by chemical attack such as etching diluted with hydrofluoric acid (HF) or etching with diverted plasma (NF 3 , NH 3 ).
  • chemical attack such as etching diluted with hydrofluoric acid (HF) or etching with diverted plasma (NF 3 , NH 3 ).
  • step 270 that is to say the preservation of a part of residual portion of the first sacrificial layer 271a.
  • the thickness e 1 of the first sacrificial layer 271a obtained at the end of step 260 is greater than the thickness e 2 of the second sacrificial layer 271b obtained. In this case, if the chemical attack of the two sacrificial layers 271a and 271b has the same kinetics, this difference in thickness ensures a partial removal for the thickness e 1 and total for the thickness e 2 .
  • the invention is not limited to the above method of removing the first and second sacrificial layers 271a and 271b.
  • the figure 2g shows the structure obtained at the end of step 280 of forming a second metallic layer 207b for the transistor 102.
  • This step 280 consists in forming the second metallic layer 207b above said residual portion of the second layer 202 , in a preferential but nonlimiting manner, by unassisted electrochemical route (from the English “electroless deposition”). More specifically, at this stage there is effectively a single semi-conductor zone exposed on the wafer, namely the second layer 202.
  • the step 280 of forming the second metal layer 207b can therefore be considered as carried out in a “self-selective” manner. ".
  • the second metallic layer 207b is produced in a non-selective manner, for example by PVD, over the entire continuous upper surface of the wafer. As described later, there is then a step of partial removal of this deposit.
  • the second metallic layer 207b is formed by selective deposition outside zones comprising dielectric zones of the upper surface of the substrate 112 and those of the first sacrificial layer 271a; more specifically, the second metal layer 207b is positioned above the second layer 202 of the second semiconductor material and formed around the stack of gates 160b instead of on dielectric elements such as STIs 239, spacers 410a , 410b, the hard masks covering the grids 124a, 124b and the first sacrificial layer 271a.
  • dielectric elements such as STIs 239, spacers 410a , 410b, the hard masks covering the grids 124a, 124b and the first sacrificial layer 271a.
  • the thickness of the second metal layer 207b is determined as a function of that of the second layer 202. More precisely, the thickness of the second metal layer 207b should be sufficiently less than that of the second layer 202.
  • the thickness of the second metal layer 207b is preferably greater than a threshold thickness (i.e. between 1 to 20 nm).
  • one possibility is to calculate the volume V at i of an atom of the material for each layer i such as an upper portion (RI) of the second layer 202, the second metal layer (CM) 207b, the second contact layer (CC) 282 (formed later in step 290).
  • the values V at i for the three layers above are therefore respectively represented as V at RI , V at CM , V at CC .
  • the detailed description of the threshold thickness of the second metal layer 207b is similar to that of the threshold thickness of the first metal layer 207a as previously described and it is therefore possible here to adapt to an equivalent calculation.
  • the output work of the silicide will be adjusted by advantageously adding to the second metal layer 207b palladium or platinum for the second p-type layer 202 in a concentration range 0 -20%.
  • first metallic layer 207a and the second metallic layer 207b can be made of different or identical materials, which depends on the characteristics (such as the conductivity) of the transistors 101, 102 desired.
  • the figure 2h shows the structure obtained at the end of step 290 of forming a second contact layer 282 for transistor 102.
  • This contact layer 282 generally forms portions of devices, advantageously serving for electrical conduction.
  • Step 290 consists in preferentially carrying out a heat treatment so as to form the second contact layer 282 of a second intermetallic compound or solid solution composed of the following two materials: the material of the second metallic layer 207b and the second semi-metallic material. conductor of an upper portion of said residual portion of the second layer 202.
  • step 250 The description of the parameters of the annealing carried out in step 250 is valid for carrying out an annealing carried out in this step 290 so as to form the second contact layer 282.
  • Step 295 is an optional step performed in an embodiment where the second metal layer 207b is formed in step 280 in a non-selective manner. This step 295 consists in removing residual portions of the second metal layer 207b and / or portions of the second contact layer 282 which are located outside the second zone; that is to say, removing the portions of the second contact layer 282 located above the STIs 239 and of the first sacrificial layer 271a.
  • the invention is not limited to the above method of removing portions of second contact layer 282 and residual portions of second metal layer 207b.
  • Step 300 consisting in completely removing the first sacrificial layer 271a is then carried out so as to expose the first contact layer 281, as illustrated in figure 2i .
  • the first sacrificial layer 271a is removed by chemical attack such as etching diluted with hydrofluoric acid (HF) or by etching with diverted plasma (NF 3 , NH 3 ).
  • chemical attack such as etching diluted with hydrofluoric acid (HF) or by etching with diverted plasma (NF 3 , NH 3 ).
  • III-V refers, as mentioned above, to materials comprising at least one element belonging to the elements of columns III and V of the Periodic Table of the Elements.

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  • Engineering & Computer Science (AREA)
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  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Claims (16)

  1. Herstellungsverfahren einer mikroelektronischen Vorrichtung, umfassend, auf der Basis eines Substrats (112):
    - ein Bilden einer ersten Schicht (201) eines ersten Halbleitermaterials auf einem ersten Bereich einer oberen Oberfläche des Substrats (112);
    - ein Bilden einer zweiten Schicht (202) eines zweiten Halbleitermaterials auf einem zweiten Bereich, verschieden von dem ersten Bereich, der oberen Oberfläche des Substrats (112);
    beinhaltend, nach dem Bilden der zweiten Schicht (202):
    - ein Bilden einer ersten metallischen Schicht (207a) über der ersten Schicht (201);
    - ein Bilden einer ersten Kontaktschicht (281) aus einer ersten intermetallischen Verbindung oder festen Lösung, beinhaltend mindestens einen Abschnitt der ersten Schicht (201) und mindestens einen Abschnitt der ersten metallischen Schicht (207a);
    - ein Bilden einer zweiten metallischen Schicht (207b) über der zweiten Schicht (202);
    - das Bilden einer zweiten Kontaktschicht (282) aus einer zweiten intermetallischen Verbindung oder festen Lösung, beinhaltend mindestens einen Abschnitt des verbleibenden Abschnitts und mindestens einen Abschnitt der zweiten metallischen Schicht (207b);
    wobei das Verfahren dadurch gekennzeichnet ist, dass es zwischen dem Bilden der ersten Kontaktschicht (281) und dem Bilden der zweiten metallischen Schicht (207b) beinhaltet:
    - ein Bilden einer ersten Opferschicht (271a) durch Oxidation eines Abschnitts eines oberen Abschnitts der ersten Kontaktschicht (281), und einer zweiten Opferschicht (271b) durch Oxidation eines oberen Abschnitts der zweiten Schicht (202), wobei die Dicke e1 der ersten Opferschicht (271a) größer ist als die Dicke e2 der zweiten Opferschicht (271b);
    - die Durchführung eines Entfernens der Gesamtheit der zweiten Opferschicht (271b), sodass ein verbleibender Abschnitt der zweiten Schicht (202) freigelegt wird, und eines teilweisen Entfernens der ersten Opferschicht (271a);
    und dadurch, dass die zweite metallische Schicht (207b) über dem verbleibenden Abschnitt der zweiten Schicht (202) gebildet wird.
  2. Verfahren nach dem vorstehenden Anspruch, wobei das Bilden der ersten und zweiten Opferschicht (271a, 271b) die Durchführung einer thermischen Behandlung beinhaltet.
  3. Verfahren nach dem vorstehenden Anspruch, wobei die thermische Behandlung während einer Dauer von 2 bis 100 Stunden und bei einer Temperatur zwischen 700 Grad (°C) und 1200 °C durchgeführt wird, sodass die erste und zweite Opferschicht (271a, 271b) gebildet werden.
  4. Verfahren nach einem der vorstehenden Ansprüche, beinhaltend, nach dem Bilden der zweiten Kontaktschicht (282), die Durchführung einer Gesamtentfernung der ersten Opferschicht (271a).
  5. Verfahren nach einem der vorstehenden Ansprüche 1 bis 4, wobei die erste und zweite Opferschicht (271a, 271b) durch chemischen Angriff entfernt werden.
  6. Verfahren nach einem der vorstehenden Ansprüche, wobei die Bildungen der ersten und zweiten Kontaktschicht (281, 282) die Durchführung einer thermischen Behandlung beinhalten.
  7. Verfahren nach dem vorstehenden Anspruch, wobei die thermische Behandlung während einer Dauer von 10 bis 600 Sekunden und bei einer Temperatur zwischen 150°C und 500°C durchgeführt wird, sodass die erste und zweite Kontaktschicht (281, 282) gebildet werden.
  8. Verfahren nach einem der vorstehenden Ansprüche 1 bis 7, wobei die erste metallische Schicht (207a) und die zweite metallische Schicht (207b) aus unterschiedlichen Materialien bestehen.
  9. Verfahren nach einem der vorstehenden Ansprüche, wobei das erste Halbleitermaterial und das zweite Halbleitermaterial unterschiedlich sind.
  10. Verfahren nach dem vorstehenden Anspruch, wobei die erste metallische Schicht (207a) durch selektives Abscheiden außerhalb von Bereichen, die dielektrische Bereiche der oberen Oberfläche des Substrats (112) beinhalten, und der zweiten Schicht (202) des zweiten Halbleitermaterials gebildet wird.
  11. Verfahren nach einem der vorstehenden Ansprüche 9 oder 10, wobei die zweite metallische Schicht (207b) durch selektives Abscheiden außerhalb der Bereiche, die dielektrische Bereiche der oberen Oberfläche des Substrats (112) beinhalten, und jener der ersten Opferschicht (271a) gebildet wird.
  12. Verfahren nach einem der vorstehenden Ansprüche 10 oder 11, wobei mindestens eine aus der ersten und zweiten metallischen Schicht (207a, 207b) durch nicht assistierten elektrochemischen Weg gebildet werden.
  13. Verfahren nach einem der vorstehenden Ansprüche, wobei die Dicke der ersten metallischen Schicht (207a) und jene der zweiten metallischen Schicht (207b) oberhalb von 5 nm liegen.
  14. Verfahren nach einem der vorstehenden Ansprüche, wobei mindestens eins aus dem ersten und zweiten Halbleitermaterial ausgewählt wird aus den folgenden Materialien: Silicium, einer festen Lösung von Silicium, die Kohlenstoff enthält, einer festen Lösung von Silicium oder von Germanium, Germanium, Silicium-Germanium, Materialien, die aufgebaut sind aus Elementen der Gruppen III und V des Standardperiodensystems der Elemente.
  15. Verfahren nach Anspruch 14, wobei das erste und zweite Halbleitermaterial ausgewählt werden aus den folgenden Materialien: Silicium, einer festen Lösung von Silicium, die Kohlenstoff enthält, einer festen Lösung von Silicium oder von Germanium.
  16. Verfahren nach Anspruch 14, wobei das erste und zweite Halbleitermaterial ausgewählt werden aus Materialien, die aufgebaut sind aus Elementen der Gruppen III und V des Standardperiodensystems der Elemente.
EP15150205.1A 2014-01-08 2015-01-06 Herstellungsverfahren einer mikroelektronischen Vorrichtung Active EP2894665B1 (de)

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Family Cites Families (9)

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JP3116637B2 (ja) 1993-03-12 2000-12-11 株式会社村田製作所 無電解めっき液
US6844225B2 (en) 2003-01-15 2005-01-18 International Business Machines Corporation Self-aligned mask formed utilizing differential oxidation rates of materials
US20050156208A1 (en) * 2003-09-30 2005-07-21 Taiwan Semiconductor Manufacturing Company, Ltd. Device having multiple silicide types and a method for its fabrication
US6933231B1 (en) 2004-06-28 2005-08-23 Micron Technology, Inc. Methods of forming conductive interconnects, and methods of depositing nickel
US7064025B1 (en) 2004-12-02 2006-06-20 International Business Machines Corporation Method for forming self-aligned dual salicide in CMOS technologies
US7220626B2 (en) * 2005-01-28 2007-05-22 International Business Machines Corporation Structure and method for manufacturing planar strained Si/SiGe substrate with multiple orientations and different stress levels
US20090315185A1 (en) * 2008-06-20 2009-12-24 Boyan Boyanov Selective electroless metal deposition for dual salicide process
DE102009010847B4 (de) * 2009-02-27 2012-12-27 Advanced Micro Devices, Inc. Integration von Halbleiterlegierungen in PMOS- und NMOS-Transistoren unter Anwendung eines gemeinsamen Ätzprozesses für Aussparungen
US9171929B2 (en) * 2012-04-25 2015-10-27 Taiwan Semiconductor Manufacturing Company, Ltd. Strained structure of semiconductor device and method of making the strained structure

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FR3016235B1 (fr) 2016-01-22
US9379024B2 (en) 2016-06-28
US20150194349A1 (en) 2015-07-09
FR3016235A1 (fr) 2015-07-10
EP2894665A1 (de) 2015-07-15

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