EP2879186B1 - Dispositif semi-conducteur en carbure de silicium - Google Patents

Dispositif semi-conducteur en carbure de silicium Download PDF

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Publication number
EP2879186B1
EP2879186B1 EP13823273.1A EP13823273A EP2879186B1 EP 2879186 B1 EP2879186 B1 EP 2879186B1 EP 13823273 A EP13823273 A EP 13823273A EP 2879186 B1 EP2879186 B1 EP 2879186B1
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region
drift layer
silicon carbide
layer
relaxing
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EP2879186A4 (fr
EP2879186A1 (fr
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Keiji Wada
Takeyoshi Masuda
Toru Hiyoshi
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Sumitomo Electric Industries Ltd
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Sumitomo Electric Industries Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching
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    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
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    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H01L29/0623—Buried supplementary region, e.g. buried guard ring
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    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
    • H01L29/1608—Silicon carbide
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
    • H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
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    • H01L29/0692—Surface layout
    • H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
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    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
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    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/4238—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the surface lay-out

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Plasma & Fusion (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Recrystallisation Techniques (AREA)

Claims (9)

  1. Dispositif à semi-conducteur au carbure de silicium, comprenant :
    une couche de carbure de silicium (101) présentant une première surface principale (P1) et une deuxième surface principale (P2) opposée à ladite première surface principale,
    ladite couche de carbure de silicium (101) incluant
    une couche de dérive (81) constituant ladite première surface principale (P1), incluant une couche de dérive supérieure (81b) et une couche de dérive inférieure (81a) et présentant un premier type de connectivité,
    une zone de corps (82) disposée sur ladite couche de dérive (81) et présentant un deuxième type de connectivité différent dudit premier type de connectivité,
    une zone source (83) disposée sur ladite zone de corps (82) de sorte à être éloignée de ladite couche de dérive (81) par ladite zone de corps (82), constituant ladite deuxième surface principale (P2), et présentant ledit premier type de conductivité, et
    une zone de relâchement (71) partiellement disposée dans une surface de la couche de dérive inférieure (81a) et présentant ledit deuxième type de conductivité, la couche de dérive supérieure (81b) étant disposée sur la surface de la couche de dérive inférieure (81a), la couche de dérive supérieure (81b) couvrant la zone de relâchement (71),
    ladite zone de relâchement (71) présentant une dose d'impuretés Drx, et une distance Ld depuis ladite première surface principale, ladite couche de dérive présentant une concentration d'impuretés Nd entre ladite première surface principale et ladite zone de relâchement, et une relation de Drx > Ld●Nd étant satisfaite ;
    dans lequel une concentration d'impuretés de la couche de dérive inférieure (81a) est inférieure à celle de la couche de dérive supérieure (81b) ; un film d'isolation de grille (91) disposé sur ladite zone de corps de sorte à connecter ladite zone source et ladite couche de dérive l'une à l'autre ;
    une électrode de grille (92) disposée sur ledit film d'isolation de grille ;
    une première électrode (98) opposée à ladite première surface principale (P1) ; et
    une deuxième électrode (94) opposée à ladite deuxième surface principale (P2).
  2. Le dispositif à semi-conducteur au carbure de silicium selon la revendication 1, dans lequel une relation de Ld ≥ 5 µm est satisfaite.
  3. Le dispositif à semi-conducteur au carbure de silicium selon la revendication 1 ou 2, dans lequel une relation de Drx ≥ 1 x 1013 cm-2 est satisfaite.
  4. Le dispositif à semi-conducteur au carbure de silicium selon l'une quelconque des revendications 1 à 3, dans lequel une tension de rupture à l'échelle desdites première et deuxième électrodes est supérieure ou égale à 600 V.
  5. Le dispositif à semi-conducteur au carbure de silicium selon l'une quelconque des revendications 1 à 4, comprenant en outre un substrat monocristallin disposé entre ladite première surface principale de ladite couche de carbure de silicium et ladite première électrode, étant en contact avec chacune de ladite première surface principale de ladite couche de carbure de silicium et ladite première électrode, composé de carbure de silicium, présentant ledit premier type de conductivité, et présentant une concentration d'impuretés supérieure à ladite concentration d'impuretés Nd.
  6. Le dispositif à semi-conducteur au carbure de silicium selon l'une quelconque des revendications 1 à 5, dans lequel
    ladite deuxième surface principale de ladite couche de carbure de silicium est disposée avec un sillon, ledit sillon présente une surface de paroi latérale passant ladite zone source et ladite zone de corps pour atteindre ladite couche de dérive et une surface de fond située sur ladite couche de dérive,
    ledit film d'isolation de grille couvre chacune de ladite surface de paroi latérale et ladite surface de fond dudit sillon, et
    ladite zone de relâchement est disposée à un emplacement plus profond que ladite surface inférieure dudit sillon.
  7. Le dispositif à semi-conducteur au carbure de silicium selon la revendication 6, dans lequel une distance Ltr entre ladite zone de relâchement et ladite surface de fond dudit sillon n'est pas supérieure à 4 µm.
  8. Le dispositif à semi-conducteur au carbure de silicium selon l'une quelconque des revendications 1 à 5, dans lequel
    ladite deuxième surface principale de ladite couche de carbure de silicium inclut une surface plate présentant ladite zone source, ladite zone de corps, et ladite couche de dérive, et
    ledit film d'isolation de grille est disposé sur ladite surface plate.
  9. Le dispositif à semi-conducteur au carbure de silicium selon la revendication 8, dans lequel
    ladite zone de corps est une zone de puits présentant une surface latérale et une surface de fond ainsi qu'une partie de coin entre ladite surface latérale et ladite surface de fond, et
    une distance Lpn entre ladite zone de relâchement et ladite partie de coin de ladite zone de puits n'est pas supérieure à 4 µm.
EP13823273.1A 2012-07-25 2013-06-11 Dispositif semi-conducteur en carbure de silicium Active EP2879186B1 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2012164274 2012-07-25
JP2013002655A JP6111673B2 (ja) 2012-07-25 2013-01-10 炭化珪素半導体装置
PCT/JP2013/066078 WO2014017195A1 (fr) 2012-07-25 2013-06-11 Dispositif semi-conducteur en carbure de silicium

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EP2879186A1 EP2879186A1 (fr) 2015-06-03
EP2879186A4 EP2879186A4 (fr) 2016-04-13
EP2879186B1 true EP2879186B1 (fr) 2020-07-22

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US (1) US8803252B2 (fr)
EP (1) EP2879186B1 (fr)
JP (1) JP6111673B2 (fr)
CN (1) CN104380472B (fr)
WO (1) WO2014017195A1 (fr)

Families Citing this family (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9790465B2 (en) 2013-04-30 2017-10-17 Corning Incorporated Spheroid cell culture well article and methods thereof
US9024328B2 (en) * 2013-07-02 2015-05-05 General Electric Company Metal-oxide-semiconductor (MOS) devices with increased channel periphery and methods of manufacture
JP6256075B2 (ja) * 2014-02-13 2018-01-10 住友電気工業株式会社 炭化珪素半導体装置
WO2016069885A1 (fr) 2014-10-29 2016-05-06 Corning Incorporated Plateforme de bioréacteurs de perfusion
JP6439606B2 (ja) * 2015-06-18 2018-12-19 住友電気工業株式会社 炭化珪素半導体装置
JP6708954B2 (ja) 2016-03-31 2020-06-10 住友電気工業株式会社 炭化珪素半導体装置
PL3652290T3 (pl) 2017-07-14 2022-08-22 Corning Incorporated Naczynia do hodowli komórkowej 3d do ręcznej lub automatycznej zmiany pożywek
JP7195302B2 (ja) 2017-07-14 2022-12-23 コーニング インコーポレイテッド ３ｄ培養のための細胞培養容器及び３ｄ細胞の培養方法
US11857970B2 (en) 2017-07-14 2024-01-02 Corning Incorporated Cell culture vessel
CN107742646A (zh) * 2017-09-21 2018-02-27 北京世纪金光半导体有限公司 一种具有掩埋悬浮结的碳化硅平面栅mosfet器件元胞结构
CN108172609A (zh) * 2017-12-22 2018-06-15 北京世纪金光半导体有限公司 具有周边深沟槽保护环和接地环的碳化硅悬浮结mosfet器件
JP6981890B2 (ja) * 2018-01-29 2021-12-17 ルネサスエレクトロニクス株式会社 半導体装置
DE102018112109A1 (de) * 2018-05-18 2019-11-21 Infineon Technologies Ag Siliziumcarbid halbleiterbauelement
JP7353263B2 (ja) 2018-07-13 2023-09-29 コーニング インコーポレイテッド 安定化装置を備えた細胞培養容器
CN111032851B (zh) 2018-07-13 2024-03-29 康宁股份有限公司 具有包含液体介质传递表面的侧壁的微腔皿
WO2020013851A1 (fr) 2018-07-13 2020-01-16 Corning Incorporated Dispositifs fluidiques comprenant des microplaques avec des puits interconnectés
CN109817699B (zh) * 2018-12-29 2022-06-28 上海集成电路研发中心有限公司 一种晶体管以及图像传感器
CN113396481A (zh) * 2019-02-04 2021-09-14 住友电气工业株式会社 碳化硅半导体器件
JP7288827B2 (ja) * 2019-09-06 2023-06-08 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
US20220384566A1 (en) 2019-12-20 2022-12-01 Sumitomo Electric Industries, Ltd. Silicon carbide semiconductor device
US20240047569A1 (en) * 2022-08-08 2024-02-08 Leap Semiconductor Corp. Silicon carbide semiconductor power transistor and method of manufacturing the same
CN116454117B (zh) * 2023-06-01 2023-09-12 苏州华太电子技术股份有限公司 沟槽型mosfet器件

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3158973B2 (ja) * 1995-07-20 2001-04-23 富士電機株式会社 炭化けい素縦型ｆｅｔ
US6037632A (en) 1995-11-06 2000-03-14 Kabushiki Kaisha Toshiba Semiconductor device
JP3392665B2 (ja) 1995-11-06 2003-03-31 株式会社東芝 半導体装置
US5719409A (en) 1996-06-06 1998-02-17 Cree Research, Inc. Silicon carbide metal-insulator semiconductor field effect transistor
SE9704149D0 (sv) * 1997-11-13 1997-11-13 Abb Research Ltd A semiconductor device of SiC and a transistor of SiC having an insulated gate
DE19830332C2 (de) * 1998-07-07 2003-04-17 Infineon Technologies Ag Vertikales Halbleiterbauelement mit reduziertem elektrischem Oberflächenfeld
DE19843659A1 (de) * 1998-09-23 2000-04-06 Siemens Ag Halbleiterbauelement mit strukturiertem Halbleiterkörper
JP3506676B2 (ja) * 2001-01-25 2004-03-15 Ｎｅｃエレクトロニクス株式会社 半導体装置
JP3954541B2 (ja) * 2003-08-05 2007-08-08 株式会社東芝 半導体装置及びその製造方法
JP5233158B2 (ja) 2007-04-25 2013-07-10 富士電機株式会社 炭化珪素半導体装置
US8421148B2 (en) * 2007-09-14 2013-04-16 Cree, Inc. Grid-UMOSFET with electric field shielding of gate oxide
JP4798119B2 (ja) 2007-11-06 2011-10-19 株式会社デンソー 炭化珪素半導体装置およびその製造方法
JP2010232503A (ja) * 2009-03-27 2010-10-14 Furukawa Electric Co Ltd:The 半導体装置および半導体装置の製造方法

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
None *

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JP6111673B2 (ja) 2017-04-12
CN104380472B (zh) 2017-04-19
EP2879186A4 (fr) 2016-04-13
EP2879186A1 (fr) 2015-06-03
US8803252B2 (en) 2014-08-12
US20140027784A1 (en) 2014-01-30
JP2014041990A (ja) 2014-03-06
CN104380472A (zh) 2015-02-25
WO2014017195A1 (fr) 2014-01-30

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