EP2806563A1 - Phasenverriegelungserkennung in Q-fraktioneller digitaler PLL - Google Patents

Phasenverriegelungserkennung in Q-fraktioneller digitaler PLL Download PDF

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Publication number
EP2806563A1
EP2806563A1 EP13305655.6A EP13305655A EP2806563A1 EP 2806563 A1 EP2806563 A1 EP 2806563A1 EP 13305655 A EP13305655 A EP 13305655A EP 2806563 A1 EP2806563 A1 EP 2806563A1
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EP
European Patent Office
Prior art keywords
fractional
modulation
digital
phase error
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP13305655.6A
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English (en)
French (fr)
Inventor
Sebastien Charpentier
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Asahi Kasei Microdevices Corp
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Asahi Kasei Microdevices Corp
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Priority to EP13305655.6A priority Critical patent/EP2806563A1/de
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H03L7/197—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division
    • H03L7/1974—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division for fractional frequency division
    • H03L7/1976—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division for fractional frequency division using a phase accumulator for controlling the counter or frequency divider
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/093—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/095—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using a lock detector

Definitions

  • the present invention generally relates to devices and methods for phase lock detection in Digital Phase-Lock-Loops (DPLL) structures, and more particularly in fractional-Q DPLL structures.
  • DPLL Digital Phase-Lock-Loops
  • DPLL are used to generate an output signal with a high frequency Fout, for instance a Radiofrequency (RF) output signal, from a reference clock signal of lower, stable frequency Fref.
  • Fout for instance a Radiofrequency (RF) output signal
  • RF Radiofrequency
  • DPLLs have superseded classical, i.e., analog Phase-Lock-Loops (PLL) in performances and design simplicity, and are therefore used in an increasing number of applications.
  • PLLs are used in frequency synthesizers for cellular phones or smart phones, digital tablets, digital Tv decoders, Wifi detection modules in desktop computers, etc.
  • DPLL structures are composed of several blocks or modules, including a Time-to-Digital Converter (TDC), a digital loop filter, a Digital-to-Analog Converter (DAC), a Voltage Controlled Oscillator (VCO) or a Digitally Controlled Oscillator (DCO) or DVCO (Oscillator with a digital and an analog inputs), a frequency divider adapted to generate a divided clock signal from the output signal, etc.
  • TDC Time-to-Digital Converter
  • DAC Digital-to-Analog Converter
  • VCO Voltage Controlled Oscillator
  • DCO Digitally Controlled Oscillator
  • DVCO Digitally Controlled Oscillator with a digital and an analog inputs
  • Some DPLL architectures may require a lock detect signal.
  • lock detect signal may be used for triggering internal calibrations processes.
  • a frequency synthesizer including the DPLL may output such a lock detect signal, for example through a dedicated output pad, for the purpose of being used by the RF system.
  • the lock condition of such analog PLL is met when an active edge of the divided clock lies within a capture time window of fixed duration, which is triggered by an active edge of the reference clock during a certain amount of time.
  • a digital counter may be used for measuring said amount of time.
  • the division ratio of the frequency divider is an integral number N .
  • a fractional DPLL may use a Sigma-Delta ( ⁇ ) Modulator for modulating a digital value corresponding to the fractional portion frac(Q) of the divider ratio Q of the frequency divider, which can thus be summed to the integral portion int(Q) of said divider ratio Q .
  • ⁇ Sigma-Delta
  • a DPLL is characterised by its operating frequency and by its ability to promptly and efficiently lock to the desired frequency for the synthesized signal. Whether this condition is met or not may be determined by a lock detector module.
  • a lock detector module is adapted to receive a phase error value provided by the TDC from comparing mutual phases of the reference signal and the synthesized signal, and to output an indication that a lock condition is met or not, with respect to this phase error value.
  • US Patent No. 8,248,106 discloses a TDC based Frequency Lock Detector (TFLD) in a divider-less fractional-N DPLL structure requiring no divider modulation, which is presented as an alternative to conventional counter based lock detect circuits.
  • the frequency lock detector accepts a digital phase error message PHERR and a unit-less frequency error tolerance ⁇ F .
  • the frequency lock detector is designed to generate periodically a lock detect signal indicating whether a synthesizer clock frequency is within the frequency error tolerance value of a reference clock frequency.
  • the determination of the frequency of the VCO in many devices is not easy. Indeed, the value of the VCO frequency changes quickly responsive to its input signal. Further, the frequency lock detector as taught by US Patent No. 8,248,106 performs a frequency lock detection instead of a phase lock detection. Finally, the proposed implementation operates in a divider-less fractional-N DPLL requiring no divider modulation.
  • To present invention aims at providing accurate phase lock detection in a DPLL.
  • phase error signal after the ⁇ noise cancellation module it is proposed to observe the phase error signal after the ⁇ noise cancellation module, then count the number of clock periods wherein the phase error signal is below a threshold value. Since the phase error signal after the ⁇ noise cancellation module does not depend on fractional modulation, the threshold value can be very low. Thus, a very high precision of the lock detector is achieved. The precision of the phase lock detector depends on the TDC resolution, but in all cases it is more accurate than lock detectors used in a classic (i.e. analog) fractional-Q PLL.
  • a first aspect of the invention relates to a fractional Digital Phase-Locked Loop, DPLL, circuit comprising:
  • a second aspect relates to a method of detecting a phase lock state of a fractional Digital Phase-Locked Loop, DPLL, circuit as defined above with respect to the first aspect, wherein the method comprises generating a lock detect signal indicating the lock state of the DPLL, with respect to the second phase error message.
  • DPLL fractional Digital Phase-Locked Loop
  • Embodiments are applicable to DPLL structures using modulation of the fractional portion frac(Q) of the frequency divider ratio Q .
  • the proposed phase lock detection scheme thus relies on observing the digital phase error signal at the output the modulation noise cancellation module.
  • a method using a threshold value compared to digital phase error values will be implemented to enhance the reliability of the detection of the phase lock condition.
  • phase lock detector Since the (second) phase error message after the modulation noise cancellation module does not depend on fractional modulation, a very high precision of the phase lock detector can be achieved.
  • the precision of the phase lock detector depends on the TDC resolution. In all cases, the phase lock detector is more accurate than lock detectors used in a classic (i.e. analog) fractional-Q PLL as known in the prior art.
  • the lock detect signal is activated when a given number of successive values of the second phase error messages keep below a given threshold.
  • the given number and/or the given threshold may be programmable.
  • a third aspect relates to a frequency synthesizer integrated circuit comprising a fractional Digital Phase-Locked Loop, DPLL, circuit according to the first aspect.
  • a fourth aspect relates to a computer program product comprising one or more stored sequences of instructions that are accessible to a processor and which, when executed by the processor, cause the processor to perform the steps of a method according to the second aspect.
  • Embodiments as described herein are directed to a phase lock detecting scheme which is applicable to DPLL structures using modulation of the fractional portion frac(Q) of the frequency divider ratio, as explicated in the introduction.
  • the proposed phase lock detection scheme uses the digital error phase signal directly from a divider modulation noise cancellation module, for instance a ⁇ noise cancellation module where the divider modulation uses a ⁇ modulator.
  • a method of actually detecting the phase lock condition may use a counter and a comparator to compare the digital error phase values with a threshold value.
  • circuit 1 is implemented as part of a mixed, i.e. analog and digital, Integrated Circuit (IC), for instance a fractional DPLL-based frequency synthesizer.
  • IC Integrated Circuit
  • the shown fractional-Q DPLL can thus be divided into three parts depending on the nature, i.e. analog and/or digital, of the signals processed therein.
  • a first part 10 comprises elements which are typically realized in the analog domain.
  • a second part 20 may comprise blocks which are implemented in the digital domain, for instance in the form of hardware modules and/or software modules of an application software running on a Digital Signal Processor (DSP).
  • DSP Digital Signal Processor
  • mixed analog-digital elements comprise devices adapted to perform conversion of signals from the analog part 10 to the digital 20 or vice versa, for instance a Time-to-Digital Converter (TDC) 105 and a Digital-to-Analog Converter (DAC) 107, respectively.
  • TDC Time-to-Digital Converter
  • DAC Digital-to-Analog Converter
  • the first part 10 is composed of analog elements receiving and/or outputting analog signals.
  • these components comprise:
  • the frequency of the synthesized signal 601 is programmable and is controlled by setting the division ratio Q of the frequency divider 103 at a desired number, which may be integral or no-integral, i.e., fractional.
  • the frequency divider is a fractional-Q divider, where Q is a non-integral division ratio which can be split into an integral part INT(Q) and a fractional part FRAC(Q) as defined by relation (1) given in the introduction
  • the TDC 105 has a first input for receiving the reference clock signal 201, and a second input for receiving the divided clock signal 401 from the frequency divider 103. It is adapted to measure the time difference between respective active edges of the signals received on its two inputs, and to generate digital words which in sequence form a phase error message Err1 representative of the phase offset between said signals.
  • the synthesized signal 601 has a frequency equal to Q times the frequency of the reference clock signal 201.
  • the digital word coming out from the TDC is a digital "image" of the charge quantity generated by an analog Charge Pump.
  • the loop feedback signal namely the divided clock signal 401 contains the fractional modulation noise inserted at the frequency divider 103 as part of the process of dividing frequency of the synthesized clock signal 601. It follows there from that the digital message Err1 carries the modulation noise signal in addition to the phase error information, the latter being the information of interest.
  • the second part 20 of the DPLL circuit 1 comprises digital blocks receiving and/or outputting digital signals, which can be software and/or hardware implemented functions running within a DSP.
  • these blocks comprise:
  • any type of digital calculator such as, for instance, a FPGA (Field Programmable Gate Array) circuit, can be used instead of a DSP.
  • FPGA Field Programmable Gate Array
  • the loop filter 106 is operable to filter the phase error message Err2 using well-known mathematical functions implementing a loop filter transfer function H(z).
  • the message Err3 thus obtained at the output of the loop filter 106 is sent to an input of a digital-analog converter 107.
  • the frequency of the modulation signal is programmable, so the circuit may be used for various applications, and for a wide range of frequency of the synthesized signal 601.
  • the ⁇ noise cancellator 113 uses mathematical functions with complex algorithms to achieve removal of the ⁇ modulation noise introduced by the ⁇ modulator 110 and thus generate the phase error message Err2 representing only the phase error information with respect to the reference clock signal 201 and the divided clock signal 401. Stated otherwise, the second digital phase error message Err2 corresponds to the first phase error message Err1 in which the modulation noise associated to the modulation of the fractional part of the division ratio has been cancelled.
  • the phase lock detector 109 includes at least one input for receiving the phase error message Err2 output from the ⁇ noise cancellator 113, and has at least one output adapted to output a lock detect signal 901. Detector 109 further receives an operational clock signal Clk , which may be derived from the reference clock signal 201 so as to have the same frequency as the update frequency of the TDC 105.
  • phase error values of the digital message Err2 after ⁇ noise cancellation then count the number of periods of the clock signal Clk in which the phase error is below a threshold value.
  • phase error signal for the lock detection knowing that the said phase error signal is the result of the integration of the frequency signal between the two input signals of the TDC module, enables to obtain better performances for the lock detection. Moreover, since the phase error signal after the ⁇ noise cancellation module does not depend on fractional modulation, a very high precision of the phase lock detector can be achieved.
  • the precision of the phase lock detector depends on the TDC resolution. TDC resolution is typically in the order of 20 picoseconds (ps), and thus setting the phase lock condition at a number K of periods of the clock signal during which the phase error values must be under the threshold results in a phase lock detector precision of Kx20 ps. In all cases, the phase lock detector is more accurate than lock detectors used in a classic (i.e. analog) fractional-Q PLL as known in the prior art.
  • a method of generating the lock detect signal 901 is further proposed herein, and will now be described with reference to the timing diagrams of FIG.4 .
  • a linear curve is shown at top of this figure, which corresponds to a phase error analog signal would result from an interpolation of the discrete phase error values of the digital phase error message Err2, or from a digital-to-analog conversion thereof. It will be appreciated, however, that the processing of the phase error messages occurs in the DSP on said discrete values.
  • the method uses a threshold value, for example a signed threshold value ⁇ Thsd, which may be programmable. Digital values of the phase error message Err2 output by the ⁇ noise cancellator 113 are compared with said threshold value at the pace of the operation clock signal Clk.
  • a threshold value for example a signed threshold value ⁇ Thsd, which may be programmable.
  • the phase error signal Err2 is a signal with the constant frequency of the clock signal Clk which is used for the DPLL timing.
  • the magnitude of the phase error signal Err2 is variable and this variation is proportional to the phase error between the reference clock signal 201 and the divided clock signal 401 applied on either input of the TDC 105.
  • a counter 114 (as shown in FIG.2 ) is implemented in the DSP for counting the number of periods of the clock signal Clk during which the absolute value of the phase error signal Err2 stays below the threshold value.
  • counter 114 reaches its maximum counting value K, a change of the logic state of the output signal 901 of the lock detector 109 is caused by the DSP, so that output signal 901 is set to indicate that the phase lock condition is met.
  • phase lock detection strategy In order to illustrate the phase lock detection strategy according to a proposed embodiment, the timing diagrams of FIG.4 are divided in six phases of operation. It is recalled that, in line with the convention mentioned in the beginning of the present description, instant values of the phase error signal Err2 must be considered on the rising edges of pulses of the clock signal Clk .
  • the current counting value of the counter 114 is indicated by a figure (from 0 to 5) in the corresponding pulse of the clock signal Clk as shown in FIG.4 .
  • phase error signal Err2 is above the threshold value. This means that the DPLL is unlocked. Thus, the counter value remains 0, assuming that the counter has been previously set to zero. In the shown example, the duration of this phase 41 corresponds to two pulses of the clock signal Clk .
  • the DPLL locks and this starts a second phase 42 followed by a third phase 43 during which the DPLL remains phase locked.
  • the DSP causes the activation of the lock detect signal 901, for instance at a logic high state as shown in FIG.4 .
  • the lock state of the DPLL lasts for only two periods of the clock signal Clk since, at instant t3, the phase error signal Err2 goes above the threshold value again.
  • the lock detect signal 901 is reset to its logic inactive state, and the counter 114 is reset to zero, so that a further phase of operation 44 is started wherein the DPLL is unlocked.
  • another operation phase 46 is started wherein the counter value is zero. This illustrates that the counter may be reset to zero before reaching its maximum value K and thus without the lock detect signal being activated.
  • the number K and/or the threshold value Thsd are programmable, which allows adapting the detection scheme to any particular application, and possibly to provide a dynamic adaptation process of the phase lock detection scheme.
  • Lock detection will occur when the counter reaches 0 and the counter will be pre-loaded to K when the absolute value of Err2 is above the threshold value.
  • the present invention can be implemented in hardware, software, or a combination of hardware and software. Any processor, controller, or other apparatus adapted for carrying out the functionality described herein is suitable.
  • a typical combination of hardware and software could include a DSP with an application computer program that, when loaded and executed, carries out the functionality described herein.
EP13305655.6A 2013-05-22 2013-05-22 Phasenverriegelungserkennung in Q-fraktioneller digitaler PLL Withdrawn EP2806563A1 (de)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2017068629A1 (ja) * 2015-10-19 2017-04-27 三菱電機株式会社 ロック検出装置、周波数シンセサイザ及び半導体装置

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090231050A1 (en) * 2005-12-05 2009-09-17 Chia-Liang Lin Digital fractional-n phase lock loop and method thereof
US20100039182A1 (en) * 2008-01-10 2010-02-18 The Regents Of The University Of California Adaptive noise cancellation for fractional-n phase locked loop
US20110234269A1 (en) * 2010-03-25 2011-09-29 Qicheng Yu Method and apparatus for quantization noise reduction in fractional-n plls
US20120007643A1 (en) * 2010-07-06 2012-01-12 Silicon Storage Technology, Inc. Binary-Weighted Delta-Sigma Fractional-N Frequency Synthesizer With Digital-To-Analog Differentiators Canceling Quantization Noise
US8248106B1 (en) 2010-07-21 2012-08-21 Applied Micro Circuits Corporation Lock detection using a digital phase error message

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090231050A1 (en) * 2005-12-05 2009-09-17 Chia-Liang Lin Digital fractional-n phase lock loop and method thereof
US20100039182A1 (en) * 2008-01-10 2010-02-18 The Regents Of The University Of California Adaptive noise cancellation for fractional-n phase locked loop
US20110234269A1 (en) * 2010-03-25 2011-09-29 Qicheng Yu Method and apparatus for quantization noise reduction in fractional-n plls
US20120007643A1 (en) * 2010-07-06 2012-01-12 Silicon Storage Technology, Inc. Binary-Weighted Delta-Sigma Fractional-N Frequency Synthesizer With Digital-To-Analog Differentiators Canceling Quantization Noise
US8248106B1 (en) 2010-07-21 2012-08-21 Applied Micro Circuits Corporation Lock detection using a digital phase error message

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2017068629A1 (ja) * 2015-10-19 2017-04-27 三菱電機株式会社 ロック検出装置、周波数シンセサイザ及び半導体装置
JPWO2017068629A1 (ja) * 2015-10-19 2018-02-01 三菱電機株式会社 ロック検出装置、周波数シンセサイザ及び半導体装置

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