EP2777078A1 - Fabrication d'un dispositif à semi-conducteurs comprenant au moins un élément semi-conducteur en forme de colonne ou de paroi - Google Patents

Fabrication d'un dispositif à semi-conducteurs comprenant au moins un élément semi-conducteur en forme de colonne ou de paroi

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Publication number
EP2777078A1
EP2777078A1 EP12794633.3A EP12794633A EP2777078A1 EP 2777078 A1 EP2777078 A1 EP 2777078A1 EP 12794633 A EP12794633 A EP 12794633A EP 2777078 A1 EP2777078 A1 EP 2777078A1
Authority
EP
European Patent Office
Prior art keywords
crystal type
sections
crystal
semiconductor
heights
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP12794633.3A
Other languages
German (de)
English (en)
Inventor
Oliver Brandt
Lutz GEELHAAR
Vladimir KAGANER
Martin Wölz
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Forschungsverbund Berlin FVB eV
Original Assignee
Forschungsverbund Berlin FVB eV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Forschungsverbund Berlin FVB eV filed Critical Forschungsverbund Berlin FVB eV
Publication of EP2777078A1 publication Critical patent/EP2777078A1/fr
Withdrawn legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/40—Crystalline structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/81—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials of structures exhibiting quantum-confinement effects, e.g. single quantum wells; of structures having periodic or quasi-periodic potential variation
    • H10D62/812—Single quantum well structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/85—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/85—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs
    • H10D62/8503—Nitride Group III-V materials, e.g. AlN or GaN
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F77/00—Constructional details of devices covered by this subclass
    • H10F77/10—Semiconductor bodies
    • H10F77/14—Shape of semiconductor bodies; Shapes, relative sizes or dispositions of semiconductor regions within semiconductor bodies
    • H10F77/143—Shape of semiconductor bodies; Shapes, relative sizes or dispositions of semiconductor regions within semiconductor bodies comprising quantum structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80—Constructional details
    • H10H20/81—Bodies
    • H10H20/811—Bodies having quantum effect structures or superlattices, e.g. tunnel junctions
    • H10H20/812—Bodies having quantum effect structures or superlattices, e.g. tunnel junctions within the light-emitting regions, e.g. having quantum confinement structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80—Constructional details
    • H10H20/81—Bodies
    • H10H20/817—Bodies characterised by the crystal structures or orientations, e.g. polycrystalline, amorphous or porous
    • H10H20/818—Bodies characterised by the crystal structures or orientations, e.g. polycrystalline, amorphous or porous within the light-emitting regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • the invention relates to a method for producing a semiconductor device, such as. B. a light-emitting device, with at least one columnar or wall-shaped semiconductor element, in particular a method for producing a semiconductor device whose at least one semiconductor element in at least one cross-sectional direction has a lateral thickness less than 1 ⁇ , in particular less than 500 nm. Furthermore, the invention relates to a semiconductor device having at least one columnar or wall-shaped semiconductor element, in particular a semiconductor device having at least one nanopillar and / or at least one nanowind, which is arranged on a substrate. Applications of the invention are given in the production of optical, in particular light-emitting, electrical, electromechanical and / or electrothermal components.
  • nanostructured semiconductor elements On a substrate which have characteristic dimensions in the sub-micrometer range.
  • For the structuring of a substrate and the production of the semiconductor elements are “top-down” methods such.
  • nano-column heterostructures are produced which along a major direction of the semiconductor elements have sections of different crystal types, e.g. B. with different chemical composition or different
  • the object of the invention is to provide an improved method for producing a semiconductor device comprising a patterned semiconductor, with which
  • the object of the invention is in particular to provide a method for producing a semiconductor device with nanostructured semiconductor elements, which is characterized by a simplified process control.
  • the method should also enable increased accuracy and / or reproducibility in the adjustment of optical, electrical, mechanical and / or thermal properties of the semiconductor elements.
  • Another object of the invention is to provide an improved semiconductor device comprising a patterned semiconductor which avoids the disadvantages of conventional semiconductor devices with patterned semiconductors.
  • the semiconductor device should be particularly suitable for a simplified production and / or an accurate and reproducible adjustment of physical or chemical properties.
  • the stated objects are achieved in each case by a method for producing a semiconductor device or by a semiconductor device, wherein the semiconductor device comprises a substrate and at least one semiconductor element which has an elongate shape and in a main direction which depends on the extent of the Surface of the substrate deviates extends.
  • the semiconductor element transversely to the main direction has a Lateraldicke which is less than the Hö ⁇ he (length) of the semiconductor element in the main direction.
  • the elongated shape of the semiconductor element is formed so that the semiconductor element in at least one sectional plane has an aspect ratio (quotient of lateral thickness and Length) is less than 1, preferably less than 0.1, more preferably less than 0.05.
  • Basic forms of the semiconductor element are z.
  • the shape of a column or: needle, wire or rod
  • the shape of a wall or: disc
  • the main direction is formed by the longitudinal direction of the column and in the wall shape by a direction perpendicular to the thickness direction of the wall.
  • the main direction is oriented perpendicular to the surface of the substrate, but alternatively, a tilt angle less than 90 ° may be present.
  • the semiconductor element may have a substantially constant lateral thickness along its entire length or, alternatively, a varying lateral thickness.
  • the columnar shape may have a diameter decreasing or increasing from the substrate to the free end of the semiconductor element. Accordingly, the semiconductor element may also have the shape of a pyramid or truncated cone or a more complicated geometric shape.
  • the semiconductor element has an active region with sections of different crystal types. At least two sections of a first crystal type are provided, between which a section of a second crystal type is arranged. In practical applications of the invention, there is preferably a series of the first crystal type portions separated by second crystal type portions.
  • the first and second types of crystals characterized by different lattice constants and un ⁇ ter Kunststoffliche optical, electrical, mechanical and / or thermal properties such. B. by different line properties and band gaps, from.
  • the sections of the different crystal types different functions. For example, in an LED, the portions of the first crystal ⁇ type quantum well portions and the portions of the second crystal type barrier sections.
  • the first and second types of crystals have different Git ⁇ terkonstanten.
  • the difference in the lattice constants causes a lattice strain to occur in the sections of the first crystal type, which depends on the lattice constant in the section of the second crystal type.
  • the at least one portion of the second crystal type also has a lattice strain that depends on the lattice constant in the adjacent portions of the first crystal type. For both types of crystal the strain is laterally inhomogeneous.
  • the active region of the at least one semiconductor element is geometrically dimensioned such that the lattice strain in the at least two sections of the first crystal type is not only dependent on the lattice constant of the first crystal type
  • the geometrical dimensions of the active area means that the height (thickness in the main direction) of the portion of the second crystal type and / or the Lateraldicke is (thickness transversely to the main direction) of the semiconducting ⁇ terelements, in particular of the active region is selected so that superimpose or influence the grating stresses of the first crystal type portions.
  • the inventors have found that with the height of the portion of the second crystal type, ie with the distance of at least two portions of the first crystal type in the main direction, and with the lateral thickness of the active region two new degrees of freedom, which are not available in conventional methods, can be created with which physical or chemical properties of the at least one semiconductor element can be set.
  • the quantum well portions are so far apart that they do not affect each other.
  • a mutual dependence of the lattice strain of the sections of the first crystal type is set in a targeted manner.
  • the inventors have further found, in contrast to the findings described in US 2011/0127490 AI, that the geometric dimensioning of the active region and therefore with the lattice strain optical, electrical, mechanical and / or thermal properties of the semiconductor element in contrast to the conventional approach To change the composition can be varied in a simplified way.
  • the geometric dimensioning of the active region especially when properties of the quantum wells are to be changed within the nano-column, places lower demands on the process management than, for example, Example, the conventional variation of the composition of a semiconductor in the longitudinal direction of the nanocolumn.
  • the change in vapor composition and temperature in the crystal growth process to vary the crystal composition can be replaced by the variation of the column geometry, which greatly simplifies the manufacturing process. Furthermore, the reproducibility of the process ⁇ leadership can improve.
  • the invention is based in particular on the following considerations of the inventors.
  • Two coherently bonded crystals with different lattice constants are mechanically stressed.
  • the stress influences essential properties of the semiconductor, such as. B. its electronic band structure, the charge carrier Agility, heat capacity or thermal conductivity.
  • the strain already occurs in conventional semiconductor devices with layered (unstructured) heterostructures of contiguous or interrupted thin layers, the lattice mismatch determines the state of stress of the layer. This would be adjustable only by the introduction of defects.
  • the mutual influence of the physical or chemical properties of the sections of the first crystal type and thus of the semiconductor elements due to the lattice strain has hitherto been disregarded.
  • the invention is now based on the idea of arranging crystallites with mismatch, ie different sections of different crystal types, in such a way that a relaxation takes place at the free surfaces of the semiconductor elements.
  • the semiconductor elements have a high aspect ratio.
  • the remaining stress in the sections can be set in particular by the mentioned geometric dimensions, such as the quotients of the heights of the adjacent sections of the first and second crystal types and / or the quotient of the height of the active area and the lateral thickness of the active area.
  • a targeted adjustment of physical and / or chemical properties of the semiconductor element, in particular of optical, electrical, mechanical and / or thermal properties of the semiconductor element, by adjusting at least one height quotient of adjacent sections and / or heights -Laterdicken- quotient predetermined, material-dependent reference values are used.
  • the process conditions are such.
  • the reference values are z. As determined by theoretical simulations depending on the materials used, from existing table values or by simple experiments.
  • the active region can be dimensioned such that all sections of the first crystal type have the same lattice strain along the main direction of the semiconductor element.
  • all portions of the first crystal type have the same optical, electrical, mechanical and / or thermal properties.
  • the inventors have found that, for example, in an LED, the lattice strain of the quantum well portions in the longitudinal ⁇ direction of a columnar semiconductor element can vary when all barrier sections have the same height. Accordingly, the spectral range of the emission would broaden.
  • the grating strains are set so that light of different wavelengths is emitted from all the quantum well portions, so that the at least one semiconductor element can be used as a broadband light source.
  • the lattice strain can be adjusted in at least one of the sections of the first crystal type by embedding the respective section on all sides in the material of the second crystal type.
  • the first crystal type portion has an interface with the second crystal type portion not only in the main direction of the semiconductor element but also in the thickness direction transverse to the main direction.
  • this provides an additional degree of freedom in the adjustment of the physical or chemical properties of the relevant section or of the entire semiconductor element.
  • a semiconductor device according to the invention can with a single semiconductor element, for. As a single nanocolumn or nanowire, be prepared on the substrate. This variant may have advantages, for. B. ben in the use of the semiconductor ⁇ element as an electronic component in a circuit ben. According to a preferred embodiment of the invention, however, it is provided that a plurality of the semiconductor elements are arranged projecting from the substrate surface on the substrate.
  • the method may be carried out so that all semiconductor elements of the same shapes and sizes or that the semiconductor elements are produced with different shapes and / or sizes. For example, even columns and wall shapes may be combined on a common sub ⁇ strat.
  • the provision of a plurality of semiconductor elements on a common substrate has the advantage that the Effect of the inventive setting of the electrical, optical, mechanical and / or thermal properties of the semiconductor elements is summed.
  • LEDs can be created with a significantly increased brightness.
  • the provision of a plurality of semiconductor elements offers further possible variations for the design of the semiconductor device.
  • the active regions of all semiconductor elements can be dimensioned the same, so that the physical and / or chemical properties of all semiconductor elements are identical.
  • the active regions of the semiconductor elements can be dimensioned differently, so that correspondingly a variation of the physical and / or chemical properties of the semiconductor elements within the semiconductor device is achieved.
  • the invention with a variety of semiconductors can be realized.
  • the portions of the first and / or second crystal types are made of a nitride-based semiconductor, in particular a gallium nitride-based semiconductor, an arsenide-based semiconductor, in particular a gallium arsenide-based semiconductor, an antimonide-based semiconductor, in particular a gallium antimony-based semiconductor , a phosphide-based semiconductor, in particular a gallium phosphide-based semiconductor, a silicon-based semiconductor and / or a germanium-based semiconductor.
  • the at least one semiconductor element is produced with the following geometric dimensions.
  • Column-shaped semiconductor element lateral thickness ⁇ 1 ⁇ m, preferably ⁇ 500 nm, particularly preferably ⁇ 50 nm; Length:> 100 nm, preferably> 500 nm, more preferably> 1 ⁇ ; Length of the active rich:> 50 nm, preferably> 100 nm, more preferably> 150 nm; Number of sections of the first crystal type: at least 2, preferably at least 4, more preferably at least 6; Height (hi) of the portions of the first crystal type: ⁇ 100 nm, preferably ⁇ 10 nm, more preferably
  • Wall-shaped semiconductor element Dimensioning such as the columnar semiconductor element, with a freely selectable extension in the longitudinal direction of the plate.
  • LED light-emitting component
  • further preferred applications include the provision of an electronic component, eg. B. in an integrated circuit, an opto-electronic device, for. As a solar cell, an electro-mechanical device or a thermoelectric device.
  • FIG. 1 shows schematic sectional views of various variants of columnar semiconductor elements according to the invention
  • FIG. 2 shows a schematic perspective view of a variant of a wall-shaped semiconductor element according to the invention
  • Figure 3 is a schematic perspective view of an embodiment of the semiconductor device having a plurality of columnar semiconductor elements
  • Figure 4 is a further schematic sectional view of a kla ⁇ lenförmigen semiconductor element
  • FIG. 5 Room temperature photoluminescence spectra for the active zone of an LED according to the invention.
  • the invention will be described in particular with regard to the adjustment of the lattice strain in the sections of the first crystal type. Depending on the specific application of the invention, it may alternatively or additionally be provided that the lattice strain in the sections of the second crystal type is specifically adjusted.
  • GaN-based semiconductors Although reference is made in the following to GaN-based semiconductors by way of example, it should be emphasized that the implementation of the invention is not restricted to these semiconductors but is instead speaking with other doped or non-doped semiconductors is possible.
  • the invention will be described below by way of example with reference to the production of an LED in which the at least one nanostructured semiconductor element comprises a heterostructure of quantum well sections and barrier sections.
  • the sections of the first and second crystal types in the at least one semiconductor element are accordingly drawn in the following as quantum well sections and as barrier sections. Since the implementation of the invention is not limited to the manufacture of an LED device, the sections of the first and second crystal types have different functions than the quantum well sections and the barrier sections in other applications.
  • FIG. 1 illustrates, in a schematic sectional view, a semiconductor device 100 according to the invention with various variants of columnar semiconductor elements 10 arranged on a substrate 30.
  • the semiconductor elements 10 have an elongated columnar shape with a main direction that is perpendicular to the surface of the substrate 30 in FIG. 1 as a z-direction in the plane of the paper.
  • the semiconductor elements 10 have z. B. a circular, elliptical or polygonal cross-section with a characteristic cross-sectional dimension (lateral thickness) D in the x direction in the range of z. B. 10 nm to 200 nm.
  • the length of the semiconductor elements 10 in the z direction is selected for example in the range of 30 nm to 500 nm.
  • the quantum well sections 11, 13, ... have a height hi, which in the range of z. B. 1 nm to 5 nm is selected, while the barrier sections 12, 14, ... a height have, the z. B. is selected in the range of 1 nm to 20 nm.
  • the quantum well portions 11, 13, ... are z. B. from (In, Ga) N, while the barrier sections 12, 14, ... are made of GaN.
  • the quantum well sections 11, 13,... Have a narrower band gap than the barrier sections 12, 14, the emission wavelength of the light emitted by the semiconductor elements 10 depending on the band gaps in the quantum well sections 11, 13,.
  • the substrate 30 is z. B. of sapphire or silicon.
  • the thickness of the substrate 30 is z. B. selected in the range of 250 ⁇ to 1 mm.
  • the quotient are from the heights h x and h 2 (hi: h 2) and / or the quotient of the height H and the Lateraldicke D (H: D) selected such that the lattice tension in the quantum well sections 11 , 13, ... influence each other as described below with reference to FIG.
  • the variants I and II differ by the lateral thickness D. As the lateral thickness D increases, the influence of adjacent quantum well portions is reduced.
  • variants III and IV show that in the active region 40, the heights h 2 of the barrier sections can vary. Accordingly, the emission wavelengths of the quantum well portions differ.
  • the heights hi of the quantum well portions could be varied in the z direction.
  • variant V shows a structure in which the quantum well sections 11, 13,... Are completely embedded in the material of the barrier sections 12, 14,.
  • the extension of the quantum well sections 11, 13,... In x- Direction can be selected, for example, about 1 nm to 3 nm smaller than the lateral thickness D.
  • FIG. 2 schematically illustrates an embodiment of a semiconductor device 100 according to the invention with a wall-shaped semiconductor element 20 which is arranged on the substrate 30.
  • the wall-shaped semiconductor element 20 has a substantially two-dimensional extent in the z and y directions, which is selected in the range of 200 nm to 2 ⁇ .
  • the lateral thickness D in the x direction is chosen to be much smaller in the range from 20 nm to 200 nm.
  • a series of quantum well portions 21, 23, ... and barrier portions 22, 24, ... form the active region 40 with a height H selected in the range of 30 nm to 200 nm.
  • FIG. 3 shows, in a schematic perspective view, an embodiment of the semiconductor device 100 according to the invention, in which a multiplicity of columnar semiconductor elements 10, each having an active region 40 of quantum well and barrier sections, are arranged on the substrate 30.
  • the semiconductor elements 10 cover on the substrate 30 a surface which z. B. 100 pm 2 to 4 mm 2 .
  • the at least one semiconductor element, in particular the columnar semiconductor elements 10 according to FIG. 3, can be produced by the following methods. First, a self-organized crystal growth process can be realized in which the growth in length is greater than the width growth, such. In molecular beam epitaxy of GaN (0001) and (In, Ga) N (0001) under nitrogen-rich conditions.
  • the lateral thickness D of the columnar semiconductor elements 10 can be adjusted by the selection and / or structuring of the substrate 30.
  • the columnar shape is used during waxing maintain the quantum well sections and barrier sections.
  • the heights of the quantum well sections and barrier sections are adjusted by the material feed in molecular beam epitaxy.
  • the complete embedding of the quantum well sections in the material of the barrier sections can be achieved by a variation of the process parameters.
  • FIG. 1 and 2 only the semiconductor elements and the substrate are shown. In practice, further components are provided depending on the specific application of the semiconductor device. For example, approximately purposes (shown gestri ⁇ smiles in Figure 3) in the LED application of contact electrodes to the substrate and a top electrode plate for Maisie- provided.
  • the contact electrodes are z. B. connected to a control device and power supply.
  • the semiconductor elements 10 can be shaped according to FIG. 3 so that they fuse together at their upper end, as described by A. Kikuchi et al. (see above), whereby a contact of the semiconductor elements 10 is simplified.
  • Figure 4 illustrates schematically the effect of the inventively provided geometric dimensioning of the active area on the example of a single pillar-shaped semiconducting ⁇ terelements 10.
  • Figure 4 illustrates schematically the effect of the inventively provided geometric dimensioning of the active area on the example of a single pillar-shaped semiconducting ⁇ terelements 10.
  • the upper part of Figure 4 is a sequence of two sections 11, 13 of the first crystal type with the height hi, which are separated by a barrier section 12 of the second crystal type with the height h 2 .
  • the average lateral stress is shown schematically in the case in which the unstressed lattice constant of the first crystal type (11, 13) is greater than that of the material of the second crystal type.
  • the lattice strain due to the mismatch between sections 11/12 and 12/13 causes a stress, which in this example is compressive (-) in sections 11, 13 and (+) in the adjacent section 12 and the remainder of the semiconductor material (see solid line on the right side of the semiconductor element 10).
  • the unstrained reference state is indicated by the dashed straight line.
  • the stresses in the sections 11, 13 of the first crystal type do not or only slightly, ie the stress is mainly determined by the section 12 and the remaining semiconductor material.
  • This situation is typically given in conventional semiconductor elements, but according to the invention also z. B. be set using predetermined, material-dependent reference values targeted.
  • the strain in one of the first crystal type portions (eg 11) will affect the strain in the second of the first crystal type portions (e.g. B. 13) and vice versa, it is reduced overall. Accordingly, the geometrical dimensioning of the heights hi and h 2 sets the grating tension in the sections 11, 13 of the first crystal type. Alternatively or additionally, this effect can be influenced by the choice of the lateral thickness D of the semiconductor element 10.
  • the influence of the stress on the band structure of a semiconductor crystal illustrated in FIG. 4 is preferably used in light-emitting components (LEDs). Given the composition of the crystal types, the energy of the resulting photons for each individual column can be influenced by the strain. Thus, multi-color light can be generated with a small number of quantum well portions (crystal layers). For example, three quantum well sections are provided.
  • the semiconductor element can be used in a thermally active device. Since crystals under compression have an improved thermal conductivity, the thermal conductivity can become anisotropic due to the strain of individual crystal axes. A high thermal conductivity allows the dissipation of heat loss from electronic components, while a low heat conductivity ⁇ can increase the efficiency of thermoelectric systems.
  • FIG. 5 illustrates an experimental result which illustrates the shift of the emission wavelength of an LED test structure according to the invention as a function of the size h 2 of the barrier sections.
  • the height h 2 of the barrier sections decreases in the range of 23 nm to 1 nm, it changes the wavelength of the light emission from 600 nm to 650 nm (intensity I, relative units).
  • This effect can be ⁇ uses to set selectively, depending on the geometric dimensions of the active area of the semiconductor elements, a light emission having a desired spectral distribution.

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  • Led Devices (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Recrystallisation Techniques (AREA)

Abstract

L'invention concerne un procédé de fabrication d'un dispositif à semi-conducteurs (100), dans lequel au moins un élément semi-conducteur en forme de colonne ou de paroi (10, 20) qui s'étend dans une direction principale (z) est formé sur un substrat (30). Dans une zone active (40) sont formés au moins deux segments (11, 13, 21, 23) d'un premier type cristallin et, entre ceux-ci, un segment (12, 22) d'un deuxième type cristallin, lesdits segments ayant chacun des hauteurs (h1, h2) prédéfinies. Le premier et le deuxième type cristallin présentent des constantes de réseau différentes et chacun des segments du premier type cristallin présente une distorsion de réseau qui est fonction des constantes de réseau dans le segment du deuxième type cristallin. Selon l'invention, une grandeur au moins parmi la hauteur (h2) du segment (12, 22) du deuxième type cristallin et une épaisseur latérale (D) de la zone active (40) perpendiculairement à la direction principale est dimensionnée de manière ciblée pour que la distorsion de réseau dans un des segments (11) du premier type cristallin dépende en plus des constantes de réseau dans l'autre segment (13) du premier type cristallin. L'invention concerne également un dispositif à semi-conducteurs (100) comprenant au moins un élément semi-conducteur en forme de colonne ou de paroi (10, 20) sur un substrat (30), en particulier fabriqué suivant le procédé ci-dessus.
EP12794633.3A 2011-11-11 2012-11-09 Fabrication d'un dispositif à semi-conducteurs comprenant au moins un élément semi-conducteur en forme de colonne ou de paroi Withdrawn EP2777078A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE102011118273A DE102011118273A1 (de) 2011-11-11 2011-11-11 Herstellung einer Halbleitereinrichtung mit mindestens einem säulen- oder wandförmigen Halbleiter-Element
PCT/EP2012/004667 WO2013068125A1 (fr) 2011-11-11 2012-11-09 Fabrication d'un dispositif à semi-conducteurs comprenant au moins un élément semi-conducteur en forme de colonne ou de paroi

Publications (1)

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EP2777078A1 true EP2777078A1 (fr) 2014-09-17

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EP12794633.3A Withdrawn EP2777078A1 (fr) 2011-11-11 2012-11-09 Fabrication d'un dispositif à semi-conducteurs comprenant au moins un élément semi-conducteur en forme de colonne ou de paroi

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Country Link
US (1) US9184235B2 (fr)
EP (1) EP2777078A1 (fr)
DE (1) DE102011118273A1 (fr)
WO (1) WO2013068125A1 (fr)

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US9184235B2 (en) 2015-11-10
WO2013068125A8 (fr) 2013-08-29
DE102011118273A1 (de) 2013-05-16

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