EP2697826A4 - Dépôt à basse température de films d'oxyde de silicium - Google Patents

Dépôt à basse température de films d'oxyde de silicium

Info

Publication number
EP2697826A4
EP2697826A4 EP12770650.5A EP12770650A EP2697826A4 EP 2697826 A4 EP2697826 A4 EP 2697826A4 EP 12770650 A EP12770650 A EP 12770650A EP 2697826 A4 EP2697826 A4 EP 2697826A4
Authority
EP
European Patent Office
Prior art keywords
low temperature
silicon oxide
oxide films
temperature deposition
deposition
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP12770650.5A
Other languages
German (de)
English (en)
Other versions
EP2697826A1 (fr
Inventor
Curtis Dove
Baljit Singh
Eduard Gil Paran Tesnado
Mehdi Balooch
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Asia Union Electronic Chemical Corp
Original Assignee
Asia Union Electronic Chemical Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Asia Union Electronic Chemical Corp filed Critical Asia Union Electronic Chemical Corp
Publication of EP2697826A1 publication Critical patent/EP2697826A1/fr
Publication of EP2697826A4 publication Critical patent/EP2697826A4/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
    • H01L21/02233—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
    • H01L21/02236—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor
    • H01L21/02238—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor silicon in uncombined form, i.e. pure silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0216—Coatings
    • H01L31/02161—Coatings for devices characterised by at least one potential jump barrier or surface barrier
    • H01L31/02167—Coatings for devices characterised by at least one potential jump barrier or surface barrier for solar cells
    • H01L31/02168—Coatings for devices characterised by at least one potential jump barrier or surface barrier for solar cells the coatings being antireflective or having enhancing optical properties for the solar cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Sustainable Development (AREA)
  • Life Sciences & Earth Sciences (AREA)
  • Electromagnetism (AREA)
  • Manufacturing & Machinery (AREA)
  • Sustainable Energy (AREA)
  • Photovoltaic Devices (AREA)
  • Surface Treatment Of Glass (AREA)
  • Paints Or Removers (AREA)
  • Formation Of Insulating Films (AREA)
EP12770650.5A 2011-04-12 2012-03-29 Dépôt à basse température de films d'oxyde de silicium Withdrawn EP2697826A4 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US201161474415P 2011-04-12 2011-04-12
PCT/US2012/031122 WO2012141908A1 (fr) 2011-04-12 2012-03-29 Dépôt à basse température de films d'oxyde de silicium

Publications (2)

Publication Number Publication Date
EP2697826A1 EP2697826A1 (fr) 2014-02-19
EP2697826A4 true EP2697826A4 (fr) 2014-10-22

Family

ID=47009645

Family Applications (1)

Application Number Title Priority Date Filing Date
EP12770650.5A Withdrawn EP2697826A4 (fr) 2011-04-12 2012-03-29 Dépôt à basse température de films d'oxyde de silicium

Country Status (4)

Country Link
EP (1) EP2697826A4 (fr)
SG (1) SG194085A1 (fr)
TW (1) TW201307610A (fr)
WO (1) WO2012141908A1 (fr)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102013004611B4 (de) * 2013-03-14 2014-12-24 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Beschichtung, Verfahren zu deren Herstellung und ihre Verwendung

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5616233A (en) * 1996-05-01 1997-04-01 National Science Council Method for making a fluorinated silicon dioxide layer on silicon substrate by anodic oxidation at room temperature
US20020106865A1 (en) * 2001-02-05 2002-08-08 Tai-Ju Chen Method of forming shallow trench isolation
EP1293488A1 (fr) * 2001-09-12 2003-03-19 Toyo Gosei Kogyo Co., Ltd. Solution de revêtement et procédé pour appliquer un film de revêtement transparent

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2721632B2 (ja) * 1992-02-25 1998-03-04 松下電工株式会社 回路板の銅回路の処理方法
KR101132533B1 (ko) * 2003-10-29 2012-04-03 아반토르 퍼포먼스 머티리얼스, 인크. 알칼리성, 플라즈마 에칭/애싱 후 잔류물 제거제 및금속-할라이드 부식 억제제를 함유한 포토레지스트스트리핑 조성물
KR100971658B1 (ko) * 2008-01-03 2010-07-22 엘지전자 주식회사 실리콘 태양전지의 텍스처링 방법

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5616233A (en) * 1996-05-01 1997-04-01 National Science Council Method for making a fluorinated silicon dioxide layer on silicon substrate by anodic oxidation at room temperature
US20020106865A1 (en) * 2001-02-05 2002-08-08 Tai-Ju Chen Method of forming shallow trench isolation
EP1293488A1 (fr) * 2001-09-12 2003-03-19 Toyo Gosei Kogyo Co., Ltd. Solution de revêtement et procédé pour appliquer un film de revêtement transparent

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of WO2012141908A1 *

Also Published As

Publication number Publication date
TW201307610A (zh) 2013-02-16
EP2697826A1 (fr) 2014-02-19
WO2012141908A8 (fr) 2012-11-22
SG194085A1 (en) 2013-11-29
WO2012141908A1 (fr) 2012-10-18

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