Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W42/00—Arrangements for protection of devices
  • H10W42/80—Arrangements for protection of devices protecting against overcurrent or overload, e.g. fuses or shunts
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W40/00—Arrangements for thermal protection or thermal control
  • H10W40/70—Fillings or auxiliary members in containers or in encapsulations for thermal protection or control
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
  • H10W70/20—Conductive package substrates serving as an interconnection, e.g. metal plates
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/071—Connecting or disconnecting
  • H10W72/073—Connecting or disconnecting of die-attach connectors
  • H10W72/07331—Connecting techniques
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/071—Connecting or disconnecting
  • H10W72/073—Connecting or disconnecting of die-attach connectors
  • H10W72/07351—Connecting or disconnecting of die-attach connectors characterised by changes in properties of the die-attach connectors during connecting
  • H10W72/07354—Connecting or disconnecting of die-attach connectors characterised by changes in properties of the die-attach connectors during connecting changes in dispositions
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/30—Die-attach connectors
  • H10W72/321—Structures or relative sizes of die-attach connectors
  • H10W72/325—Die-attach connectors having a filler embedded in a matrix
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/30—Die-attach connectors
  • H10W72/341—Dispositions of die-attach connectors, e.g. layouts
  • H10W72/347—Dispositions of multiple die-attach connectors
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/30—Die-attach connectors
  • H10W72/351—Materials of die-attach connectors
  • H10W72/352—Materials of die-attach connectors comprising metals or metalloids, e.g. solders
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/851—Dispositions of multiple connectors or interconnections
  • H10W72/853—On the same surface
  • H10W72/865—Die-attach connectors and bond wires
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/851—Dispositions of multiple connectors or interconnections
  • H10W72/874—On different surfaces
  • H10W72/884—Die-attach connectors and bond wires
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/90—Bond pads, in general
  • H10W72/941—Dispositions of bond pads
  • H10W72/944—Dispositions of multiple bond pads
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/90—Bond pads, in general
  • H10W72/951—Materials of bond pads
  • H10W72/952—Materials of bond pads comprising metals or metalloids, e.g. PbSn, Ag or Cu
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W76/00—Containers; Fillings or auxiliary members therefor; Seals
  • H10W76/40—Fillings or auxiliary members in containers, e.g. centering rings
  • H10W76/42—Fillings
  • H10W76/47—Solid or gel fillings
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W90/00—Package configurations
  • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
  • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
  • H10W90/736—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked lead frame, conducting package substrate or heat sink
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W90/00—Package configurations
  • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
  • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
  • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Definitions

• the invention relates to the area of high power applications, and in
• An electronic power apparatus comprises one or more (high) power
• semiconductor module may comprise switching functionality, and may be configured as transistors or diodes. Failure of one or more of the power semiconductor chips and thus of the power semiconductor modules during operation may cause a failure of the electronic power apparatus and also represent an important issue regarding manufacturing, maintenance and/or retrofitting applications.
• power semiconductor modules (particularly semiconductor modules such as insulated gate bipolar transistor (IGBT) modules) with an internal short circuit failure mode SCFM capability are important components of an electronic power apparatuses such as voltage source converters (VSC) usable in a power transmission area.
• SCFM capability means that a power semiconductor chip of the power semiconductor module fails not with an open circuit, but a short circuit. If failed, the power semiconductor chips are not able to switch any more. However, the power semiconductor chip still carry a load current at least for certain time. There is designed redundancy in the system, and the other power semiconductor modules are able to share the blocking voltage since a failed power semiconductor module has now only a function of a resistor (with a very low resistance) or conductor. Therefore, the electronic power apparatuses equipped with such power semiconductor modules usually require only regular, planned maintenance to change the failed power semiconductor modules.
• One of the possible solutions (and a current solution of the applicant) for the SCFM capability of a power semiconductor module is based on melting of materials due to dissipation of energy induced by the failure.
• a silicon power semiconductor chip and a suitable metal part attached to an emitter contact of the power semiconductor chip for example, aluminum (Al), silver (Ag) - these materials must create an eutectic alloy with silicon with sufficiently low melting temperature) melt and create an electrically highly conductive alloy - a so called "hot spot".
• Such a built-in solution has been applied in press-pack power semiconductor module concepts - a so called StakPak (see for example, EP 0 989 611 A2 or B1 , US 6,426,561 B1 , US 7,538,436 B2 the content of which will be detailed later).
• the collector side of the power semiconductor chips is soldered to the substrate.
• an aluminum piece (a component to be melt to form a conductive channel through the chip) and the molybdenum piece (a component compensating a coefficient of thermal expansion (CTE) mismatch) are stacked on the emitter side of each power semiconductor chip.
• a mechanical component (a spring) is used to apply pressure necessary for a dry contact of a good quality.
• dry contact may particularly denote a pressure based contact interface between the power semiconductor chip and components arranged adjacent to the power semiconductor chip.
• the spring concept also protects chips against mechanical damage allowing homogeneous distribution of pressure between power semiconductor chips and allows compensating height changes caused by short circuit failure.
• a spring-loaded press pack package comprising SCFM capability.
• a respective package comprises a baseplate on which a silicon-based power semiconductor chip is soldered.
• a platelet is arranged on an upper side of the silicon chip, and is pressed by a spring loaded pin towards the power semiconductor chip.
• the material of the power semiconductor chip and the material of the platelet are heated such that an eutectic metallic alloy is formed which provides a short circuit path over the power semiconductor chip.
• EP 0 989 61 1 A2 or B1 or US 6,426,561 B1 describes a pressure-based IGBT module comprising a plurality of power semiconductor chips connected in parallel to one another and being sandwiched between a conductive substrate and respective pistons.
• a layer made of a material such as aluminum, silver, gold, copper, or magnesium is arranged in contact with the power semiconductor chip, and is arranged between the substrate and a respective one of the pistons. Upon heating, the layer together with the semiconductor material of the power semiconductor chip form an eutectic mixture, and thus form a metallically conductive channel over the power semiconductor chip.
• module comprising a plurality of power semiconductor chips sandwiched between a conductive base plate and a conductive top plate.
• a contact piston presses the top plate and a respective one of the power
• the material of the top plate and the base plate is made of a metal matrix composite material whose value of a coefficient of thermal expansion is adaptable to a value either close to or matching a value of the coefficient of thermal expansion of the material of the power semiconductor chip.
• Typical problems relevant for the described device or StakPak module are aging of dry electrical contacts (for example, due to a penetration of silicone gel which may cover the power semiconductor chips), a resistance of a current path ((particularly owing to) many interfaces (particularly between respective components)), a complexity of (particularly an arrangement of the) mechanical components, a limitation of current load by the spring shape, and costs. Recently there has been also started a discussion about possible limits of current and voltage rating in the future.
• a power semiconductor module comprises a bottom electrode- baseplate, wherein the bottom electrode-baseplate is electrically and thermally conductive, a top electrode-baseplate, wherein the top electrode- baseplate is electrically and thermally conductive, a power semiconductor chip, and a first preform, wherein the power semiconductor chip comprises a bottom electrode and a top electrode, the first preform is made of material configured for supporting a creation of an electrically conductive alloy when being melted, the first preform provides in combination with the power semiconductor chip a short circuit failure mode capability of the power semiconductor module, and wherein the bottom electrode of the power semiconductor chip is thermally and electrically connected to the bottom electrode-baseplate via a first bonding layer, and wherein the top electrode of the power semiconductor chip is thermally and electrically connected to a first side of the first preform via a second bonding layer.
• the second side of the first preform is thermally and electrically connected to the top electrode-baseplate via a
• the electronic power apparatus comprising a power semiconductor module as described above.
• manufacturing a power semiconductor module comprising providing a power semiconductor chip comprising a bottom electrode and a top electrode, providing a bottom electrode-baseplate, wherein the bottom electrode-baseplate is electrically and thermally conductive, providing a top electrode-baseplate, wherein the top
• electrode-baseplate is electrically and thermally conductive, providing a first preform made of material configured for supporting a creation of an electrically conductive alloy (particularly with a material of the
• the term "power semiconductor module” may particularly denote an arrangement which may comprise at least one power semiconductor based component, for example a diode or a transistor.
• power semiconductor chip may particularly denote a
• semiconductor material based functional component may refer to switching a current.
• preform may particularly denote a parison or a workpiece which may particularly comprise or be configured as a platelet.
• top and bottom elements and “upper and lower sides” may particularly denote a relative arrangement of first and second elements or of first and second sides to one another, and may not imply any direction or any arrangement relative to a ground level.
• side of an element may particularly denote a (two dimensional) surface or (three dimensional) surface layer portion of the element.
• a first element is connected to a second element via a third
• element may refer to a direct or indirect connection (particularly via further elements) between the first, second, and third elements.
• bonding may particularly denote a technique for joining
• elements to one another may particularly comprise sintering, soldering, brazing, and diffusion bonding.
• the power semiconductor module may comprise a high
• a presence of dry contacts in the power semiconductor module may be eliminated by present invention, in particular by the bonding layers between the individual elements.
• a risk of a cover material (for example, silicone gel) penetrating into interfaces between respective components and/or a risk of oxidation of the interface between the respective components, particularly by forming insulating layers comprising oxygen, may be reduced.
• the power semiconductor module may be reduced, thereby reducing a resistance along a current path between the top and bottom electrode- baseplates. Accordingly, an efficiency of the power semiconductor module and thus the electronic power apparatus may be enhanced.
• a mechanical complexity of the power semiconductor module may be reduced by avoiding a constructive design comprising a pressure applying element such as a spring.
• apparatus may accordingly comprise a reduced package volume, particularly a reduced height (particularly by about two thirds in
• the power semiconductor module and the electronic power apparatus may be used in various applications areas.
• the bonding layers may represent thin elements and may directly contact adjacent layers or components
• the power semiconductor module may comprise an improved heat dissipation in comparison to power semiconductor module based on pressure applying elements such as a spring.
• the improved heat dissipation of the power semiconductor module via its bottom-electrode baseplate and top electrode-baseplate may correspond to an improved inherent cooling capability of the power semiconductor module being sufficient for short time heat pulses.
• the power semiconductor module may comprise an improved internal SCFM capability provided by the first preform in combination with the power semiconductor chip. In case of a failure of the power
• the material of the first preform and the material of the power semiconductor chip may be heated to melt such that a conductive alloy (particularly an eutectic alloy) having a lower melting temperature compared to the material of the first preform and the material of the power semiconductor chip, may be formed. Accordingly, a conductive current path may be formed by the melted material of the first preform and the material of the melted power semiconductor chip such that the power semiconductor chip may fall into a short circuit failure mode.
• the failed power semiconductor chip may not have a functionality of a switch or diode any more.
• a permanent conductive path with sufficient current carrying capability may be formed by the conductive alloy such that, owing to redundancy in the system in terms of another power semiconductor chips, the respective electronic apparatus may be still operational at least for a short time. Accordingly, the lifetime of the electronic power apparatus may be prolonged despite a failure of the power semiconductor chips by providing a short circuit failure mode.
• maintenance measures may be initiated by for example, a control unit of the electronic power apparatus.
• the first preform must provide enough material to form the conductive channel though the failed power semiconductor chip. This may be the case if the thickness of the first preform is at least 50% of the thickness of the power semiconductor chip and/or may have a thickness of at least 0.1 mm, more preferable of at least 0.5mm and most preferably of at least 0.8mm.
• the manufactured semiconductor module may comprise a sandwiched stack formed by the bottom electrode-baseplate, the semiconductor chip, the first preform, and the top electrode-baseplate.
• Each component of the power semiconductor module may be connected to one another by respective bonding layers formed by bonding (particularly by sintering or soldering).
• the stack comprising the power semiconductor chip and the first preform and may be further elements is formed. All the elements of the sack, including the
• semiconductor chip and the first preform are thermally and electrically connected to each other via bonding layers, in particular by the third bonding layer, and a bottom element in the stack being connected to the bottom electrode-baseplate by the first bonding layer and the top element in the stack being connected to the top electrode-baseplate by the second bonding layer.
• the power semiconductor module may further comprise a second preform comprising material being configured for compensating a thermal expansion mismatch between the power semiconductor chip and the first preform, wherein the second side of the first preform may be thermally and electrically connected to a first side of the second preform via a fourth bonding layer, wherein the second side of the second preform may be thermally and electrically connected to the top electrode-baseplate via the third bonding layer.
• the arrangement of the second preform may reduce stress between the material of the power semiconductor chip and the material of the first preform, thereby improving a reliability of the semiconductor device.
• the stack may comprise the second preform, wherein the second side of the first preform is thermally and electrically connected to the first side of the second preform via the fourth bonding layer.
• the top element in the stack is formed by the second preform and top element of the stack is thermally and electrically connected to the top electrode-baseplate via the third bonding layer.
• At least one of the first and second bonding layers may be configured as silver layers such that conventional and cheap material may be used for connecting the power semiconductor chip to the bottom electrode- baseplate. Further, low melting temperature alloys may be formed by a silver bonding layer in combination with the material of the semiconductor chip (particularly silicon). Thus, the SCFM capability of the semiconductor device may be improved.
• the third bonding layer may be configured as a layer of solder, whereby the top electrode-baseplate and the first preform may be connected to one another by means of soldering.
• soldering a cost-effective technique for connecting the respective components of the power semiconductor module to one another in a mechanically stable way may be used, thereby facilitating the manufacturing of the power semiconductor module.
• the fourth bonding layer may be configured as a silver layer, and the third bonding layer may be configured as a layer of solder. Accordingly, in a case in which the second preform may be present in the power
• the first and second preforms may be connected to one another via a silver layer and the second preform and the top electrode-baseplate may be connected to one another by a layer of solder. Accordingly, a mechanical stability of the power semiconductor module and the SCFM capability of the power semiconductor module may be further enhanced by using silver and solder as bonding material, as may be explained above.
• the power semiconductor module may comprise at least two stacks in parallel. This has the advantage, that the current load can be distributed. Further, in case the third bonding layer is formed by solder, a difference of the height between the stacks can easily be compensated.
• the power semiconductor chip may be an insulated gate bipolar transistor (IGBT), a diode, a metal oxide semiconductor field effect transistor (MOSFET), a thyristor, a gate turn off (GTO) thyristor, an integrated gate commutated thyristor (IGCT), or a reverse conductive chip.
• IGBT insulated gate bipolar transistor
• MOSFET metal oxide semiconductor field effect transistor
• GTO gate turn off
• IGCT integrated gate commutated thyristor
• reverse conductive chip may particularly denote a power semiconductor chip configured for operating in both freewheeling diode mode and transistor mode by utilizing the same available silicon volume in both modes such that an increase in the power density level of the power semiconductor chip and thus in the module may be accomplished.
• a reverse conductive chip may comprise or may be configured as a bimodal insulated gate transistor (BIGT) or a reverse conductive IGBT.
• BIGT bimodal insulated gate transistor
• the top electrode-baseplate and/or the bottom electrode-baseplate may be made of molybdenum, aluminum-graphite, copper-graphite, copper- molybdenum or any material having a coefficient of thermal expansion sufficiently close to the coefficient of thermal expansion of a power semiconductor chip material (for example, silicon).
• a power semiconductor chip material for example, silicon.
• the top electrode-baseplate may be arranged in parallel to the bottom electrode-baseplate.
• the first preform may be made of aluminum-graphite (Al-graphite) or a laminate material of aluminum and molybdenum-aluminum (for example, AI/AI(AIMo)/AI).
• Al-graphite aluminum-graphite
• a laminate material of aluminum and molybdenum-aluminum for example, AI/AI(AIMo)/AI.
• layers of aluminum and molybdenum-aluminum may be stacked onto one another, and/or may be sandwiched between the power semiconductor chip and the top electrode- baseplate.
• aluminium may form a conductive alloy, particularly an eutectic alloy, in combination with the bulk material of the semiconductor device (for example, silicon).
• molybdenum may further comprise a coefficient of thermal expansion of about 5 ppm/K which may be close compared to the coefficient of thermal expansion of silicon (3 ppm/K) such that the mechanical stability of the power semiconductor module may be improved.
• the first preform may have a thickness which is at least 50% of the thickness of the power semiconductor chip and/or may have a thickness of at least 0.1 mm, more preferable of at least 0.5mm and most preferably of at least 0.8mm.
• the first preform may be made of aluminium, silver, gold, copper and/or magnesium
• the second preform may be made of aluminum-graphite, copper-graphite, copper-molybdenum or molybdenum (particularly having a coefficient of thermal expansion between 3 to 8 ppm/K).
• these materials may represent cost- effective and easily processible materials when designing the first and second preforms.
• the first preform may have a thickness which is at least 50% of the thickness of the power semiconductor chip and/or may have a thickness of at least 0.1 mm, more preferable of at least 0.5mm and most preferably of at least 0.8mm.
• the aluminium-graphite may comprise an aluminium skin or outer surface portion of the first (bulk) preform which may increase an amount of aluminium of the alloy formed when heat impacts the first preform in a failure event. Accordingly, the alloy formed by the first preform and the power semiconductor chip may be further improved.
• An aluminium foil may be arranged between the bottom electrode- baseplate and the bottom electrode of the power semiconductor chip, which may allow for providing additional aluminium from a bottom side of the power semiconductor chip for the creation of the conductive alloy.
• the conductive path over or through the semiconductor chip may be improved, thereby further improving a short circuit failure mode of the power semiconductor module.
• a lower side of the aluminium foil may be connected to the bottom electrode-baseplate via a ((silver) sintered) bonding layer, and the upper side of the aluminium foil may be connected to the bottom electrode of the power semiconductor chip by another ((silver) sintered) bonding layer.
• manufacturing of the power semiconductor module may be facilitated in that a conventional connection technique may be used for connecting various components of the power semiconductor module to one another.
• the method may be further facilitated in that one common connection technique may be employed for these layers.
• the aluminium foil is a inherent part of the bottom electrode-baseplate so that the surface of the bottom electrode-baseplate towards the stack or towards the power
• semiconductor chip is formed by the aluminium foil.
• the power semiconductor chip may be embedded in silicone gel.
• This silicone gel may provide a protection of the power semiconductor chip against its environment and may provide an electrical insulation of the power semiconductor chip.
• the silicone gel may fill up open spaces of a housing of the power semiconductor module.
• the power semiconductor module may comprise a package casing or package housing which may withstand the failure event and the formation of the alloy as described above, since temperature caused by the failure event and impacting the power semiconductor module may be dissipated over the housing to the environment.
• the package may also be configured for withstanding an overpressure which may develop in the power semiconductor module owing to the failure event of the power semiconductor chip.
• the bottom electrode-baseplate and/or the top electrode-baseplate may be configured for being cooled (particularly by a water cooling system or an air cooling system) such that a double-side cooled power semiconductor module comprising SCFM capability may be provided. Accordingly, a higher switching power per power semiconductor chip material area may be provided owing to the cooling of the top electrode- baseplate and the bottom-electrode base plate. Further, a number of used power semiconductor modules in the electronic power apparatus may be reduced. Further, since the power semiconductor chip may be connected to the top and bottom electrode-baseplates by bonding, the semiconductor chip may be connected to two large thermal masses such that heat pulses may be effectively buffered by thermal capacitances of the top and bottom electrode-baseplates. Accordingly, a cooling system connected to the top and bottom electrode-baseplates may be designed in a less efficient way, thereby further reducing costs.
• the bottom electrode-baseplate, the top electrode-baseplate, the power semiconductor chip, the first preform and/or the second preform may comprise a surface layer which may be, for example, formed by electroplating and may serve for protecting a surface of the respective component against damages and/or to reduce electrical resistance.
• a respective bonding layer is formed between the surface layer of the component and an adjacent component.
• the power semiconductor module may further comprise an at least another power semiconductor chip (or a plurality of another power semiconductor chips) which is (or are) connected to the bottom electrode- baseplate and the top electrode-baseplate in a similar way as described above with respect the power semiconductor chip.
• an at least another power semiconductor chip or a plurality of another power semiconductor chips which is (or are) connected to the bottom electrode- baseplate and the top electrode-baseplate in a similar way as described above with respect the power semiconductor chip.
• one or more of the above described measures and technical effects may apply to such a power semiconductor module.
• the power semiconductor chips of one or more of the power semiconductor modules may be connected in parallel to one another.
• the electronic power apparatus may comprise a plurality of power semiconductor modules each of which comprising one or more power semiconductor chips.
• the power semiconductor chips of one or of more power semiconductor modules may be connected in parallel to one another, and the power semiconductor modules may be connected in series to one another. Accordingly, in a case of a failure of one of the power semiconductor chips of one of the power semiconductor modules, the other power semiconductor modules may provide a current switching or current blocking capability of the electronic power apparatus.
• the power semiconductor modules may be stacked above one another such that the electronic power apparatus may comprise a compact design.
• the electronic power apparatus may be configured as a direct current (DC) circuit breaker apparatus. Accordingly, by designing the power semiconductor modules of the DC circuit breaker apparatus with a SCFM capability, the DC circuit breaker apparatus may be operable despite a failure event of one of its power semiconductor modules. In particular, since the power semiconductor module may represent a large amount of the manufacturing costs of the DC circuit breaker apparatus, reducing the manufacturing costs of the DC circuit breaker apparatus by about more than 50 per cent in comparison to a DC circuit breaker apparatus comprising pressure based power semiconductor modules may be accomplished.
• DC direct current
• the reduced height of the power semiconductor modules may cause the electronic power apparatus to comprise a compact shape.
• the DC breaker apparatus may be usable in High Voltage DC (HVDC) transmission networks.
• HVDC High Voltage DC
• a lifetime of the short circuit failure mode of the DC circuit breaker apparatus may be sufficiently long even being shorter in comparison to a lifetime of a short circuit failure mode of a pressure based power semiconductor module or electronic power apparatus.
• the electronic power apparatus may comprise a bypassing functionality configured for bypassing a failed power semiconductor module and thus may provide another short circuit failure mode
• the bypassing functionality may comprise a switching unit being electrically connected in parallel to power semiconductor module of the electronic power apparatus or in parallel to the electronic power apparatus.
• the switching unit may either form part of the electronic power apparatus or may be embodied as a separate unit.
• the switching unit may be mechanically operated using, for example, hydraulically generated pressure, or may be electrically operated.
• the switching unit may be embodied as a controllable relay.
• bypassing functionality may comprise a driving gate unit configured for permanently switching on the another power semiconductor chips distinct of the failed power semiconductor chip such that a current may be distributed along all power semiconductor chips instead of only along the failed power semiconductor chip. Thus, a lifetime of the failed power semiconductor module may be prolonged.
• the latter described bypassing functionality may similarly apply to power semiconductor modules comprising diodes.
• the method may further comprise providing a second preform made of material being configured for compensating a thermal expansion mismatch between the power semiconductor chip and the first preform, and bonding (particularly sintering) the second preform to the subassembly.
• this measure and the accordingly manufactured power semiconductor module may comprise the above described technical effects and advantages.
• an aluminum foil may be connected to the bottom electrode- baseplate and the semiconductor chip by bonding, particularly by (silver) sintering.
• the sintering may comprise low temperature bonding (LTB) or nanosintering, thereby facilitating the method by using conventional bonding techniques.
• LTB low temperature bonding
• nanosintering thereby facilitating the method by using conventional bonding techniques.
• the bottom electrode-baseplate, the power semiconductor chip, and the first preform may be bonded, particularly sintered, to one another in one step particularly using a respective fixture tool.
• the manufacturing process may be speeded up.
• the first and/or second preforms may be bonded, particularly sintered, to the power semiconductor chip, and afterwards the power semiconductor chip including the first and/or second preforms may be bonded, particularly sintered, to the bottom electrode-baseplate.
• a relative arrangement of the fragile power semiconductor chip and the first and/or second preforms may be firstly set before connecting the power semiconductor chip to the bottom electrode- baseplate.
• the first and/or second preforms may be bonded, particularly sintered, to one another, and afterwards to the power semiconductor chip particularly using a subsequent bonding step, particularly sintering step, whereby contamination of the power semiconductor chip edges may be prevented which may occur when bonding, particularly sintering, the combined first and second preforms to the power semiconductor chip.
• a sequence of bonding the bottom electrode-baseplate, the power semiconductor chip, the first preform, the second preform, and/or the aluminium foil to one another may be arbitrarily.
• components of the power semiconductor module may be configured for being withstanding short circuit events in that a degree of strength of the sintered bonding layers between the respective components of the power semiconductor module may be sufficiently strong.
• the power semiconductor module may be configured for
• the short circuit may propagate within the failed power semiconductor module and eventually may move to another power semiconductor module of the electronic power apparatus.
• the power semiconductor module may comprise a
• cooling of the power semiconductor chips may be improved, thereby reducing the heat impact on the power semiconductor module during the operation and supporting to prevent failure events.
• Figures 1 to 4 show perspective views of steps of a method of
• Figure 5 shows a schematic cross-sectional view of an embodiment of the power semiconductor module, which may be used in a electronic power apparatus according to an exemplary embodiment of the invention.
• Figure 6 shows an enlarged view of a power semiconductor module of Figure 5.
• Figure 7 shows a power semiconductor module of a DC circuit breaker apparatus according to another exemplary embodiment of the invention.
• the electronic power apparatus is usable in high power applications, and is configured for withstanding heat impacted failure of one of its power semiconductor chips such that an operation of the electronic power apparatus is maintained despite of the failure of the one of its power semiconductor modules.
• a bottom electrode-baseplate 102 In a first step of the method, a bottom electrode-baseplate 102, a plurality of power semiconductor chips 104a-f, and a plurality of preforms 106a-f are provided.
• the bottom electrode-baseplate 102 is made of copper- molybdenum.
• a part of the power semiconductor chips 104a-f of the plurality of power semiconductor chips 104a-f are configured as switching components in the form of silicone based IGBTs and another part of the power semiconductor chips 104a-f of the plurality of power semiconductor chips 104a-f are configured as free-wheeling diodes. It is also possible that all the semiconductor chips 104a-f are of the same type.
• each first preform 106a-f of the plurality of first preforms 106a-f are identically designed with respect to one another, and are made of aluminium- graphite.
• the thickness of the first preform may have at least 50% of the thickness of the power semiconductor chip 104a-f and/or may have a thickness of at least 0.1 mm, more preferable of at least 0.5mm and most preferably of at least 0.8mm.
• the thickness of the first preform106a-f depends on the thickness of the power semiconductor chip 104a-f, which again depends on the electric specification, i.e. on the blocking voltage of the power semiconductor chip 104a-f.
• the first preform must provide enough materiel to form a conductive channel if the chip fails.
• a bottom electrode of each of the power semiconductor chips 104a-f of the plurality of semiconductor chips 104a-f is bonded to a respective upper side of the bottom electrode-baseplate 102 using a silver sintering process. Accordingly, a first silver bonding layer is formed between the upper side of portions of the bottom electrode-baseplate 102 and the respective lower electrode of each of the power semiconductor chips 104a-f. Next, an upper electrode of each of the power semiconductor chips 104a-f is sintered to a lower side of a respective one of the preforms 106a- f. A used sinter material is made of silver. Accordingly, a second silver bonding layer is formed between the upper electrode of the power semiconductor chips 104a-f and the lower side of the preforms 106a-f.
• a top electrode- baseplate 108 made of copper-graphite is soldered to the upper sides of the preforms 106a-f such that a third soldered bonding layer is formed between each of the preforms 106a-f and respective portion of the top electrode-baseplate 208.
• stacks 209a-f are formed each of which comprising a single power semiconductor chip 104a-f and one of the first preforms 106a-f.
• the power semiconductor chip 104a-f is bonded to the preform 106a-f.
• the power semiconductor module thus comprises the bottom electrode-baseplate 102 bonded to the bottom element within the stack 209a-f.
• the bottom element within the stack 209a-f is the power semiconductor chip104a-f.
• the top element within the stack 209a-f is bonded to the top electrode-baseplate 108.
• the top element is the preform 106a-f.
• a rectangularly shaped, framed housing 310 is attached to the circumference of the upper surface of the bottom electrode-baseplate 102.
• An upper inner surface portion of an inner surface of the housing 310 abuts against lateral sides of the top electrode-baseplate 208.
• silicone gel 311 is inserted in a space formed between the bottom electrode-baseplate 102, the top electrode-baseplate 208 and the housing 310 such that the semiconductor chips 106a-f are embedded in the silicone gel 31 1.
• a plurality of the above described power semiconductor modules comprising the stacks 209a-f arranged in the housing 310 and covered by the silicone gel 31 1 are manufactured and are stacked above one another.
• the stacks of one power semiconductor module are connected in parallel to one another, and the plurality of power semiconductor modules are connected in series to one another.
• the electronic power apparatus now referenced by a reference numeral 312, is manufactured.
• Figure 4 shows an intermediate method step which is executed between the method step illustrated in Figure 1 and the method step illustrated in Figure 2.
• respective bonding wires 413a-d are attached to gate contacts 414a-c of the power semiconductor chips 106a, c, d, e and to a conductive lead 415 which is arranged along a longitudinal extension of the bottom electrode-baseplate 102 between the power semiconductor chips 106a, c, e and the power semiconductor chips 106b, d, f.
• the conductive lead 415 forms part of an electrical connection to the gate contacts 414a-c of the power semiconductor chips 104a-f from auxiliary terminals used for a control of the power semiconductor chips. It is noted that the auxiliary terminals are not shown in Figure 4.
• bonding wires 413a-d are shown in Figure 4 for illustration purposes, a suitable number of bonding wires are attached to the respective gate contacts of the power semiconductor chips 104a-f such that the power semiconductor chips 104a-f of the assembled power electronic module and/or electronic power apparatus 312 are electrically connected in parallel to one another.
• the method may comprise a step of silver sintering an aluminium foil to the upper side of the bottom electrode-baseplate 102 prior to connecting the semiconductor chips 104a-f to the bottom electrode- baseplate 102.
• the aluminium foil may extend along an entire surface of the bottom electrode-baseplate 102, and may be present between connection regions of the semiconductor chips 104a-f to the bottom electrode-baseplate 102.
• the bottom and top electrode-baseplates 102, 208 Prior to operation of the power electronic module and / or electronic power apparatus 312, the bottom and top electrode-baseplates 102, 208 are connected to a water cooling system such that the bottom electrode- baseplate 102 and the top electrode-baseplate 208 may be cooled, in order to improve the operation performance of the electronic power apparatus 312.
• Gate voltages are applied to respective gate contacts of the power semiconductor chips 104a-f of the power semiconductor module. Afterwards, electric current is applied to the bottom electrode- baseplate 102 such that a current is transferred to the top electrode- baseplate 208 via each of the stacks 209a-f comprising a power semiconductor chip.
• one of the power semiconductor chips 104a-f is impacted by a heat impulse caused by, for example, a cosmic ray event or a flash-over between respective portions of the bottom electrode-baseplate 102 and the top electrode-baseplate 108.
• the power semiconductor chip 104a is affected by such a heat impact and the power semiconductor chip 104a comprises an IGBT.
• the heat is transferred to the material of the preform 106a and the bulk material of the power semiconductor chip 104a such that an electrically conductive alloy or even eutectic alloy starts to form at an interface between the upper side of the power semiconductor chip 104a and the lower side of the preform 106a.
• a respective melting process results in an electrically conductive channel through the semiconductor chip 104a, whereby a stable short circuit failure mode of the
• the power semiconductor module 512 comprises a bottom electrode- baseplate 502 and a top electrode-baseplate 508 both made of
• a plurality of silicon based semiconductor chips 504a, b, a respective plurality of first preforms 506a, b made of aluminium and a plurality of second preforms 516a, b made of molybdenum are sandwiched between the bottom electrode-baseplate 502 and the top electrode- baseplate 508 and form respective stacks 517a, b between the bottom electrode-baseplate 502 and the top electrode-baseplate 508.
• a first silver bonding layer 618 is sintered between the bottom electrode-baseplate 502 and the lower electrode of the power semiconductor chip 504a ( Figure 6).
• a second silver bonding layer 620 is sintered between the upper electrode of the power semiconductor chip 504a and the lower side of the first preform 506a.
• a third silver bonding layer 622 is sintered between the upper side of the first preform 506a and the lower side of the second preform 516a. Further, a layer 624 of solder is soldered between the upper side of the second preform 516a and the lower side of the top electrode- baseplate 508. Afterwards, the power semiconductor chips 509a, b are embedded in silicone gel 61 1.
• the stack 509a comprises a further improved mechanical stability and reliability, since a coefficient of thermal expansion of the second preform 516a is close to a coefficient of thermal expansion of the silicon material of the power semiconductor chip 506a.
• the thickness of the first preform 506a, 506b may have at least 50% of the thickness of the power semiconductor chip 104a-f and/or may have a thickness of at least 0.1 mm, more preferable of at least 0.5mm and most preferably of at least 0.8mm.
• the thickness of the first preform 506a, 506b depends on the thickness of the power semiconductor chip 504a, 504b, which again depends on the electric specification, i.e. on the blocking voltage of the power semiconductor chip 504a, 504b.
• the first preform must provide enough materiel to form a conductive channel if the chip fails.
• a respective method of manufacturing the power semiconductor module is described in the following. First, the bottom electrode-baseplate 502, the power semiconductor chips 504a, b, the first preforms 506a, b, and the second preforms 516a, b are stacked onto one another. The latter components are then sintered to one another in one sintering step using the silver sintering materials. Alternatively, the components are sintered to one another in subsequent sintering steps.
• the bottom electrode-baseplate 502 is sintered to the power semiconductor chips 509a, b, and afterwards, in one sintering step, the first and second preforms 506a, b, 516a, b are sintered to one another and to the power semiconductor chip 506a, b, respectively.
• the DC breaker apparatus comprises a mechanical disconnecting device, a small switching device, and a plurality of identically designed power semiconductor modules 712 each one which comprising the stacks 709a-f, preferably at least two stacks 709a-f in parallel in each power semiconductor module 217.
• the power semiconductor modules are stacked above one another and are connected in series to one another.
• the mechanical disconnecting device and the small switching device are arranged in series and in a bypass line bypassing the plurality of power semiconductor modules.
• the small switching device is identically constructed compared to the power semiconductor module with stacks 509a, b illustrated in Figures 5 and 6, and the stacks 709a-f are similarly constructed compared to the stacks 209a-f of the power semiconductor module 312 illustrated in Figures 1 to 4.
• the power semiconductor chips of the stacks 709a-f comprise BIGTs instead of the IGBTs which are embedded in silicone gel 71 1.
• top and bottom electrode-baseplates of the small switching device are cooled using an air cooling device, whereas top and bottom electrode-baseplates 702, 708 of the stacks 709a-f are not cooled.
• Current is transferred via the bypass line comprising the mechanical switching device and the small switching device.
• the power semiconductor modules are controlled to switch the DC circuit breaker apparatus 712, and current is transferred via the power semiconductor modules and thus the stacks 709a-f for about 10 milliseconds. Accordingly, an inherent cooling capability of the stacks 709a-f is sufficient, since a time of the current transfer via the stacks 709a- f is extremely short.
• the invention here is on a concept of a power semiconductor module with internal SCFM capability without dry contacts and mechanical components developing high pressure and with double side cooling of chips in the power semiconductor module.
• the proposed power semiconductor module basically consists of two
• the semiconductor chips and the additional elements form a stack. At least one stack is placed between the two electrically conductive baseplates. It is however preferred to place at least two stacks between the two baseplates.
• the additional elements are able to form a eutectic alloy together with silicon. To attach adjacent parts, joining methods such as soldering, brazing or sintering (etc.) are used. In an application the power semiconductor module is sandwiched between two coolers which also serve as positive and negative electrodes. [00101] It has been shown experimentally that in such a structure, a SCFM is formed after a chip failure. The SCFM has been shown to possess a certain lifetime, at least several seconds.
• the advantages of the described package are: 1. Lower material and production cost than for a StakPak; 2. Higher switching power per silicon area due to the improved cooling; 3. Less package volume (in particular: less height) of the power semiconductor module; 4. High reliability under normal operation conditions (no dry contacts, CTE- matched materials, low chip temperature ripples due to large thermal masses directly attached to the chip); 5. SCFM capability.
• Preferred embodiments may be as follows.
• the power semiconductor module includes a power semiconductor chip, a bottom electrically and thermally conductive electrode-baseplate, a top electrically and thermally conductive electrode-baseplate, a preform made of material supporting creation of spot in a case of a failure (creation of eutectic alloy with Si with lower melting temperature).
• the bottom electrode of the power semiconductor chips is thermally and electrically connected to the bottom electrode-baseplate via a first bonding layer.
• the top electrode of the power semiconductor chip is thermally and electrically connected to the preform via a second bonding layer.
• the other side of the preform is thermally and electrically connected to the top electrode-baseplate via a third bonding layer.
• module includes a power semiconductor chip, a bottom electrically and thermally conductive electrode-baseplate, a top electrically and thermally conductive electrode-baseplate, a first preform made of material supporting creation of spot in a case of a failure (creation of eutectic alloy with Si with lower melting temperature), a second preform made of material compensating CTE mismatch between a power semiconductor chip and the first preform.
• the bottom electrode of the power semiconductor chips is thermally and electrically connected to the bottom electrode-baseplate via a first bonding layer.
• the top electrode of the power semiconductor chip is thermally and electrically connected to the first preform via a second bonding layer.
• the other side of the first preform is thermally and electrically connected to the second preform via a fourth bonding layer.
• the other side of the second preform is thermally and electrically connected to the top baseplate via a third bonding layer.
• a 3. embodiment may relate to a power semiconductor module as
• a 4. embodiment may relate to a power semiconductor module as
• the first preform is bonded to the top electrode of the power semiconductor chip via a silver layer.
• a 5. embodiment may relate to a power semiconductor module as
• a 6. embodiment may relate to a power semiconductor module as
• top electrode is bonded to the first preform or the second preform via a layer of solder.
• a 7. embodiment may relate to a power semiconductor device as
• a 8. embodiment may relate to a power semiconductor module as described in one of the previous embodiments, wherein the baseplates could be made of Molybdenum, Al-graphite, Cu-graphite, Cu-molybdenum etc. (materials with CTE close enough to silicon).
• a 9. embodiment may relate to a power semiconductor module as
• the first preform is made of e.g. Al-graphite.
• a 10. embodiment may relate to a power semiconductor module as
• the preform is made of laminate material (sandwich) - AI/Mo(AIMo)AI.
• a 1 1. embodiment may relate to a power semiconductor module as
• the first preform is made of Aluminium, Silver, Gold;
• a 12. embodiment may relate to a power semiconductor module as
• Aluminium skin increasing amount of Aluminium available for hot spot.
• a 13. embodiment may relate to a power semiconductor device as
• a 14. embodiment may relate to a power semiconductor module as
• a 15. embodiment may relate to a power semiconductor module as
• a 16. embodiment may relate to a power semiconductor module as
• a 17. embodiment may relate to a power semiconductor module as
• the structure has a package-case withstanding the failure event and formation of the hot spot.
• a subassembly - bottom electrode- baseplate, power semiconductor chip and preform is prepared by the silver sintering process (eventually also Al foil from 13) and the top electrode- baseplateof the power semiconductor module is bonded using soldering.
• the subassembly - bottom electrode- baseplate, chip, first and second preform is prepared by the sintering process (eventually also Al foil from 13) and the top electrode-baseplate is bonded using soldering.
• a 20. embodiment may relate to the method as described in the 18 or 19 embodiment, wherein sintering can be LTB (low-temperature bonding) or nanosintering.
• a 21. embodiment may relate to the method as described in one of the embodiment 18 to 20, wherein all components can be sintered in one step using fixture.
• a 22. embodiment may relate to the method as described in one of the embodiment 18 to 21 , wherein the preforms can be sintered on the power semiconductor chips and afterwards the power semiconductor chips with preforms are sintered to the bottom electrode.
• a 23. embodiment may relate to the method as described in one of the embodiment 19 to 22, wherein preforms are sintered together and than bonded to power semiconductor chip surface in the next sintering step (less contamination of chip edges).
• Sintered bonds should be sufficiently strong to withstand SC event.
• the presspack module should be in principle able to handle a transition event.
• a double-side cooled module of press-pack type with an internal short circuit failure mode capability is presented. Bonding technologies which only recently got more attention in power electronics in a combination with CTE (coefficient of thermal expansion) matched emitter or top electrode- baseplate and collector or bottom electrode-baseplates are proposed for its fabrication. This approach should allow fabrication of very compact and relatively simple power semiconductor modules without internal dry contacts suitable especially for multilevel converter topologies applied in a power transmission area.
• CTE coefficient of thermal expansion
• Figures 1 to 4 are showing an example of a small double side cooled power semiconductor module with SCFM capability according to the 1. embodiment. This power semiconductor module was designed with the aim to check feasibility of the concept.
• Figure 1 A bottom electrode- baseplate with bonded power semiconductor chips and first preforms supporting SCFM - hot spot formation. Materials of the first preform and power semiconductor chip form a eutectic alloy with a low-melting temperature. CTE of preform and power semiconductor chip is sufficiently close.
• Figure 2 A top electrode-baseplate was bonded to the top contact of the chip and/or the preform.
• Figure 3 The finalized power
• Figure 4 An example of a possible gate wiring of the power semiconductor module.
• Figures 5, 6 may show a schematic cross-section and a detailed of a part of a power semiconductor module with SCFM capability according to the 2. embodiment.
• CTE reasonably matched bottom electrode-baseplate e.g. Molybdenum
• the component or first preform made of metal suitable for SCFM capability e.g. Aluminium
• SCFM capability e.g. Aluminium
• another, second preform is bonded on the other side of the first preform.
• the second preform has CTE close to Silicon.
• the top electrode- baseplate is soldered to the second preform.
• Another exemplary embodiment refers to a DC Circuit Breaker containing double-side cooled BIGT packages.
• a background for this embodiment may be as follows.
• DC Circuit Breakers containing IGBT and diodes as conducting / blocking elements show potential to be used in future HVDC transmission networks. Particularly promising properties are achievable using BIGT chips instead of the IGBT / diode combination since here, the health of the IGBTs and diodes can be monitored via the BIGT's gate.
• the short-circuit mode does not need to possess a long lifetime since the power semiconductor chips are activated only for a short time during a switching event (total required short-circuit lifetime within 30 years: > 10 s).
• a problem may be as follows.
• the StakPak construction is designed for a long short-circuit lifetime and is hence a complex and expensive construction.
• the cost of the StakPak power semiconductor modules significantly contributes to the whole DC circuit breaker cost.
• the power semiconductor chips are attached to a relatively low thermal mass (Moly base plate at the bottom side of the chips). This means that a transient heat load is not buffered optimally.
• the maximum duration of a high current pulse (e.g. 8-10 kA) through the chips is limited.
• Such a double-side cooled power semiconductor module basically consists of one or several BIGT chips which are sandwiched between two electrically conductive plates - electrode-baseplates - to which the power semiconductor chips are attached. Besides the top and bottom electrode-baseplates, additional components (such as spacer layers) could be included.
• the power semiconductor module can be combined with some other short-circuit functionality that could e.g. be triggered by the driving gate unit.
• This invention combines several novel technologies (double-side cooled packages, BIGT chips, transistor-based DC circuit breaker) to obtain a substantial cost and/or performance improvement of DC circuit breakers.
• a business benefit may be as follows.
• the power semiconductor module itself is significantly cheaper than the StakPak due to its simple construction. Since the power semiconductor module represents a large amount of the total DC circuit breaker cost (> 50% (70%), depending what you include in the costs) the cost of the entire circuit breaker can be significantly reduced.
• the double-side cooled power semiconductor module are very flat

Priority Applications (1)

Applications Claiming Priority (5)

Publications (2)

Family

ID=45562353

Family Applications (1)

Country Status (3)

Families Citing this family (12)

Family Cites Families (9)

• 2012
  • 2012-02-08 EP EP12702294.5A patent/EP2673803B1/de active Active
  • 2012-02-08 CN CN201280008105.0A patent/CN103370786B/zh active Active
  • 2012-02-08 WO PCT/EP2012/052118 patent/WO2012107482A2/en not_active Ceased

Also Published As

Similar Documents

Legal Events