EP2668753B1 - Appareil et procédé permettant de recevoir et de réacheminer des paquets de données - Google Patents

Appareil et procédé permettant de recevoir et de réacheminer des paquets de données Download PDF

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Publication number
EP2668753B1
EP2668753B1 EP12700231.9A EP12700231A EP2668753B1 EP 2668753 B1 EP2668753 B1 EP 2668753B1 EP 12700231 A EP12700231 A EP 12700231A EP 2668753 B1 EP2668753 B1 EP 2668753B1
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Prior art keywords
data
information
address
receiving
addresses
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German (de)
English (en)
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EP2668753A1 (fr
Inventor
Søren KRAGH
Peter Ekner
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Napatech AS
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Napatech AS
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L67/00—Network arrangements or protocols for supporting network services or applications
    • H04L67/01—Protocols
    • H04L67/02—Protocols based on web technology, e.g. hypertext transfer protocol [HTTP]
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/10—Packet switching elements characterised by the switching fabric construction
    • H04L49/103—Packet switching elements characterised by the switching fabric construction using a shared central buffer; using a shared memory
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/90—Buffering arrangements
    • H04L49/9047—Buffering arrangements including multiple buffers, e.g. buffer pools
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/10—Packet switching elements characterised by the switching fabric construction
    • H04L49/113—Arrangements for redundant switching, e.g. using parallel planes
    • H04L49/118—Address processing within a device, e.g. using internal ID or tags for routing within a switch

Definitions

  • the present invention relates to an apparatus and a method for receiving and forwarding data packets and in particular to receiving data packets on a plurality of separate adapters each forwarding the data packets on a common bus and to a common storage.
  • Technology of this type may be seen in US2005/207423
  • the invention relates to an apparatus according to claim 1.
  • a data packet may be any type of a data unit to be transmitted on or transported by a network, data cable, data bus, trunk, or the like.
  • a data unit conforms to one or more data standards, such as the Ethernet standard being an umbrella under which a number of different standards or data packet types exist, such as UDP and TCP data packets.
  • a data packet usually has a number of different information items or types, such as address data, payload or the like, which are each positioned at well defined or known positions within the data packet.
  • Such positions and types will typically differ from data packet type to data packet type, but usually, the data packet type, and thus the positions of individual contents thereof, may be determined from the actual data packet, where after the individual data items, such as address data and/or payload, may be derived, altered, and/or used in the analysis.
  • the type or standard may be derived directly from the data packet, such as when a particular data item of the packet identifies the type/standard, or may be derived from data derived from the data packet, such as on the basis of recognition of types and positions of data items of the data packet and subsequently determination of type(s) or standard(s) of data packet in which such data may be found at such position(s).
  • Data packets as received may be pre-ordered in a multiple of manners and for a number of reasons.
  • data exchange between computers is a file transfer, TCP transfer, VoIP or the like, where the order of the individual packets is important.
  • transfers are called streams.
  • a stream of data packets normally is a sequence of data packets transmitted from a single transmitter to one or more receivers. These data packets relate to e.g. a single file or the like transmitted in smaller portions, being the payload of the packets. The transmitter and receiver, or any intermediate network elements, will usually then have addresses also represented in the packet. In addition, other stream identifying information may be present in the data packet, depending on the individual data packet standard.
  • a stream may be identified on the basis of e.g. the addresses and/or the stream identifying information, whereby, if used consistently, the same information may be derived, and any subsequent process may identify the stream merely from the information.
  • data packets may be provided with information therein determining the order thereof, such as a sequence number or a time stamp. Thus, this information may be used for ordering the packets.
  • receiving and forwarding elements are physically separate, whereby these may be removed or replaced if desired.
  • more or fewer such elements may be provided in order to adapt the functionality and capabilities of the apparatus.
  • the controlling unit may be a separate circuit or may be connected to or even embodied in one of the receiving and forwarding elements.
  • the remaining data receiving and forwarding elements may be identical.
  • the data receiving and forwarding elements and the controlling unit may all be fixed to each other and may be provided in the same housing or server. These may be made of individual circuits or network units scattered over a given area and connected (via wires or wirelessly) to each other via one or more networks, such as or including the WWW, so as to be able to exchange data. This exchange may be under any data transfer protocol, such as TCP, Ethernet, Bluetooth or the like, and using any type of data transfer, wired or wireless.
  • the individual means of the system may each be formed by one or more processors, such as FPGAs, ASICs or the like, or a single such processor may form multiple of the means and perform multiple of the steps.
  • the storage may be any form of storing unit, such as a monolithic storing unit or one composed by a number of storing elements separated in space.
  • Usual storing technologies are based on hard drives, floppy discs, RAM, ROM, PROM, EPROM, EEPROM, Flash, memory cards, CD-ROM, DVD, memory cards, or the like.
  • the address will describe both the identity of the actual storing unit and the "local address" therein.
  • the functionality of the system need not merely be the forwarding of data. Additional processing may, as will be described further below, be performed, such as the analysis of the data packets.
  • the receiving means usually will be a type of networking element adapted to receive data packets from a network.
  • this means may have a PHY, a MAC or the like, if Ethernet data packets are to be received.
  • PHY Physical Uplink Control
  • MAC Network Control Protocol
  • the receiving means may store the data packets or output these without delay for further processing/storing/transport. Most often, a buffer is provided to take into account delays, but this is not a requirement.
  • the first information, the address and the request information may be forwarded and transmitted on a communication means, such as a bus, separate from that used by the storing means for storing the at least part of the data packet and the reply information and used by the controller to read the reply information.
  • a communication means such as a bus
  • the first information may relate to any relevant feature of the packet, such an addressee thereof (MAC or IP address, receiver or transmitter), a size/length thereof, its belonging to or a position thereof in - a stream, its time of arrival, or the like. Naturally, any number of such features may form part of the first information.
  • the address determined by the controller and received by the first receiving means may be any type of address, such as an absolute address in a single storage or multiple, interconnected storages, a relative address, such as an address relating to the storage or an address in the storage. It is noted that an address may be further translated in order to obtain the actual address for storage.
  • the address may be the identity of e.g. a queue or address space or area in the storage within which the data is stored, such as in a predetermined order.
  • the storing means thus may select the parts of the data packet, if not the whole data packet, to be stored and store this. Naturally, if the data or part thereof is not desired transmitted to e.g. the receiver, the address portions thereof may be deleted or not stored in order to save space in the storage.
  • the reply information represents information as to received addresses at which at least part of the data packets have been stored.
  • the controlling unit stores or holds the addresses which have been reserved or forwarded, such as to the individual receiving and forwarding element. These addresses, or information representing these, may be held in any type of storage and may be held in separate storages for each receiving and forwarding element or in a single storage. These addresses may be represented themselves, or information may be held from which the addresses may be derived.
  • An advantage of the storing means outputting the reply information to the storage is that when outputting the reply information, the storing means is well aware of which addresses have already been at least forwarded to the storage. Thus, updated information is available.
  • the reply information may comprise the actual, received and used or not-yet-used addresses.
  • the reply information need be only a number relating to the number of received and used addresses, such as the number of addresses used since, for example, the last transmission of reply information.
  • the reply information may be the number of received addresses which have, in fact, not yet been used, such as at the time of storing the reply information. From this information, the controlling unit is able to determine at which addresses in the storage, data is present.
  • the determining means may determine the address in accordance with any principle or policy. It may be desired to store the data in a given order, such as the order of time or receipt, and/or it may be desired to store data relating to certain addressees or flows/streams separately. As will be described further below, a number of queues may be implemented, so that data may be stored in queues in accordance with certain policies.
  • the address determination is performed on the basis of the first information, and then, the first information is made to comprise the information required for the address determination.
  • multiple addresses may be allocated to one data packet, depending on the size thereof. In this situation, the size or the number of addresses required may form part of the first information.
  • the maintaining or updating of information relating to addresses in which data packets, or the at least part thereof, are stored may be performed in order to know which addresses are not in use, and therefore preferably used by the determining means determining the addresses. In this manner, an address is not allocated which is already in use.
  • Other users of such information may be processes or processors reading information from the storage and thus freeing addresses for re-use and re-allocation by the determining means.
  • Such processes/processors require knowledge as to in which addresses valid data is present.
  • the information relating to addresses in which data packets are stored may represent this knowledge in a number of manners.
  • One manner is to store or know each address in which data is stored, or alternatively each address in which data is not stored.
  • One advantage of a queue is that only the end(s) of the queue are required in order to determine which part of or how much of a queue is allocated.
  • Any means may be used for transporting the (at least parts of) data packets and reply information to the storing means, read the reply information from the storing means and for transporting the first information, address and request information to/from the receiving and forwarding elements.
  • Such means may e.g. be selected so as to be able to support a varying number of receiving and forwarding elements. This may be the situation in both wireless communication and different types of wired data busses, such as ring busses and star-shaped busses as well as standard busses and be able to communicate any type of information or data on any protocol.
  • such means are a data bus common to the controlling unit and all receiving and forwarding means.
  • this transporting means is of a type where data is not allowed to over-take when forwarded thereto, it is clear that the reply information output by a storing means will be quite accurate in that this storing means will know to which addresses data has been forwarded at the time of outputting the reply information. Also, any storing delays will be taken into account in that the reply information, once stored in the storage, will indicate to the controlling unit exactly which addresses have now been used.
  • the storing means are adapted to store the reply information only after the at least part of the data packets have been stored, or at least forwarded to the transporting means, at all addresses received prior to receipt of the request information, the very existence of this reply information in the storage will be an indication that such addresses are now in use.
  • the controlling unit when the controlling unit is aware of which addresses were returned to each receiving and forwarding element prior to and/or after the outputting of the request information to that element, the controlling unit, when determining that the reply information is present in the storage, will known which addresses are now in use. It is noted that this is irrespective of any delays existing on the data path from the storing means to the storage.
  • each receiving and forwarding element further comprises means for determining a point in time of receipt/access of the data packet, the time determining means comprising clock means, the clock means of all time determining means being synchronized.
  • the time determining means comprising clock means, the clock means of all time determining means being synchronized.
  • Different synchronization manners may be adopted, such as simply providing a global synchronization or clocking signal.
  • the clocks of individual elements or circuits may be synchronized to one of the clocks, such as that of the controlling unit.
  • the time of arrival or time stamp may form part of the first information and thus be relayed to the controlling unit which may then use this information to allocate addresses so that the data packets are stored in the correct order.
  • one or more queues are defined in the storage as separate groups of addresses, the determining means of the controlling unit being adapted to determine, from the first information, a queue to which to add the pertaining data packet, and to select an address from the groups of addresses of the pertaining queue.
  • a queue is implemented as an ordered list where data is added to an end of the list and de-queued from the other end of the list.
  • the queue is implemented as a circular list.
  • the ends of the list thus may be identified by two pointers, one pointer identifying the next address to receive data (or the latest address used), and the other identifying the next address to be de-queued or the latest de-queued address.
  • the information as to which address in which data is stored thus may be represented by the pointers of the queues or may be used for generating, controlling or updating these pointers.
  • the determining means of the controlling unit may be adapted to determine an address in the determined queue so that the data packets are stored in the queue in an order of receipt/access.
  • This order of receipt/address may be that of receipt of the first information by the controlling unit or the receipt/address by the receiving and transmitting element.
  • the receiving and transmitting units preferably are adapted to determine the time of receipt of each data packet and forward this information in the first information in order for the determining means to be able to determine the address.
  • the assembly further comprises means for reading or de-queuing data from the storage, the reading means comprising means for outputting third information relating to one or more address(es) of the storing means, the data of which has been read/de-queued. Also this information is desired in determining in which addresses, data is stored, such as in the updating or managing of the pointers or end addresses of the queues. Naturally, this third information may be the individual addresses de-queued, or the third information may represent a plurality of addresses, such as an interval of de-queued addresses.
  • the controlling unit is adapted to hold, for each queue, a write pointer identifying a next address in which to add data and a read pointer identifying a next address to be read/de-queued from the queue, the reading/updating means being adapted to:
  • the reading/de-queuing means may actually be updating the read pointer(s) and merely forward a copy thereof as the third information to the controller.
  • the read pointers are maintained by the reading/de-queuing means and the write pointers by the controller, which then merely receives, from time to time, a copy of the updated read pointer(s).
  • the reading/updating means preferably is adapted to update the write pointer to an address only if reply information has been received representing all addresses between the read and write pointers.
  • the write pointer is still not updated, as this would include the "hole” or missing data packet in the queue. Then, when the missing data packet has been stored, the write pointer is updated to the next "hole” or the end of the queue.
  • This identification of "holes” may be performed by the controlling means and on the basis of the second information.
  • Another aspect of the invention relates to a method according to claim 9.
  • a receiving and forwarding element may be receiving/accessing one data packet, outputting first information relating to an earlier received/accessed data packet and receiving an address for an even earlier received/accessed data packet.
  • controlling unit may determine the addresses for multiple data packets simultaneously, and the step of receiving the reply information and updating the information relating to the addresses may be performed simultaneously to the other steps.
  • the number of receiving and forwarding elements may vary depending on the desired performance and bandwidth.
  • the storing step comprises storing the reply information only after the at least part of the data packets have been stored at all addresses received prior to receipt of the request information.
  • the storing step comprises all receiving and forwarding elements forwarding the data packets to the storage over a common bus which preferably is also used for storing and receiving the reply information.
  • this common bus is of a type where over-taking is not allowed when data has been transferred thereto, i.e. data or reply information from a storing means may not overtake each other between the individual storing means and the storage, the storage means will be able to provide exact information in the reply information as to which addresses are in use (or not in use).
  • the storage means will be able to provide exact information in the reply information as to which addresses are in use (or not in use).
  • data/reply information from one storing means overtakes that of another storing means, as long as the data/reply information from each storing means is stored in the order (in time) of providing to the bus.
  • the controller may, from the very presence of the reply information in the storage, determine or describe which addresses are now in use or not in use.
  • the addresses may be directly or indirectly provided in the reply information for the controller to use. Also in this situation is the non-overtaking transport desired.
  • the receiving and forwarding element further determines a point in time of receipt/access of the data packet, the time determining means comprising clock means, the clock means of all time determining means being synchronized. As mentioned above, different manners of obtaining this synchronization exist. Then, this point in time may form part of the first information, and the address determination may be based thereon.
  • a plurality of queues may be defined in the storage as separate groups of addresses, the determining step comprising determining, from the first information, a queue to which to add the pertaining data packet, and selecting an address from the groups of addresses of the pertaining queue.
  • the determining step preferably comprises determining an address in the determined queue so that the data packets are stored in the queue in an order of receipt/access.
  • the method further comprises the step of reading or de-queuing data from the storage, the reading step comprising outputting third information relating to one or more address(es) of the storing means, the data of which has been read/de-queued.
  • the third information may be output each time an address has been de-queued, when a predetermined number of addresses have been de-queued or periodically, for example.
  • the determining step comprises determining, for each queue, a write pointer identifying a next address in which to add data and a read pointer identifying a next address to be read/de-queued from the queue, the reading/updating step comprising:
  • the determining step may comprise updating the write pointer to an address only if reply information has been received representing all addresses between the read and write pointers.
  • FIG 1 an embodiment 10 of an apparatus for analyzing and forwarding data frames is illustrated having a number of adapters 12 each connected to and receiving data from a network, such as the WWW.
  • a system of this type may be used for receiving a large number of data packets and facilitate storage and/or forwarding thereof in a suitable manner.
  • These data packets usually are transmitted between pairs of computers or networks on a data connection monitored by the present system.
  • the data packets normally are not meant for nor addressed to or from the present system.
  • This data may, when stored, be processed by one or more subsequent processes or processors 34.
  • structured storing is desired in order to achieve swift, yet structured, retrieval of the data.
  • a plurality of processors is provided when a single processor does not suffice, whereby separate storing of data for each processor is desired.
  • the processors may be used for analyzing the data traffic, for storing the data and/or for transmitting the data to other network elements, computers or the like, depending on the result of the processing in the processors.
  • the data packets are parts of streams of data packets.
  • streams of data packets are exchanged.
  • This stream may be a file transfer or an exchange of audio/video, such as Voice over IP.
  • a stream is a sequence of data packets which are similar. The belonging of a data packet to a stream is determinable, and it is desired that all data packets of a stream are stored together, in the desired order, handled by the same subsequent process or processor and/or output in that order.
  • the belonging of a received data frame to a stream is determined from an analysis of the frame. This analysis is described in further detail below.
  • the present embodiment aims at providing a set-up in which multiple adapters 12 divide the task of analyzing the frames/packages and/or storing these.
  • the adapters 12 receive data frames from the network 14, such as the WWW, a trunk or network of any suitable type. Each adapter 12 receives a number of frames independently of the other adapters 12.
  • all adapters are identical and each comprises a so-called PHY 20, which is an element adapted to receive data frames from a network or data cable and a so-called MAC circuit 22 which converts the received frames to a standard usually used on data busses on e.g. computers.
  • PHY 20 is an element adapted to receive data frames from a network or data cable
  • MAC circuit 22 which converts the received frames to a standard usually used on data busses on e.g. computers.
  • a time stamp in the circuit 24, where after the frame is fed to an analyzing circuit 26 which derives data relating to the data frame, such as relating to a standard the frame conforms to, such as whether it is VLAN and/or MPLS tagged, and potentially address data there from.
  • data relating to the data frame such as relating to a standard the frame conforms to, such as whether it is VLAN and/or MPLS tagged, and potentially address data there from.
  • a plurality of different types of standards are known, each of which defines which types of data (address, encapsulation, payload, error correction etc) are present in the frame and where such data is present.
  • types of data may be derived.
  • the circuit 26 outputs data identifying the data frame, such as its belonging to a data packet stream, or a queue in a central storage. Then, the length of the data frame, the ID/queue identification and the time stamp of the data frame are transmitted, in a request circuit 28, to a central server memory allocator or controller 16, which returns an address within the storage 18 in which the data frame is to be stored. This address is returned to a transfer circuit 30 also receiving the data frame and which subsequently transmits the data frame to the identified address via a common data bus 32, such as running a PCI Express (PCIe) protocol.
  • PCIe PCI Express
  • This storing may be using Direct Memory Addressing, which means that the frame is stored directly at the desired address, and that no further analysis is required. This is the fastest manner of storing data in a data storage, but it requires that the physical address is known.
  • the circuit 28 may alternatively output, together with the time stamp and length of the packet, other information identifying the frame (type, addresses or the like), whereby the allocator itself will determine the queue to which the frame is to be added and thus derive the address at which the frame is to be stored.
  • the "out of band” communication between the allocator 16 and the adapters 12 may be a low bandwidth point-to-point communication, a daisy chain topology, or a ring topology. This communication, as is described further below, is also used for synchronizing the clocks of the time stamp circuits 24.
  • a suitable protocol for this communication may be a standard 64b/66b codec requiring approximately 1Gbps full duplex bandwidth per 10Gbps of Ethernet front port (PHY) bandwidth.
  • Another use of the communication between the allocator and the adapters 12 is that of keeping the allocator informed of the storing progress.
  • the allocator 16 is aware of which addresses in the storage 18 have been allocated and to which adapter 12. In order to determine which addresses are actually used, the allocator 16 transmits requests, such as in the form of request or idle packets, to the individual adapters 12. In response to a request, the adapter 12 will transmit a reply package to the storage 18 in a predetermined address. The adapter 12 is adapted to output the data packets and the response in the order of receipt of the individual addresses and the request, respectively.
  • An adapter 12 may not be able to immediately forward a data packet to the storage 18, even though one or more addresses in the storage 18 have been allocated for that data packet, as delays may occur, such as due to arbitration on the bus 32. However, as the data packets and the reply are output in order from the adapter 12, the storing of the reply will indicate that the data packets pertaining to all earlier received addresses have now been stored by that adapter 12.
  • Each adapter 12 may store its reply at a different address in order for the allocator 16 to determine which adapter 12 has forwarded a reply.
  • each request will have therein a number, which is copied into the reply, so that the allocator 16 can determine that an updated reply has been stored by comparing to the former number of that address.
  • the allocator 16 thus will monitor the addresses and determine when an update of a number exists, whereby an adapter 12 has stored data packets in all addresses received since the receipt of the request for that adapter 12 with the number just received in the reply.
  • the allocator 16 keeps track of all addresses output before and after the requests (including the numbers), the allocator 16 can determine which of the addresses in the storage are occupied, which have been forwarded to the adapters 12 but are still not in use, and which addresses are free.
  • the reply from the adapter 12 may comprise all addresses in which data have been stored since the last reply, or all addresses received at which no data have been stored yet. In this situation, the allocator 16 may not need to keep track of the addresses allocated but only those in which data is stored.
  • this free/used information may be used for reading data packets out of the storage 18.
  • Reading information from an address which has been allocated but wherein the correct data has not yet been stored will be problematic.
  • the data packets are stored in the storage 18 as queues. In this situation, holes may occur in a queue due to a data packet for which space has been reserved/allocated but which due to a delay has still not arrived.
  • a queue in the storage is simply implemented as a list, preferably a circular list, of addresses, and a pointer may be used for pointing to the end of the stored data at which new data is to be written/added, and another pointer may point to the end from which data is de-queued.
  • the allocator 16 may update both pointers but at least that at the writing end.
  • the allocator 16 will not move the writing pointer to have the hole included between the writing and reading pointers which together denote the addresses in which data exist. Contrary to that, the writing pointer will only be positioned at the hole and then, when the hole is "filled", move the pointer to the next hole or to the end of the used addresses. In this manner, any process de-queuing the data will not de-queue the hole and thus miss the not-yet-arrived packet.
  • Figure 2 illustrates the use of queues and a manner of ensuring that the processor 34 is aware of which parts of the queue contain valid data.
  • FIG 2 three queues are illustrated to the left. These queues are queues of data in each adapter 12, which data await transmission to the main storage 18. Fat lines are illustrated in each queue, and this describes the position, in the queue of data, of receiving a request and thus for outputting a reply to the storage 18 in the embodiment where this data is output in the order instructed by the allocator 16. Thus, when the fat line is at the front of the queue, the corresponding reply is fed to the storage 18. The upper queue feeds this reply to the address Add-1, the middle one to Add-2 and the lower one to Add-3.
  • the queues are implemented as circular queues, and this is illustrated at queue 3, which overall has been assigned the storage positions between the addresses indicated at the Bottom-3 and Top-3 pointers.
  • the curved arrow indicates that the queue is circular and that, consequently, when the Top-3 pointer is reached, further data is added from the Bottom-3 pointer.
  • valid data is present between the Read pointer (Read-1/2/3) and the Write pointer (Write-1/2/3).
  • the processor 34 then is allowed to read data from the Read pointer and to the Write pointer. New data is stored in addresses above the Write pointer, but as holes (see above) may still exist, the processor is not allowed to de-queue such data, before no holes are present.
  • the processor when having de-queued data, may alter the corresponding Read pointer to make the read addresses available to new data.
  • the corresponding queue may be assumed complete, where after the Write pointer may be moved to the top address currently used, so that the processor has more data available.
  • the allocator 16 sees the data, or altered data, at the Add-address, it may shift the Write pointer to an address which could have been fixed at the point in time of forwarding the request information, as the Allocator 16 at that point in time was aware of which addresses of the pertaining queue were allocated before the request point in time.
  • the allocator 16 may issue a request to all adapters 12 simultaneously (or at least substantially simultaneously). Then, the Write pointer of the shared queue is not altered, before the allocator 16 sees amended data in all relevant Add-addresses, as this is ensures that all data between the former Write address and the new Write address of the shared queue are occupied by valid data.
  • the above embodiment 10 may store the data frames in any number of queues in the storage 18. Which queue to forward a data packet to may depend on the future destiny of the frame. If the frame is to be analysed by one or more processors, one queue may be provided for each processor, and the forwarding of frames to a queue may depend on how long the queue is before adding the packet. If the queue is long, and the processor thus busy, the packet may be provided in a shorter queue of a processor thus less busy.

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
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Claims (16)

  1. Appareil de réception et de transfert de paquets de données, l'appareil comprenant une unité de commande, une mémoire comprenant une pluralité d'adresses auxquelles des données peuvent être mémorisées, et une pluralité d'éléments de réception et de transfert de données, chacun d'eux comprenant :
    - des moyens de réception ou d'accès à un paquet de données,
    - des moyens de délivrance de premières informations relatives au paquet de données,
    - des premiers moyens de réception pour recevoir une adresse pour la mémorisation d'au moins une partie du paquet de données,
    - des deuxièmes moyens de réception pour recevoir des informations de demande et pour générer des informations de réponse,
    - des moyens de mémorisation de l'au moins une partie du paquet de données dans la mémoire à l'adresse reçue et de mémorisation des informations de réponse dans la mémoire à une adresse prédéterminée, les informations de réponse représentant des informations concernant des adresses reçues auxquelles l'au moins une partie des paquets de données a été mémorisée,
    l'unité de commande comprenant :
    - des moyens de réception des premières informations,
    - des moyens de détermination d'une adresse et de retour de l'adresse aux deuxièmes moyens de réception de l'élément de réception et de transfert de données pertinent,
    - des moyens de délivrance des informations de demande à au moins l'un des éléments de réception et de transfert de données,
    - des moyens de conservation d'informations relatives à des adresses retournées à l'au moins un élément de réception et de transfert de données à la suite de la délivrance des informations de demande à celui-ci, et
    - des moyens de lecture, à partir de l'adresse prédéterminée dans la mémoire, des informations de réponse et de mise à jour d'informations, sur la base des informations conservées, relatives à des adresses dans la mémoire auxquelles les au moins des parties des paquets de données sont mémorisées.
  2. Appareil selon la revendication 1, dans lequel les moyens de mémorisation sont aptes à mémoriser les informations de réponse uniquement après la mémorisation de l'au moins une partie des paquets de données à toutes les adresses reçues avant de recevoir les informations de demande.
  3. Appareil selon la revendication 1, dans lequel chaque élément de réception et de transfert comprend en outre des moyens de détermination d'un point dans le temps de réception/d'accès au paquet de données, les moyens de détermination de temps comprenant des moyens d'horloge, les moyens d'horloge de tous les moyens de détermination de temps étant synchronisés.
  4. Ensemble selon l'une quelconque des revendications précédentes, dans lequel une ou plusieurs files d'attente sont définies dans la mémoire en tant que groupes distincts d'adresses, les moyens de détermination de l'unité de commande étant aptes à déterminer, à partir des premières informations, une file d'attente à laquelle ajouter le paquet de données pertinent, et à sélectionner une adresse à partir des groupes d'adresses de la file d'attente pertinente.
  5. Ensemble selon la revendication 4, dans lequel les moyens de détermination de l'unité de commande sont aptes à déterminer une adresse dans la file d'attente déterminée de sorte que les paquets de données soient mémorisés dans la file d'attente dans un ordre de réception/d'accès.
  6. Ensemble selon l'une quelconque des revendications précédentes, l'ensemble comprenant en outre des moyens de lecture ou de sortie de file d'attente de données de la mémoire, les moyens de lecture comprenant des moyens de délivrance de troisièmes informations relatives à une ou plusieurs adresses des moyens de mémorisation, dont les données ont été lues/sorties de file d'attente.
  7. Ensemble selon les revendications 4 et 6, dans lequel l'unité de commande est apte à conserver, pour chaque file d'attente, un pointeur d'écriture identifiant une adresse suivante à laquelle ajouter des données et un pointeur de lecture identifiant une adresse suivante à lire/sortir de la file d'attente,
    les moyens de lecture/mise à jour étant aptes à effectuer :
    - la mise à jour du pointeur d'écriture de la file d'attente sur la base d'informations de réponse reçues et
    - la mise à jour, sur la base de troisièmes informations reçues, du pointeur de lecture de la file d'attente de laquelle des données ont été sorties et
    dans lequel les moyens de détermination sont aptes à déterminer l'adresse également sur la base des pointeurs de lecture et d'écriture des files d'attente.
  8. Ensemble selon la revendication 7, dans lequel les moyens de lecture/mise à jour sont aptes à effectuer la mise à jour du pointeur d'écriture à une adresse uniquement s'il a été reçu des informations de réponse représentant toutes les adresses entre les pointeurs de lecture et d'écriture.
  9. Procédé de fonctionnement d'un appareil comprenant une unité de commande, une pluralité d'éléments de réception et de transfert de données, et une mémoire comprenant une pluralité d'adresses auxquelles des données peuvent être mémorisées, le procédé comprenant :
    un élément de réception et de transfert apte à effectuer :
    - la réception ou l'accès à un paquet de données,
    - la délivrance de premières informations relatives au paquet de données,
    - la réception d'une adresse pour la mémorisation d'au moins une partie du paquet de données,
    - la mémorisation de l'au moins une partie du paquet de données à l'adresse dans la mémoire,
    - la réception des informations de demande et la génération d'informations de réponse, et
    - la mémorisation des informations de réponse dans la mémoire à une adresse prédéterminée, les informations de réponse représentant des informations concernant des adresses reçues auxquelles au moins une partie des paquets de données a été mémorisée,
    l'unité de commande étant apte à effectuer :
    - la réception des premières informations,
    - la détermination d'une adresse, la conservation de l'adresse et le retour de l'adresse aux moyens de réception de l'élément de réception et de transfert de données pertinent,
    - la délivrance des informations de demande à l'élément de réception et de transfert de données, et
    - la lecture, depuis la mémoire, des informations de réponse à partir de l'adresse prédéterminée et la mise à jour d'informations, sur la base des informations conservées, relatives à des adresses dans la mémoire auxquelles les au moins des parties des paquets de données sont mémorisées.
  10. Procédé selon la revendication 9, dans lequel l'étape de la mémorisation comprend la mémorisation des informations de réponse uniquement après la mémorisation de l'au moins une partie des paquets de données à toutes les adresses reçues avant de recevoir les informations de demande.
  11. Procédé selon la revendication 9 ou 10, dans lequel l'élément de réception et de transfert détermine en outre un point dans le temps de réception/d'accès au paquet de données, les moyens de détermination de temps comprenant des moyens d'horloge, les moyens d'horloge de tous les moyens de détermination de temps étant synchronisés.
  12. Procédé selon l'une quelconque des revendications 9 à 11, dans lequel une pluralité de files d'attente sont définies dans la mémoire en tant que groupes distincts d'adresses, l'étape de la détermination comprenant la détermination, à partir des premières informations, d'une file d'attente à laquelle ajouter le paquet de données pertinent, et la sélection d'une adresse à partir des groupes d'adresses de la file d'attente pertinente.
  13. Procédé selon la revendication 12, dans lequel l'étape de la détermination comprend la détermination d'une adresse dans la file d'attente déterminée de sorte que les paquets de données soient mémorisés dans la file d'attente dans un ordre de réception/d'accès.
  14. Procédé selon l'une quelconque des revendications 9 à 13, comprenant en outre l'étape de la lecture ou de la sortie de file d'attente de données de la mémoire, l'étape de la lecture comprenant la délivrance de troisièmes informations relatives à une ou plusieurs adresses des moyens de mémorisation, dont les données ont été lues/sorties de file d'attente.
  15. Procédé selon les revendications 12 et 14, dans lequel l'étape de la détermination comprend la détermination, pour chaque file d'attente, d'un pointeur d'écriture identifiant une adresse suivante à laquelle ajouter des données et d'un pointeur de lecture identifiant une adresse suivante à lire/sortir de la file d'attente,
    l'étape de la lecture/mise à jour comprenant :
    - la mise à jour du pointeur d'écriture de la file d'attente sur la base d'informations de réponse reçues et
    - la mise à jour, sur la base de troisièmes informations reçues, du pointeur de lecture de la file d'attente de laquelle des données ont été sorties et
    l'étape de la détermination comprenant la détermination de l'adresse également sur la base des pointeurs de lecture et d'écriture des files d'attente.
  16. Procédé selon la revendication 15, dans lequel l'étape de la détermination comprend la mise à jour du pointeur d'écriture à une adresse uniquement s'il a été reçu des informations de réponse relatives à toutes les adresses entre les pointeurs de lecture et d'écriture.
EP12700231.9A 2011-01-28 2012-01-11 Appareil et procédé permettant de recevoir et de réacheminer des paquets de données Active EP2668753B1 (fr)

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Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9015379B1 (en) * 2013-10-11 2015-04-21 Ge Aviation Systems, Llc Method of controlling data communication
US10733167B2 (en) 2015-06-03 2020-08-04 Xilinx, Inc. System and method for capturing data to provide to a data analyser
US10691661B2 (en) 2015-06-03 2020-06-23 Xilinx, Inc. System and method for managing the storing of data
JP6465843B2 (ja) * 2016-09-13 2019-02-06 キヤノン株式会社 リング型バスシステム
TWI628542B (zh) * 2017-04-21 2018-07-01 慧榮科技股份有限公司 快閃記憶體的垃圾回收斷電回復方法以及使用該方法的裝置
CN109600795B (zh) * 2017-09-30 2021-09-28 智邦科技股份有限公司 A-msdu子帧的处理方法及无线网络存取装置
TWI725240B (zh) * 2017-09-30 2021-04-21 智邦科技股份有限公司 聚合媒體存取服務數據單元( a - m s d u ) 子訊框的處理方法及無線網路存取裝置
ES2819008T3 (es) * 2018-03-26 2021-04-14 Ewab Eng Ab Controlador de sistema transportador, sistema transportador y método de sincronización de datos
KR102608825B1 (ko) * 2018-04-26 2023-12-04 에스케이하이닉스 주식회사 메모리 컨트롤러 및 이의 동작 방법
CN114124421B (zh) * 2020-08-31 2024-04-12 深圳市中兴微电子技术有限公司 Acl规则处理方法、装置、计算机设备和可读介质
CN113709061A (zh) * 2021-07-23 2021-11-26 合肥忆芯电子科技有限公司 一种报文转发的方法和电路

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61234149A (ja) * 1985-04-09 1986-10-18 Nec Corp 受信バツフア装置
JPS6373741A (ja) * 1986-09-16 1988-04-04 Matsushita Electric Ind Co Ltd 通信制御装置
JP2723970B2 (ja) * 1989-05-26 1998-03-09 株式会社日立製作所 データ転送制御装置
JP3064688B2 (ja) * 1992-08-31 2000-07-12 日本電気株式会社 データ受信装置
US5790545A (en) * 1996-03-14 1998-08-04 Motorola Inc. Efficient output-request packet switch and method
US6434115B1 (en) * 1998-07-02 2002-08-13 Pluris, Inc. System and method for switching packets in a network
US7065050B1 (en) * 1998-07-08 2006-06-20 Broadcom Corporation Apparatus and method for controlling data flow in a network switch
US20020126673A1 (en) * 2001-01-12 2002-09-12 Nirav Dagli Shared memory
US7287649B2 (en) * 2001-05-18 2007-10-30 Broadcom Corporation System on a chip for packet processing
US6967951B2 (en) * 2002-01-11 2005-11-22 Internet Machines Corp. System for reordering sequenced based packets in a switching network
KR100548214B1 (ko) * 2003-12-10 2006-02-02 삼성전자주식회사 복수의 인터페이스를 통해 패킷을 전송하기 위한 정보 독출을 미리 수행하여 패킷 전송을 빠르게 수행하는 패킷 포워딩 시스템 및 그 방법
JP4336625B2 (ja) * 2004-06-17 2009-09-30 株式会社日立製作所 パケット転送装置
US7817636B2 (en) * 2008-01-30 2010-10-19 Cisco Technology, Inc. Obtaining information on forwarding decisions for a packet flow
US9270542B2 (en) * 2009-07-31 2016-02-23 Ixia Apparatus and methods for forwarding data packets captured from a network
US8934341B2 (en) * 2009-12-04 2015-01-13 Napatech A/S Apparatus and a method of receiving and storing data packets controlled by a central controller
WO2011067409A1 (fr) * 2009-12-04 2011-06-09 Napatech A/S Ensemble et procédé de réception et de stockage de données avec économie de bande passante par régulation de la mise à jour des niveaux de remplissage de files d'attente
CN102742220B (zh) * 2009-12-04 2015-09-09 纳派泰克股份公司 使用加时间戳和中央控制器由多个适配器对数据帧进行的分布式处理

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
None *

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EP2668753A1 (fr) 2013-12-04
CN103339903A (zh) 2013-10-02
US20130311609A1 (en) 2013-11-21
DK2668753T3 (en) 2017-12-04
JP2014508454A (ja) 2014-04-03
CN103339903B (zh) 2016-05-04
KR20140004743A (ko) 2014-01-13
WO2012100984A1 (fr) 2012-08-02
BR112013018419A2 (pt) 2016-10-11
JP5816301B2 (ja) 2015-11-18

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