EP2659589A4 - Procédé de détection de phase-de fréquence - Google Patents

Procédé de détection de phase-de fréquence

Info

Publication number
EP2659589A4
EP2659589A4 EP10861467.8A EP10861467A EP2659589A4 EP 2659589 A4 EP2659589 A4 EP 2659589A4 EP 10861467 A EP10861467 A EP 10861467A EP 2659589 A4 EP2659589 A4 EP 2659589A4
Authority
EP
European Patent Office
Prior art keywords
phase
detection method
frequency detection
frequency
detection
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP10861467.8A
Other languages
German (de)
English (en)
Other versions
EP2659589A1 (fr
Inventor
Steven Wen
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Telefonaktiebolaget LM Ericsson AB
Original Assignee
Telefonaktiebolaget LM Ericsson AB
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Telefonaktiebolaget LM Ericsson AB filed Critical Telefonaktiebolaget LM Ericsson AB
Publication of EP2659589A1 publication Critical patent/EP2659589A1/fr
Publication of EP2659589A4 publication Critical patent/EP2659589A4/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00Automatic control of frequency or phase; Synchronisation
    • H03L7/06Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08Details of the phase-locked loop
    • H03L7/085Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/089Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00Automatic control of frequency or phase; Synchronisation
    • H03L7/06Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08Details of the phase-locked loop
    • H03L7/085Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00Automatic control of frequency or phase; Synchronisation
    • H03L7/06Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
EP10861467.8A 2010-12-29 2010-12-29 Procédé de détection de phase-de fréquence Withdrawn EP2659589A4 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2010/002190 WO2012088625A1 (fr) 2010-12-29 2010-12-29 Procédé de détection de phase-de fréquence

Publications (2)

Publication Number Publication Date
EP2659589A1 EP2659589A1 (fr) 2013-11-06
EP2659589A4 true EP2659589A4 (fr) 2015-01-21

Family

ID=46382145

Family Applications (1)

Application Number Title Priority Date Filing Date
EP10861467.8A Withdrawn EP2659589A4 (fr) 2010-12-29 2010-12-29 Procédé de détection de phase-de fréquence

Country Status (4)

Country Link
US (1) US8766689B2 (fr)
EP (1) EP2659589A4 (fr)
CN (1) CN103329440B (fr)
WO (1) WO2012088625A1 (fr)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8945565B2 (en) 2006-12-01 2015-02-03 Selexys Pharmaceuticals Corporation Methods of treating inflammatory or thrombotic conditions with anti-P-selectin antibodies
US8766689B2 (en) * 2010-12-29 2014-07-01 Telefonaktiebolaget L M Ericsson (Publ) Phase-frequency detection method
US8598925B1 (en) * 2012-07-16 2013-12-03 Nanowave Technologies Inc. Frequency determination circuit and method
US10451661B2 (en) 2016-10-28 2019-10-22 Samsung Electro-Mechanics Co., Ltd. Digital frequency measuring apparatus
KR102041662B1 (ko) * 2016-10-28 2019-11-07 삼성전기주식회사 디지털 주파수 측정 장치
US10727847B1 (en) 2019-02-07 2020-07-28 International Business Machines Corporation Digital control of a voltage controlled oscillator frequency

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2286300A (en) * 1994-02-04 1995-08-09 Adc Telecommunications Inc Digitally controlled phase lock loop
EP2237418A2 (fr) * 2009-04-03 2010-10-06 Nxp B.V. Synthétiseur de fréquences

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4577163A (en) * 1984-07-09 1986-03-18 Honeywell Inc. Digital phase locked loop
JP3538994B2 (ja) * 1995-09-20 2004-06-14 ソニー株式会社 ディジタルカウンタおよびディジタルpll回路
JPH1022822A (ja) * 1996-07-05 1998-01-23 Sony Corp ディジタルpll回路
JPH10117142A (ja) * 1996-10-11 1998-05-06 Fujitsu Ltd 位相同期ループ回路および半導体集積回路
US6247138B1 (en) * 1997-06-12 2001-06-12 Fujitsu Limited Timing signal generating circuit, semiconductor integrated circuit device and semiconductor integrated circuit system to which the timing signal generating circuit is applied, and signal transmission system
JP4176705B2 (ja) * 2004-12-02 2008-11-05 シャープ株式会社 Pll回路
FR2882871A1 (fr) * 2005-03-01 2006-09-08 Atmel Corp Oscillateur commande en tension a multiphase realignee et boucle a phase asservie associee
US20080284526A1 (en) * 2007-05-15 2008-11-20 Joseph Hughes Tuning circuit and method
US7940128B2 (en) * 2007-09-17 2011-05-10 Synopsys, Inc. High speed PLL clock multiplier
US8076979B2 (en) 2008-04-04 2011-12-13 Freescale Semiconductor, Inc. Lock detection circuit for phase locked loop
JP2010130412A (ja) * 2008-11-28 2010-06-10 Renesas Technology Corp 半導体集積回路
US8058916B2 (en) * 2010-04-15 2011-11-15 Xilinx, Inc. Lockstep synchronization and maintenance
US8766689B2 (en) * 2010-12-29 2014-07-01 Telefonaktiebolaget L M Ericsson (Publ) Phase-frequency detection method
JP2012205046A (ja) * 2011-03-25 2012-10-22 Renesas Electronics Corp 半導体集積回路およびその動作方法
US8536910B2 (en) * 2011-06-20 2013-09-17 Texas Instruments Incorporated System and method for reducing power consumption in a phased-locked loop circuit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2286300A (en) * 1994-02-04 1995-08-09 Adc Telecommunications Inc Digitally controlled phase lock loop
EP2237418A2 (fr) * 2009-04-03 2010-10-06 Nxp B.V. Synthétiseur de fréquences

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of WO2012088625A1 *

Also Published As

Publication number Publication date
US20130278311A1 (en) 2013-10-24
WO2012088625A1 (fr) 2012-07-05
CN103329440B (zh) 2016-03-23
US8766689B2 (en) 2014-07-01
EP2659589A1 (fr) 2013-11-06
CN103329440A (zh) 2013-09-25

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