EP2592521B1 - Methods and circuits for providing stable current and voltage references based on currents flowing through ultra-thin dielectric layer components - Google Patents

Methods and circuits for providing stable current and voltage references based on currents flowing through ultra-thin dielectric layer components Download PDF

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Publication number
EP2592521B1
EP2592521B1 EP12007509.8A EP12007509A EP2592521B1 EP 2592521 B1 EP2592521 B1 EP 2592521B1 EP 12007509 A EP12007509 A EP 12007509A EP 2592521 B1 EP2592521 B1 EP 2592521B1
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Prior art keywords
terminal
dielectric layer
current
component
voltage
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German (de)
English (en)
French (fr)
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EP2592521A3 (en
EP2592521A2 (en
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Mark Alan Lemkin
Thor Nelson Juneau
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Analog Devices International ULC
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Analog Devices International ULC
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    • GPHYSICS
    • G05CONTROLLING; REGULATING
    • G05FSYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02Regulating voltage or current
    • G05F3/08Regulating voltage or current wherein the variable is dc
    • G05F3/10Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/24Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the field-effect type only

Definitions

  • the present subject matter relates to techniques and equipment to provide stable current and voltage references that are insensitive to variations in operating conditions.
  • the subject matter further relates to providing low-power references based on currents, such as leakage currents, flowing through ultra-thin dielectric-layer components.
  • circuits benefit from reduced power consumption. This is particularly the case for devices which operate on scavenged power, such as thermally-harvested energy (via a Peltier, thermocouple, or similar device), vibration-harvested energy (through a magnet and coil, or piezoelectric transducer, for example), or photoelectric-harvested energy (via a solar cell, for example). Circuits which are powered by a battery with an ultra-low self discharge rate, for example the EnerChip solid state batteries sold by Cymbet, also benefit from reduced power consumption.
  • CMOS technology has decreased in geometry the gate oxide thickness has been continuously reduced. For device geometries below about 0.18um, gate leakage becomes considerable. Gate leakage from these ultra-deep submicron CMOS processes has been identified as an undesired behavior with many undesirable properties. For example, in a microprocessor, gate-oxide leakage contributes to high standby current. Other applications have identified a minimum frequency below which the transistor no longer provides current gain for certain device dimensions and bias points (see, e.g.: " Analog Circuits in Ultra-Deep-Submicron CMOS", IEEE Journal of Solid State Circuits, Vol. 40, No. 1, January 2005, pp. 132-143 ).
  • US 2008/169869 A1 discloses an integrated circuit that includes at least one tunneling device voltage reference circuit for use in low voltage applications.
  • the tunneling device voltage reference circuit includes a pair of voltage dividing device stacks, one having a linear voltage output and the other having a non-linear voltage output.
  • a feedback circuit supplies a regulated voltage to each of the voltage dividing stacks so that the output voltages of the two device stacks equalize. Once the feedback circuit has locked, any one of the device stack output voltages and the regulated voltage may be used as a voltage reference.
  • a circuit according to claim 1 including an ultra-thin dielectric layer component including an ultra-thin dielectric layer component.
  • the component has a first terminal, a second terminal, and an ultra-thin dielectric layer disposed between the first and second terminals such that the first and second terminals contact the dielectric layer and are physically separated from each other.
  • the circuit further includes driving circuitry operative to apply a voltage to the first terminal with respect to the second terminal, in order to cause a unidirectional current to flow through the dielectric layer while the driving circuitry is in operation.
  • the driving circuitry is a current mirror coupled to the component and configured to source at an output node a reference output current that is based upon (e.g., equal, proportional to, or otherwise functionally related to) the current flow through the dielectric layer.
  • the ultra-thin dielectric layer has a thickness of 3nm or less; the first and second terminals are formed on opposite sides of the ultra-thin dielectric layer and are spaced apart from each other by the thickness of the dielectric layer; and/or the ultra-thin dielectric layer is formed of at least one of silicon dioxide, silicon nitride, a high-k dielectric material, a low-k dielectric material, hafnium silicate, zirconium silicate, hafnium dioxide, and zirconium dioxide.
  • the ultra-thin dielectric layer component is a transistor, wherein the first terminal is a gate terminal of the transistor, the second terminal is a channel region of the transistor (e.g., a channel region of a transistor in depletion, accumulation, or inversion mode), and the ultra-thin dielectric layer is an ultra-thin gate oxide layer of the transistor.
  • the ultra-thin dielectric layer component is a MOSCAP or other integrated circuit structure comprising a well formed in a substrate, wherein a first surface of the ultra-thin dielectric layer contacts the well, the first terminal is on a second surface of the dielectric layer opposite the first surface, and the second terminal includes the well.
  • the ultra-thin dielectric layer component is a capacitor structure, wherein the first and second terminals are conductive plates contacting opposite surfaces of the ultra-thin dielectric layer.
  • a circuit including an ultra-thin dielectric layer component is provided.
  • the component has a first terminal, a second terminal, and an ultra-thin dielectric layer disposed between the first and second terminals such that the first and second terminals contact the dielectric layer and are physically separated from each other.
  • the circuit further includes a current source coupled to the component and configured to apply a current to the first terminal of the component to cause the current to flow from the first terminal through the dielectric layer to the second terminal.
  • the circuit operates such that the component provides a reference output voltage between the first and second terminals in response to the current flow through the dielectric layer.
  • the current source of the circuit includes a differential amplifier circuit, wherein the output of the differential amplifier is configured to control the current source such that a voltage across an impedance coupled to an output of the differential amplifier tracks the voltage at the first terminal of the component.
  • the circuit is coupled to an oscillator circuit, wherein the oscillator circuit comprises a current reference generator circuit coupled to the first terminal and configured to generate a stable current reference proportional to the reference output voltage provided by the component, and circuitry configured to generate an oscillator output signal by cyclically charging a capacitor using the stable current reference.
  • the circuit is coupled to a power-on-reset circuit coupled to the first terminal of the component and configured to generate a power-on-reset output signal in response to detecting that a power supply level exceeds the reference output voltage at the first terminal of the component.
  • the various circuits and methods disclosed herein relate to providing stable current and voltage references that are insensitive to variations in circuit operating conditions such as temperature.
  • the circuits and methods further provide low-power current and voltage references, such as current and voltage references based on leakage currents of ultra-thin dielectric-layer components.
  • the circuits and methods provide stable current and voltage references that output currents/voltages having relatively constant and invariable amplitude values.
  • the current and voltage references are designed to maintain stable outputs independently of variations in circuit and ambient temperatures, changes in circuit load or power supply voltage, and/or any other changes in circuit operating conditions.
  • a reference circuit may provide an output current with an amplitude that varies by no more than 100 pA over a range of operating temperatures from -40 Celsius to +85 Celsius, or provide an output voltage with an amplitude that varies by no more than 10 mV over a range of power supply values from +2 Volts to +3.6 Volts or no more than 10 mV over a range of operating temperatures from -40 Celsius to +85 Celsius.
  • the circuits and methods can provide stable reference currents with very low amplitudes (e.g., in the range of 50-130 pA).
  • the reference circuits provide stable reference voltage or currents using circuitry operating using very low bias currents with amplitudes as low as 50-130 pA or lower, and total reference circuit current consumptions in the order of a few nA (e.g., 1-10 nA).
  • FIG. 1A shows an illustrative ultra-thin dielectric layer component 100.
  • the ultra-thin dielectric-layer component 100 is formed of at least one ultra-thin dielectric layer 101 separating two electrical contacts 103a, 103b coupled to respective component terminals 107a, 107b.
  • the electrical contacts 103a, 103b are formed of conductive materials, such as appropriately doped silicon, polysilicon, metal depositions or conductive plates such as capacitor plates, or the like.
  • the electrical contacts are generally formed on opposite surfaces of the ultra-thin dielectric layer 101, such that the contacts are separated from each other by a minimum distance equal to a thickness of the ultra-thin dielectric layer.
  • the two electrical contacts do not contact each other, but each is in contact with the ultra-thin dielectric layer.
  • the ultra-thin dielectric layer has additional terminals.
  • the ultra-thin dielectric layer can be formed of any of a variety of dielectric substance, and in various examples may be formed of silicon dioxide, silicon oxide (e.g., a dielectric including a silicon oxide that is not a 1:2 ratio of silicon to oxygen), silicon nitride, a high-k dielectric material, a low-k dielectric material, hafnium silicate, zirconium silicate, hafnium dioxide, hafnium oxide, zirconium dioxide, or another appropriate type of dielectric.
  • the thickness of the ultra-thin dielectric layer is generally limited to be less than 3 nm (e.g., in a range of 1-3 nm, such as a thickness of 1.9 nm on an n-type substrate or 2.1 nm on a p-type substrate). In some examples, however, the thickness can be limited to be less than 1 nm. Other dielectric layer thicknesses may also advantageously be used, including thicknesses of more than 3 nm. In general, in a dielectric layer shaped as a cuboid having rectangular faces (such as that shown in FIG. 1A ), the thickness of the dielectric layer may correspond to the smallest dimension of the layer (as shown illustratively in component 100 of FIG. 1A ).
  • the two electrical contacts may be formed such that they each contact at least part of (or substantially all of) respective opposite surfaces of the cuboid that are separated from each other by the thickness dimension.
  • the thickness of the dielectric layer may be set based on the material of the dielectric layer so as to provide conduction of non-negligible current through the dielectric layer when a normal operating voltage is applied across the layer.
  • the ultra-thin dielectric layer allows tunneling of charge carriers (e.g., electrons and/or holes) through the dielectric layer from one electrical contact to the other electrical contact in response to a voltage or current being applied between the contacts.
  • charge carriers e.g., electrons and/or holes
  • the charge carriers tunnel through the dielectric layer in a relationship characterized by one or more current vs. voltage curves such as those shown in FIG. IE.
  • charge carriers tunnel though the dielectric layer when standard integrated circuit operating voltages (e.g., in the range of 100 mV - 5 V) or currents (e.g., in the range of 1 pA - 100 mA) are applied between the contacts.
  • FIGS. 1B and 1C illustratively show cross-sections of two illustrative ultra-thin dielectric layer components 110 and 120 formed in integrated circuit substrates.
  • the components may be formed, for example, in Ultra-Deep Submicron CMOS (UDSCMOS) processes.
  • UDSCMOS Ultra-Deep Submicron CMOS
  • the component 110 of FIG. 1B may be referenced as a MOSCAP
  • the component 120 of FIG. 1C may be referenced as an ultra-thin gate oxide transistor.
  • the component 110 of FIG. 1B is formed in a substrate 111 (e.g., a p-type substrate), and includes an ultra-thin dielectric layer 117 formed on the surface of the substrate.
  • a first contact is formed of a doped region or well 113 (e.g., an n-well) extending below and contacting the dielectric layer 117, and of a diffusion region 115 (e.g., an n+ diffusion) forming a contact to the doped region or well.
  • a first electrical terminal can be coupled to the doped region or well 113 and/or diffusion region 115 to serve as one terminal of the component 110.
  • a second contact is formed of a conductor 119 (e.g., a conductor such as metal, polysilicon, or salicided or silicided polysilicon) formed on an upper surface of the dielectric layer 117.
  • a second electrical terminal can be coupled to the conductor 119 to serve as another terminal of the component 110.
  • the component 110 is formed directly in the substrate 111 (e.g., an n-doped substrate) without the presence of a well 113, the first contact is formed of a region of the doped substrate 111 extending below and contacting the dielectric layer 117, and the first contact is set to a substrate potential of the substrate 111.
  • the component 120 of FIG. 1C is formed in a substrate 121 (e.g., a p-type substrate), and includes an ultra-thin dielectric layer 127 formed on the surface of the substrate.
  • a first contact is formed of a doped region or well 123 (e.g., an n-well) extending below and contacting the dielectric layer 127, of a diffusion region 125 (e.g., an n+ diffusion) forming a contact to the doped region or well and serving as a body terminal, and of two additional diffusion regions 131, 133 (e.g., p+ diffusions) serving as drain and source terminals.
  • a first terminal of the component 120 corresponds to the channel region of the transistor (the region of the doped region or well 123 that is below the dielectric layer 127), and can be formed of the interconnection of the body, drain, and source terminals to serve as one terminal of the component 120.
  • a second contact is formed of a conductor 129 (e.g., a conductor such as metal, polysilicon, or salicided or silicided polysilicon) formed on an upper surface of the dielectric layer 127 and serving as a gate terminal.
  • a second electrical terminal of the component 120 can be coupled to the gate terminal conductor 129 to serve as another terminal of the component 120.
  • the component 120 is formed directly in a region of the doped substrate 121 without the presence of a well 123, the first contact is formed of a channel region of the substrate 121 extending below and contacting the dielectric layer 127.
  • the components 110 and 120 have each been described as being formed in p-type substrates, the components 110 and 120 can alternatively be formed in n-type substrates.
  • the component 110 would include a p-type doped region or p-well 113 and a p+ diffusion 115 while the component 120 would include a p-type doped region or p-well 123, a p+ diffusion 125, and n+ diffusions 131 and 133.
  • Ultra-thin dielectric layer components exhibit a relationship between a gate voltage and a gate current, and are such that the gate current is of a non-negligible quantity due at least in part to the tunneling of charge carriers through the dielectric layer.
  • core transistor 120 or MOSCAPs 110 formed in a 130nm, 90nm, 65nm, or any other appropriate integrated circuit fabrication technology may exhibit such non-negligible gate currents.
  • the mechanism for the gate current is electron tunneling.
  • the mechanism for the gate current is hole tunneling.
  • the mechanism for the gate current is direct tunneling of a carrier across the dielectric barrier. Tunneling is a behavior described by quantum mechanics.
  • an integrated circuit may include one or more core components with thin gate oxides, and one or more I/O components with thicker gate oxides able to handle higher voltages for device inputs and outputs. These thicker gate-oxide components have substantially reduced gate leakage.
  • FIG. 1D is a graph illustrating simulated current versus voltage of a diode.
  • current is plotted vs. voltage for a 1 um x 1 um silicon p-n junction diode at three temperatures: -40C, 22.5C, 85C.
  • FIG. IE is a graph illustrating simulated gate current versus gate-source voltage for an ultra-thin gate oxide transistor such as component 120.
  • the drain, source, and body terminals are tied to zero potential for a 1um x 1um core (1.2V) high-VT NMOS transistor fabricated in a 65nm CMOS process at three temperatures: -40C, 22.5C, and 85C.
  • FIG. 1E shows that for a constant forward voltage, the gate current of the ultra-thin dielectric layer transistor component doesn't even double at bias point 104, and changes by less than 5% at bias point 106.
  • the relatively low temperature variation of the ultra-thin dielectric layer transistor's gate-current/gate-voltage transfer characteristic may be used to generate a reference with good temperature stability at ultra-low currents compared to a reference using a junction component such as a diode or a bipolar transistor.
  • a junction component such as a diode or a bipolar transistor.
  • FIG. ID and FIG. IE Another difference between FIG. ID and FIG. IE is that the slope of the current vs. forward voltage for the diode is much steeper than the slope of the current vs. forward voltage for the ultra-thin dielectric layer transistor component. Since the slope of the diode is steep, the useful operating range of the diode for low-power applications is substantially reduced as compared to the ultra-thin dielectric layer transistor component because the forward diode current quickly becomes prohibitively large for a fixed reference voltage output. Note that while bandgap references typically use bipolar junction transistors (BJTs), BJTs typically perform poorly at very high and very low current
  • FIG. 2A which shows an unclaimed example useful for understanding the invention, is a schematic diagram illustrating an embodiment of a low-power current reference circuit 200 operative to produce at an output node 208 a reference output current that is proportional to (or otherwise based on) the current flow through the ultra-thin dielectric layer component 202.
  • a bias current is generated by ultra-thin dielectric-layer core component 202 in response to a driving circuit applying a voltage across the component 202.
  • the driving circuit includes a PMOS current mirror coupled to the component and comprising devices 204 and 206.
  • Diode-connected transistor 204 applies a voltage to a first terminal of component 202 (e.g., the gate of transistor 202) thereby causing a current to flow across the dielectric of component 202.
  • the voltage applied by the transistor 204 to the first terminal is a voltage having a constant amplitude/value while the current mirror is active, which causes a current to flow through the dielectric layer in a unidirectional direction from the transistor 204 to the ground node (or lower power supply node) through the dielectric layer component.
  • the output of the circuit is taken at drain 208 of PMOS transistor 206, where a reference output current proportional to the current flow through the component 202 is sourced.
  • the current sourced at node 208 generally tracks the current flowing through component 202 (and may have the same current amplitude as the current flowing through component 202); more generally, however, if transistors 204 and 206 have different dimensions, the current sourced at node 208 is proportional to the current flowing through component 202 and the proportionality constant is determined by the ratio of sizes of transistors 204 and 206.
  • the voltage applied to component 202 is generally of constant polarity and, therefore, current through component 202 flows in only one direction during operation of reference circuit 200. That is, during operation of reference circuit 200, the current flow through component 202 flows from the gate of 202 through the ultra-thin dielectric layer to the channel when the circuit is powered.
  • devices 204 and 206 are fashioned from PMOS transistors with gate oxides that are thicker than the ultra-thin gate oxide of component 202, such that gate leakage currents in the current mirror transistors 204 and 206 are negligible when compared to the reference current levels.
  • component 202 may utilize a 1.2V gate oxide while PMOS current mirror devices 204 and 206 may utilize 2.5V transistor gate oxides.
  • Component 202 is coupled between the drain node of device 204 and one of a ground node (as shown in FIG. 2A ) or a lower power supply.
  • the component 202 of FIG. 2A is illustratively shown as an ultra-thin dielectric layer transistor component having source, drain, and body terminals coupled together, the component 202 can more generally be any ultra-thin dielectric-layer component.
  • the component 202 may be any of components 100, 110, or 120, or any interconnection of two or more of such components in series and/or in parallel.
  • FIG. 2B is a plot illustrating simulated output current produced by current source 200 versus temperature.
  • the negative current refers to current being sourced out of the drain of transistor 206.
  • device 202 is a 1um/1um 1.2V high-VT NMOS transistor having an ultra-thin gate oxide
  • devices 204 and 206 are 0.32um/10um 2.5V low-leakage PMOS transistors in a 65nm CMOS process.
  • the power supply voltage is fixed with a constant voltage of 1.2V across nodes VDD (i.e., the upper power supply) and GND (i.e., the lower power supply). Note that the current variation of this circuit is good over temperature, especially considering the small area it occupies and the low bias current output.
  • the output of this current source may be used to bias an operational amplifier, an oscillator, a comparator or any other appropriate type of circuit.
  • FIG. 2C which is an unclaimed example useful for understanding the invention, is a schematic diagram illustrating an embodiment of a low-power current reference circuit 250 operative to produce at an output node 258 a reference output current that is proportional to (or otherwise based on) the current flow through the ultra-thin dielectric layer component 252.
  • component 252 and transistors 254, 256, and 258 are respectively similar to and function analogously to elements 202, 204, 206, and 208 of circuit 200. As such, description of these components will not be repeated.
  • Circuit 250 additionally includes buffer 262 receiving an input voltage level V ref at an input node.
  • the buffer 262 is operative to set the voltage at the first terminal of component 252 to V ref by controlling the gate voltage of source follower transistor 260.
  • a bias current is thus generated through ultra-thin dielectric-layer core component 252 in response to the input voltage level V ref being applied across its terminals.
  • the bias current is mirrored by transistors 254 and 256, and a current proportional to the current through element 252 is sourced at node 258.
  • the input reference voltage V ref is a voltage having a constant amplitude/value while the current mirror is active, which causes a current to flow through the dielectric layer in a unidirectional direction.
  • FIG. 3A which shows an unclaimed example useful for understanding the invention, is a schematic diagram illustrating an embodiment of a low-power voltage reference circuit 300.
  • the voltage reference circuit 300 utilizes an ultra-thin dielectric layer component 302 and current source 304 implemented as an impedance device such as a resistor.
  • the current source coupled to the component 302 applies a current to the component 302 to cause a current to flow through the dielectric layer to a ground node (as shown) or a lower power supply node.
  • the current flow through the component 302 produces a reference output voltage V out across the terminals of the component 302.
  • FIG. 3B is a graph illustrating simulated voltage versus temperature as the supply voltage VDD is stepped.
  • the reference output voltage V out for a fixed supply voltage of 2.8V changes approximately 6.5mV as temperature varies from -40C to 85C.
  • the reference output voltage V out changes 151mV as the supply voltage VDD varies from 2V to 3.6V.
  • current source 304 comprises a resistor with a value greater than 10 MOhms which has quite small dimensions in a deep-submicron process.
  • FIG. 4A is a schematic diagram illustrating an embodiment of a low-power voltage reference circuit 400.
  • the voltage reference circuit 400 utilizes core (1.2V) ultra-thin dielectric layer component 402 (illustratively shown as an NMOS transistor) coupled in series with a current source circuit.
  • the current source circuit includes a PMOS current mirror comprising 2.5V transistors 404 and 406, 2.5V native NMOS source-follower transistor 408, and an impedance device 410 (such as a resistor).
  • the current source circuit produces at the drain of transistor 404 a current that is proportional to (or equal to, in examples in which transistors 404 and 406 have the same dimensions) the current flowing through the impedance device 410.
  • the current source applies the current to the first terminal of component 402, to cause the reference output voltage V out to be produced across the terminals of component 402.
  • the circuit 400 uses a feedback loop to improve the output voltage stability produced at output node 412 over temperature.
  • the output voltage at node 412 applies a voltage to impedance device 410 which generates a current that is mirrored via PMOS transistors 404 and 406 to core component 402. Because changes in current from the resistor result in only small changes in reference voltage, this circuit provides a substantially constant reference voltage over temperature.
  • a temperature coefficient of the impedance device 410 and/or of the source-follower transistor 408 is used to provide improved temperature performance by causing the current through component 402 to vary with temperature in a manner that compensates for variations in the current/voltage relationship of component 402 over temperature.
  • this circuit has good supply rejection as the device 404 and device 408 drop excess supply voltage over their drain / source terminals; as a result, changes (and/or noise) in the supply voltage level may result in only small changes in the reference voltage level.
  • a startup circuit is not included and startup occurs based on device leakage currents.
  • a small current is injected into node 412 or node 414 to ensure that a stable undesired operating point does not exist.
  • the startup current may be removed after startup has occurred.
  • FIG. 4B is a graph illustrating simulated voltage versus temperature as supply voltage is stepped.
  • the output voltage at node 412 for a fixed supply voltage of 2.8V changes approximately 1.1mV as temperature varies from -40C to 85C.
  • the output voltage changes 10.7mV as the supply voltage VDD varies from 2V to 3.6V.
  • Further improvements in power supply rejection may be attained by additional cascoding of devices 404 and 408.
  • the simulated current consumption of approximately 4.8nA is exceptionally low for such a stable reference.
  • FIG. 5A is a schematic diagram illustrating an embodiment of a low-power reference circuit 500.
  • the circuit 500 includes a current source (transistors 506, 508) producing at the drain of transistor 506 a current that mirrors the current flowing through an impedance device (formed, in circuit 500, of the interconnection of 504 and 522).
  • the current source applies the current to the first terminal of component 502, to cause the reference output voltage V out to be produced across the terminals of component 502.
  • active feedback is provided by a differential amplifier comprising 2.5V transistors 512, 514, 518, 520, and 516.
  • the differential amplifier has first and second input nodes at the gate terminals of transistors 512 and 514, and produces an output signal at the source node of transistor 516.
  • Current source 510 which mirrors the current produced by the current source formed of transistors 506 and 508, biases the amplifier by (optionally) scaling and mirroring the current through PMOS transistor 508.
  • a compensation capacitor is tied between the drain of NMOS 520 or the drain of 504 and a supply rail to stabilize the amplifier.
  • An impedance element such as one formed of core ultra-thin dielectric layer component 504 in series with resistor 522, is coupled between the source of transistor 516 and ground and serves to adjust the resistor current as the temperature varies.
  • the differential amplifier is configured to maintain equal the voltage at its first and second input nodes.
  • the differential amplifier controls the current source (506, 508) such that the voltage across the impedance element (formed of the series interconnection of 504 and 522) tracks the voltage across the component 502. Since the threshold voltage of component 504 is reduced as the temperature rises, current through the resistor 522 increases, partially cancelling out the voltage drop at the reference output node 524 caused by the temperature characteristic of core component 502 in response to the rise in temperature.
  • FIG. 5B is a graph illustrating simulated voltage versus temperature as supply voltage is stepped. In the example shown there is a temperature variation of less than 500uV at 2.8V supply, and a variation from 2V to 3.6V of only 8mV at 25C. The current consumption of the reference of FIG. 5B is exceptionally low for such a stable reference, measuring 2.4nA at 25C.
  • components 502 and 504 can each be formed of one or more ultra-thin dielectric layer components such as any of components 100, 110, or 120.
  • component 504 is of the same type as component 502 (for example, they are both 1.2V transistor devices); component 504 is of a different type than component 502 (for example, component 504 is a 2.5V device or a PMOS device).
  • other means of communicating the output voltage to the current generating stack is used, for example a simple source-follower circuit, instead of an amplifier.
  • a second order correction term is applied to a reference similar to the reference of FIG. 5A .
  • a second order correction term may be generated by first subtracting a current proportional or inversely proportional to temperature from a constant or relatively constant current and squaring the resulting difference current. The squared difference current is added or subtracted, as appropriate, from the nominal current to the reference core for improved temperature accuracy.
  • a second order correction term is generated in the voltage domain, as opposed to a current domain.
  • third- or higher-order correction terms are applied for improved reference performance.
  • Process variation may affect the ultra-thin dielectric layer thickness, gate-oxide thickness, or threshold voltage of the various transistors within a circuit, thereby causing variation in the circuit behavior from device to device.
  • a voltage or current is measured at a time of manufacture (e.g., using a wafer probe or final test) and used to adjust a characteristic of the circuit to improve a performance metric.
  • FIG. 6A is a graph illustrating simulated voltage versus temperature as models are varied. In the example shown, the temperature performance of an embodiment of the circuit of FIG. 5A is simulated with slow, typical, and fast models for the core transistors and ultra-thin dielectric layer components.
  • FIG. 6B is a graph illustrating simulated voltage versus temperature as models are varied with trim for minimum temperature coefficient.
  • the performance of the circuit is trimmed for minimum temperature coefficient by adjusting the value of a resistor similar to resistor 522.
  • the variation over process of the nominal output voltage at 25C has been reduced by more than a factor of five, while the variation over temperature for a given curve is about 1mV.
  • FIG. 6C is a graph illustrating simulated voltage versus temperature as models are varied with trim for an approximately constant output voltage at 25C.
  • trim is attained by adjusting a resistor using laser trim; trim is attained by adjusting an effective resistance using transistors as switches to connect or disconnect resistors in an array; trim is attained using a digital-to-analog converter (DAC) to selectively identify resistors to connect or disconnect in an array; trim is attained by adjusting a ratio of transistors in a current mirror (e.g. the current mirror of FIG. 5A comprising 506 and 508) using transistors as switches to connect or disconnect unit transistors in an array; or any other appropriate method of adjustment.
  • DAC digital-to-analog converter
  • the value of the digital trim word is determined at a time of manufacture at which point the proper value of trim is associated with the particular unit under test.
  • circuit trim is associated with the unit under test via digital trim; blowing of metal or polysilicon fuses; laser trimming of metal or polysilicon wires; laser trim of thin film resistors; a nonvolatile memory such as flash or FRAM; one-time programmable memory such as provided by the circuit IP vendor Kilopass; or any other appropriate method.
  • a low-power oscillator uses a gate-leakage to gate-voltage characteristic of one or more ultra-thin dielectric layer component(s) as a reference.
  • FIG. 7A is a schematic diagram illustrating an embodiment of a low-power oscillator 700 using a ultra-thin dielectric layer leakage-current based reference.
  • voltage reference circuit 702 which is similar to circuit 500 of FIG. 5A , in conjunction with current reference generator 704 provides a charging current to oscillator core 706.
  • Current reference generator 704 uses amplifier 714 to force the reference voltage at node V out across resistor 716, so as to produce a stable current reference equal to the current flowing through resistor 716 and transistor 719.
  • a replica transistor 718 which may have the same or a different size from transistor 719, applies a current having an amplitude based on the voltage V out (e.g., proportional to the voltage V out ) to capacitor 720 which is slowly charged.
  • Comparator 722 compares the voltage on capacitor 720 with a reference voltage V ref , and determines when the voltage on capacitor 720 has crossed a threshold equal to the reference voltage V ref . In various embodiments the comparator measures a voltage greater than the reference voltage; a voltage equal to the reference voltage; a voltage equal to a fraction of the reference voltage; or any other appropriate level. When the reference voltage threshold is crossed, the comparator 722 outputs a signal at node OscOut causing transistor 728 to rapidly discharge capacitor 720.
  • Capacitor 720 is thus cyclically charged using the stable current reference, and a precise timing reference can be established based on the time between two charging cycles of the capacitor 720.
  • Feedback capacitor 724 AC couples the voltage at node 726 back to the comparator core (in positive feedback) causing the comparator output slew rate to be faster.
  • the signal at node OscOut may be used to keep track of time or initiate an event, such as causing a microprocessor to wake from a sleep mode.
  • capacitor 720 is partially discharged, or capacitor 720 is fully discharged, in response to reaching the reference voltage threshold. Because the current levels (such as the current applied by transistor 718) may be made very small, capacitor 720 may be small-valued even for very low output frequencies. The use of a small-valued capacitance saves die area, thereby reducing product cost.
  • the oscillator of FIG. 7A has a simulated current consumption of 7nA at 3.6V including all three blocks 702, 704, and 706.
  • FIG. 7B is a graph illustrating simulated frequency versus temperature. In the example shown, the total variation over temperature is about 1%, which is particularly good given the low power consumption. In some embodiments the frequency of the oscillator is adjusted by digitally trimming the value of capacitor 720.
  • the frequency of the oscillator is adjusted by digitally trimming the amount of current sourced by transistor 718.
  • a reference for bias currents used in amplifier 714, comparator 722 and the logic recovery circuit between node 726 and node OscOut are generated by a PMOS mirror comprising PMOS transistors 708 and 710 in conjunction with diode-connected NMOS 712.
  • PMOS and NMOS utilize I/O voltage devices (such as a 2.5V device in 65nm) except for the two core ultra-thin dielectric layer components in reference generator 702 (corresponding to components 502 and 504 of FIG. 5A ).
  • the oscillator output at node OscOut is coupled to a counter or a timer to keep track of time or initiate an event after an elapsed amount of time has passed.
  • a low-power oscillator is trimmed for improved frequency accuracy at a time of manufacture; an oscillator is periodically trimmed in situ by comparing the number of oscillation cycles of the oscillator that occur in a number of cycles of a second oscillator with improved frequency accuracy, such as a quartz crystal oscillator or a MEMS-resonator based oscillator; an oscillator is sporadically (e.g., when a temperature change is determined to exceed a certain amount) trimmed in situ by comparing the number of oscillation cycles of the oscillator that occur in a number of cycles of a second oscillator with improved frequency accuracy, such as a quartz crystal oscillator or a MEMS-resonator based oscillator.
  • a power-on-reset circuit uses a gate leakage-current to gate voltage characteristic of an ultra-thin dielectric layer component to determine when a power supply has reached a particular threshold voltage level.
  • FIG. 8A is a schematic diagram illustrating an embodiment of a power-on reset circuit 800 using an ultra-thin dielectric layer component based reference circuit.
  • reference 802 is coupled to supply-voltage comparator 804.
  • Ultra-thin dielectric layer components 820, 822, 824, 826, and 828 are arranged in series between the power supply nodes VDD and GND (or a lower power supply node VSS) to provide an ultra-low current voltage divider at an output node of the comparator 804.
  • additional (or fewer) ultra-thin dielectric layer components are included in the series interconnection to provide additional (or fewer) voltage divider reference levels.
  • components 820, 822, 824, 826, and 828 are core (1.2V) NMOS ultra-thin dielectric layer transistor components fabricated in a 65nm process; however, in other embodiments, other types of ultra-thin dielectric layer components may be used.
  • the gate capacitance acts to divide the voltage, providing a zero in the frequency response from the supply to the taps.
  • the inter-component nodes or taps 810, 812, 814, 816, and 818 serve as voltage-divider output nodes.
  • Tap 816 is connected to comparator 806 to detect when the power-on-reset threshold (corresponding to the voltage potential V 816 at node 816) has been crossed or exceeded.
  • the size and number of components in the voltage divider are chosen with consideration of the maximum gate voltage allowed for reliability; the maximum desired current in the voltage divider; the fractional step size of the taps; parasitic layout capacitance; parasitic junction leakage current.
  • FIG. 8B is a graph illustrating simulated output state as supply is varied. In the example shown, the threshold of PORn vs. supply as temperature is stepped from -40 to 85C changes by only about 35mV.
  • a voltage supervisor circuit outputs a power on reset signal as well as one or more voltage threshold signals by comparing different taps of the voltage divider with a reference voltage.
  • a voltage threshold signal is used as a brownout detector.
  • two or more thresholds are used to generate hysteresis in the power-on-reset circuit so that a power-on-reset signal occurs until a first threshold is crossed in a positive going direction. In the negative going direction, the supply has to cross a second, lower threshold to assert power-on-reset after the first threshold is crossed. Hysteresis in this fashion is helpful to prevent a limit cycle from forming as the device draws current coming out of reset.
  • a plurality of thresholds is used in a supply supervisor for an energy-scavenged device.
  • a scavenger such as a solar cell provides a small amount of current to charge a capacitor until a voltage threshold is crossed.
  • the supply supervisor initiates a sequence of events to perform a desired operation which may include one or more of: measurement of a parameter from a transducer such as temperature; sending a data packet by a radio transmitter; listening for a data packet by a radio receiver; incrementing a nonce stored in a nonvolatile memory; actuating a device; or any other appropriate action or combination of actions.
  • the supply supervisor can ensure that a sufficient amount of energy to complete a desired operation has accumulated on the capacitor before initiating the operation.
  • An ultra-low power supervisor circuit is advantageous because only a tiny portion of the scavenged energy is required for supply supervision.
  • energy is scavenged via a photoelectric cell constructed from one or more P-N junctions fabricated on the same piece of silicon as the voltage supervisor chip.
  • a light shield may be constructed using one or more layers of metal over the sensitive portions of the circuit.
  • An optically transparent or translucent plastic such as a type of plastic suitable for packaging light-emitting-diodes, may be used to encapsulate and protect the integrated circuit from the environment (such as moisture or ionic contamination) while allowing light energy to reach the photoelectric cell.
  • a 1mm x 1mm area is allocated for a photoelectric cell on the same piece of silicon as the voltage supervisor. Assuming an efficiency of 10%, the photoelectric cell will generate about 50nW of power with typical office lighting. If 10nW is allocated for voltage supervision, this would allow a radio, such as Dust Networks' LPZ600 (which consumes approximately 30uJ to transmit a packet from power off) to measure temperature and send a packet containing this information approximately every 10 minutes using only the energy collected by incident light on the silicon chip. In some embodiments, a portion or all of the functionality of a device such as Dust Networks' LPZ600 is integrated on the same piece of silicon as a photoelectric cell and a low-power voltage supervisor.
  • a radio such as Dust Networks' LPZ600 (which consumes approximately 30uJ to transmit a packet from power off) to measure temperature and send a packet containing this information approximately every 10 minutes using only the energy collected by incident light on the silicon chip.
  • a portion or all of the functionality of a device such as Dust
  • an oscillator output is used to provide a switched-cap resistor in place of a resistive element, for example device 522.
  • a switched-cap resistor is beneficial in terms of size for large resistances. Switched-cap design is well known by those skilled in the art.
  • PMOS devices are used instead of NMOS devices; NMOS devices are used instead of PMOS devices; the drain and source voltage of a transistor-type component 120 are of similar potential and/or coupled to each other; the drain and source voltage of a transistor-type component 120 are of different potential; the body terminal of a transistor-type component 120 is of a similar potential to (and/or coupled to) a drain and/or source terminal; the body terminal of a transistor-type component 120 is of a different potential than a drain or source terminal; the body terminal of a transistor-type component 120 is connected to ground; the body terminal of a transistor-type component 120 is connected to a positive power supply voltage; only one of the source, drain, and body terminals is connected and the other terminals remain floating.
  • a MOSCAP with an ultra-thin gate oxide (such as a core gate oxide in a 65nm process) is used in place of or in conjunction with a transistor-type component 120.
  • a MOSCAP is constructed with a first terminal of n-type silicon under a dielectric layer and a second terminal of polysilicon on top of the dielectric layer.
  • a MOSCAP is constructed with a first terminal of p-type silicon under a dielectric layer and a second terminal of polysilicon on top of the dielectric layer.
  • one or more references, oscillators, and voltage supervisor circuits are included on a single integrated circuit to provide power management.
  • the circuit techniques and circuits described herein are used to provide a voltage, current, or timing reference.
  • the gate is separated from the substrate by a dielectric including silicon dioxide; the gate is separated from the substrate by a dielectric including a silicon oxide that is not a 1:2 ratio of silicon to oxygen; the gate is separated from the substrate by a dielectric including a silicon nitride; the gate is separated from the substrate by a dielectric including a Hafnium Oxide; or the gate is separated from the substrate by any other appropriate dielectric.

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EP12007509.8A 2011-11-03 2012-11-05 Methods and circuits for providing stable current and voltage references based on currents flowing through ultra-thin dielectric layer components Active EP2592521B1 (en)

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US11469223B2 (en) * 2019-05-31 2022-10-11 Analog Devices International Unlimited Company High precision switched capacitor MOSFET current measurement technique
US10845839B1 (en) * 2019-09-13 2020-11-24 Analog Devices, Inc. Current mirror arrangements with double-base current circulators

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US6265749B1 (en) * 1997-10-14 2001-07-24 Advanced Micro Devices, Inc. Metal silicide transistor gate spaced from a semiconductor substrate by a ceramic gate dielectric having a high dielectric constant
EP1014547A3 (en) * 1998-12-21 2000-11-15 Fairchild Semiconductor Corporation Low-current charge pump system
CH697322B1 (fr) * 2000-06-13 2008-08-15 Em Microelectronic Marin Sa Procédé de génération d'un courant sensiblement indépendent de la température et dispositif permettant de mettre en oeuvre ce procédé.
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US6917319B1 (en) * 2004-03-30 2005-07-12 International Business Machines Corporation Digital to analog converter using tunneling current element
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