EP2543136A1 - Convertisseur courant-tension à réflecteur de courant, étage d'entrée d'un amplificateur et amplificateur correspondant - Google Patents
Convertisseur courant-tension à réflecteur de courant, étage d'entrée d'un amplificateur et amplificateur correspondantInfo
- Publication number
- EP2543136A1 EP2543136A1 EP10719533A EP10719533A EP2543136A1 EP 2543136 A1 EP2543136 A1 EP 2543136A1 EP 10719533 A EP10719533 A EP 10719533A EP 10719533 A EP10719533 A EP 10719533A EP 2543136 A1 EP2543136 A1 EP 2543136A1
- Authority
- EP
- European Patent Office
- Prior art keywords
- current
- output
- voltage
- input
- converter
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000006243 chemical reaction Methods 0.000 claims abstract description 7
- 230000003321 amplification Effects 0.000 claims description 12
- 238000003199 nucleic acid amplification method Methods 0.000 claims description 12
- 238000005259 measurement Methods 0.000 claims description 5
- 230000000087 stabilizing effect Effects 0.000 claims description 4
- 238000002347 injection Methods 0.000 claims description 2
- 239000007924 injection Substances 0.000 claims description 2
- 239000003990 capacitor Substances 0.000 description 9
- 230000003071 parasitic effect Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- 230000000712 assembly Effects 0.000 description 1
- 238000000429 assembly Methods 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 230000006641 stabilisation Effects 0.000 description 1
- 238000011105 stabilization Methods 0.000 description 1
- 230000001052 transient effect Effects 0.000 description 1
- 238000011144 upstream manufacturing Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/32—Modifications of amplifiers to reduce non-linear distortion
- H03F1/3205—Modifications of amplifiers to reduce non-linear distortion in field-effect transistor amplifiers
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/08—Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements
- H03F1/083—Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements in transistor amplifiers
- H03F1/086—Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements in transistor amplifiers with FET's
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/30—Modifications of amplifiers to reduce influence of variations of temperature or supply voltage or other physical parameters
- H03F1/301—Modifications of amplifiers to reduce influence of variations of temperature or supply voltage or other physical parameters in MOSFET amplifiers
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2200/00—Indexing scheme relating to amplifiers
- H03F2200/03—Indexing scheme relating to amplifiers the amplifier being designed for audio applications
Definitions
- the present invention relates to a current-voltage converter with a current reflector, the input current comprising a fixed component and a variable component, the converter comprising:
- a current reflector circuit comprising two constant current sources each connected between the output and a respective reference voltage
- Such a converter finds its application in particular in a high fidelity amplifier with high linearity and low rate of thermal distortion. It is common, in such an amplifier, to use as input, a digital-to-analog converter such as the PCM 1792 component of Texas Instrument. This converter has a current output, so that the analog signal is modulated in intensity.
- Digital-to-analog converters with current output are particularly appreciated since they are insensitive to thermal distortion, these operating at constant power.
- the current sources are switched between the mass or an output fixed to a virtual mass traditionally produced by an amplifier with operational amplifier.
- all the transistors of the converter operate at constant current and voltage, therefore at constant power, whatever the modulation of the output signal.
- the difficulty of preserving this absence of thermal distortion is reported on the following two stages, namely, the current-voltage converter and the associated voltage gain stage.
- the current-voltage converter is made from an operational amplifier assembly whose output is limited to a few volts of amplitude.
- the operational amplifier is followed by a transistor assembly to ensure a rise in voltage.
- the invention aims to provide a current-voltage converter incorporating a gain stage, which degrades less the performance of the digital-analog converter such as the PCM 1792 placed upstream.
- the object of the invention is a current-voltage converter with a current reflector of the aforementioned type, characterized in that it comprises a cascode stage connected in series with each constant current generator to impose a constant potential difference at the same time. terminals of each constant current generator regardless of the output voltage.
- the converter comprises one or more of the following characteristics:
- the converter comprises a cascode stage connected in series at the input for the current to be converted;
- the input for the current to be converted is connected to the output through one of the cascode stages connected in series with the constant current generators;
- the converter comprises, for each cascode stage, means for reinjecting a current equal to the current absorbed in the current reflector circuit;
- the converter comprises, for each cascode stage, means for measuring the current absorbed for the cascode stage;
- the current measurement means comprise a measuring current mirror circuit mounted on the gate control circuit of each transistor of a cascode stage, and the means for reinjecting the current absorbed into the current reflector circuit comprise means of summation and inversion of the sign of the two currents obtained at the output of the measuring current mirrors, the output of the summing and inversion means being connected to the current mirror circuit for the injection into the current reflector circuit of the opposite of the sum of currents obtained at the output of the measurement current mirror circuits;
- the means for summing and inverting the sign of the two currents obtained at the output of the measurement current mirrors comprise, for each current mirror, a sign-reversing current mirror connected in series, the outputs of the two current mirrors sign inversion being connected together to the current reflector circuit;
- the means for reinjecting the current absorbed comprise means for injecting a connection signal into the current generator associated with the cascode stage so that the current generator provides an increased current of the current absorbed by the cascode stage;
- the reinjection means are capable of reinjecting a current equal to the current absorbed into the current reflector circuit for audible frequencies, such as frequencies below 20 kHz, and the converter comprises means for stabilizing the voltage delivered on the output to reduce the rate of current feedback for frequencies above audible frequencies, such as frequencies above 20 kHz, the feedback rate being equal to the amount of reinjected current divided by the amount of current absorbed;
- the stabilization means comprise a low-pass filter
- the converter has no operational amplifier.
- the difference in intensity between the two sources of constant current is equal to the fixed component of the input current.
- the invention also relates to an input stage of a high fidelity amplifier with high linearity and low distortion rate comprising a current-output digital-to-analog converter and a current-voltage converter as defined above.
- the invention also relates to a high fidelity amplifier with high linearity and low distortion rate comprising an input stage as defined above and an amplification stage, no voltage gain stage being interposed between the current-voltage converter and the amplification stage.
- the amplifier has the following characteristic:
- the conversion resistor has a value greater than or equal to the difference between the extreme values of the output voltage of the amplification stage divided by the difference between the extreme values of the intensity of the input current of the current converter; voltage.
- FIG. 1 is a schematic view of a high fidelity amplifier according to the invention
- FIG. 2 is an electrical diagram of the current-voltage converter of the amplifier of FIG. 1 according to a first embodiment
- FIGS. 3 and 4 are electrical diagrams of alternative embodiments of the current-voltage converter of FIG. 2;
- FIG. 5 is a set of curves illustrating the frequency responses for the three embodiments of FIGS. 2 to 4 of the current-voltage converter.
- Amplifier 10, shown diagrammatically in FIG. 1, is a high fidelity amplifier able to receive an input 12 on a digital signal and to output an amplified analog signal.
- the amplifier comprises an input stage 16 for converting the digital input signal into a voltage modulated analog output signal, as well as an amplification stage 18, ensuring the provision of a sufficient power for the load placed downstream, namely one or more speakers. It is preferably a class A amplification stage.
- the input stage 16 comprises a digital-to-analog converter 20 whose input is connected to the input 12 of the amplifier for receiving a digital signal Lmeric- This digital-analog converter is able to output an analog signal modulated current I m0 duié- the digital to analog converter is for example a PCM 1792 Texas Instruments company.
- the output of the digital-to-analog converter 20 is connected to a current-voltage converter 22 according to the invention.
- This converter is able to supply a voltage V modU
- the output of converter 22 is connected to the input of the amplifier stage 18 as known per se.
- Figure 2 is illustrated the input stage 16.
- the digital-to-analog converter 20 is schematized by a current source.
- the current-voltage converter 22 has an input 24 connected at the output of the digital-analog converter 20 and a voltage output 26 able to be connected directly to the amplification stage 18.
- the current-voltage converter 22 comprises two voltage sources 28, one of whose terminals is connected to ground and whose other terminal supplies two DC voltage buses 32, 34, one being maintained at a constant potential of + 50 V and the other maintained at a constant voltage of -50 V with respect to the mass.
- the current-voltage converter 22 comprises a conversion resistor 36, one terminal of which is connected to the output 26, and the other terminal of which is connected to ground.
- the input 24 of the converter is connected to the terminal of the resistor 36 constituting the output 26 of the converter through a current reflector circuit 38 capable of ensuring transmission of the entire modulation current I modU
- the output current of the digital-to-analog converter 22 comprises a DC component of 6.2 mA and a variable component varying between -4 and +4 mA.
- the current reflector circuit 38 is able to cancel the DC component.
- the current reflector circuit comprises a first constant current generator 40 connecting the DC bus 32 to the output 26 and a second constant current generator 42 connecting the output 26 to the voltage bus 24.
- the current generators 40 and 42 are perfect current generators, the generator 40 being able to provide an intensity greater than 6.2 mA and the current generator 42 being able to provide an intensity equal to that of the generator 40 increased of 6.2 mA.
- variable component of the output current of the digital-to-analog converter 20 is entirely directed into the resistor 36, performing a current-voltage conversion whose linearity limitation resides only in the defects of the resistor 36.
- the conversion resistor 36 has a value greater than or equal to the difference between the extreme values of the output voltage of the amplification stage 18 divided by the difference between the extreme values of the intensity I m0C i u i é of the input current of the current-voltage converter 22.
- a first cascode stage 44 is connected in series between the generator 40 and the output
- a second cascode stage 46 is interposed between the current source 42 and the output 26.
- These two cascode stages each comprise an MOS transistor 44A, 46A whose drain is connected to the output 26 and whose source is connected to the current generator 40 and 42.
- the gates of the two transistors 40, 46 are each maintained at a fixed voltage. + 45.3 V and - 45.3 V, respectively for the transistors 44 and 46.
- the gates of the transistors 44, 46 are respectively connected to the voltage buses 32, 34 by a zener diode 48, 50.
- a resistor 52 ensuring the circulation of a low intensity current through the diodes 48, 50 connects the anode of the diode 48 to the cathode of the diode 50. This resistance has for example a value of 100 k ⁇ .
- the input 24 of the current-voltage converter is connected between the cascode stage 46 and the current generator 42.
- an additional cascode stage 54 is disposed between the input 24 of the converter and the current reflector circuit 38 to which it is connected.
- This cascode stage comprises a transistor MOS type 54A whose source is connected to the input 24. The drain is connected to the current reflector circuit 38 and the gate is connected to ground. It will be understood that the cascode stages 44 and 46 make it possible for the current sources 40, 42 to have no voltage variation at their terminals when the output voltage at the point 26 varies even by several tens of volts.
- the cascode stages 44, 46 ensure that the voltage differences across the current generator terminals 40, 42 are constantly equal to 2.7 V, regardless of the output voltage of the circuit. This voltage across the current generator terminals is fixed to the fixed voltage of 4.7 V across the diodes 48, 50 minus the fixed voltage, for example equal to 2 V between the gate and the source of each transistor 44A, 46A.
- the cascode stage 54 ensures that the voltage at the output of the digital-to-analog converter 20 is maintained in the range of 0 to 5 V, to compensate for the fact that the digital-to-analog converter does not act as a source of perfect current.
- FIGS. 3 and 4 provide a solution to the charge and discharge of parasitic capacitors by eliminating the resulting harmonic distortion, which can reach a relatively high level of the order of -70 dBc.
- Figure 3 shows the elements of Figure 2 supplemented by additional elements.
- the elements identical or corresponding to those of Figure 2 are designated by the same reference numbers and will not be described in detail again, since they are connected identically.
- the constant current generators 40, 42 are each formed of a resistor 124, 126 of which one terminal is connected to the respective voltage bus 32, 34, and the other terminal is connected to the cascode stage 44, 46 associated, through a transistor MOS type 128, 130 whose gate is respectively connected to the voltage bus 32 and 34 by a zener diode respectively 132, 134.
- the grids and anodes of the diodes 132, 134 are connected by a resistor 136 adapted to ensure the flow of a current through the diodes 132, 134 in reverse bias or zen.
- the gates of the transistors 44A, 46A of the cascode stages 44, 46 are interconnected by a current generator 138 able to establish a constant current of the order of 0.8 mA.
- the current generator terminal 138 connected to the gate of the transistor 44 is connected to the voltage bus by a resistor 140 while the other terminal of the generator connected to the gate of the transistor 46A is connected to the voltage bus 44 by a resistor 142.
- the circuit of FIG. 3 comprises means 144, 146 for measuring the current absorbed by the cascode stage 44, 46 and means for reinjecting a current equal to the current absorbed in the current reflector circuit 38.
- These means 144, 146 are formed, in the embodiment of FIG. 3, by a link respectively comprising in series a capacitor 150, 152 and a resistor 154, 156. This link connects the gate of the transistors 44A, 46A to the terminals of the resistors 124, 126 connected to cascode stages 44, 46 through transistors 128, 130.
- the reinjection means are, for example, adapted to reinject a current equal to the current absorbed in the current reflector circuit 38 for the audible frequencies, such as frequencies below 20 kHz, and the circuits 144, 146 comprise stabilizing means the voltage delivered on the output 26 to reduce the rate of current feedback for frequencies above the audible frequencies, such as frequencies above 20 kHz.
- the reinjection rate is equal to the amount of reinjected current divided by the amount of current absorbed.
- a capacitor 158, 160 is disposed between each voltage bus 32, 34 and the gate of the transistors 44A, 46A. These capacitors 158, 160 form, with the resistors 154, 156, a low-pass filter, avoiding correction for frequencies higher than the audible frequencies.
- the circuits 144, 146 do not include a capacitor disposed between each voltage bus 32, 34 and the gate of the transistors 44A, 46A, the correction then also being carried out for the high frequencies, such as the frequencies greater than 20 kHz .
- circuits 144, 146 act to correct the current generators 40,
- the circuits 144 and 146 act as an error current trap, the error current being the current through the gates of the transistors 44A and 46A which should ideally have remained through the drain-source dipole of these transistors. This current is trapped in the sense that it is reinjected, inside the current sources 40 and 42, into the same branch from which it has escaped, the drain-source junction of transistors 44A and 46A, which junction conveys the summed current through output resistor 36.
- FIG. 4 shows another embodiment in which elements identical or corresponding to those of FIG. 2 are designated by the same reference numerals.
- the means for measuring the current absorbed by each cascode stage 44, 46 comprise a current mirror circuit 224, 226 whose input branch is placed on the control circuit of the gate of each transistor 44A, 46A.
- each current mirror circuit comprises two MOS type transistors, whose gates are interconnected, the input branch transistor is connected in series with a resistor and is interposed between the DC voltage bus 32 , 34 and the zener diode 48, 50.
- the output branches of the current mirror circuits 224, 226 also consisting of a transistor in series with a resistor are connected to the input branches of another current mirror circuit 244. , 246 each forming an inverter. These current mirror circuits have their output branches connected together at the point of connection of the input 24 to the current reflector circuit 38.
- the current mirror circuits 244, 246 forming an inverter and whose outputs are connected, ensuring a feedback in the reflector circuit 38 of the current absorbed by the transistors 44A, 46A, this current being measured in the control branches of these transistors by the current mirror circuits 224, 226.
- FIG. 5 shows the respective frequency responses of the circuits of FIGS. 2, 3 and 4. Each frequency response contains a combination of an expected fundamental frequency and unwanted harmonic frequencies corresponding to the harmonic distortion of the circuit response.
- Curve 402 shown in strong solid line, shows the response of the circuit of FIG. 2, curve 403 in solid continuous line, the response for the circuit of FIG. 3, and the dotted curve, the response for the circuit of FIG. Figure 4.
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Amplifiers (AREA)
Abstract
Description
Claims
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR1051541 | 2010-03-03 | ||
PCT/FR2010/050473 WO2011107671A1 (fr) | 2010-03-03 | 2010-03-16 | Convertisseur courant-tension à réflecteur de courant, étage d'entrée d'un amplificateur et amplificateur correspondant |
Publications (2)
Publication Number | Publication Date |
---|---|
EP2543136A1 true EP2543136A1 (fr) | 2013-01-09 |
EP2543136B1 EP2543136B1 (fr) | 2017-03-08 |
Family
ID=42703556
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP10719533.1A Active EP2543136B1 (fr) | 2010-03-03 | 2010-03-16 | Convertisseur courant-tension à réflecteur de courant, étage d'entrée d'un amplificateur et amplificateur correspondant |
Country Status (7)
Country | Link |
---|---|
US (1) | US8901998B2 (fr) |
EP (1) | EP2543136B1 (fr) |
JP (1) | JP5711273B2 (fr) |
KR (1) | KR101805557B1 (fr) |
CN (1) | CN102884723B (fr) |
BR (1) | BR112012022176B8 (fr) |
WO (1) | WO2011107671A1 (fr) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR3024305B1 (fr) | 2014-07-23 | 2018-03-30 | Devialet | Etage d'entree d'un amplificateur et amplificateur correspondant |
FR3024306B1 (fr) | 2014-07-23 | 2018-03-30 | Devialet | Convertisseur courant-tension, etage d'entree d'un amplificateur et amplificateur correspondant |
US9590504B2 (en) | 2014-09-30 | 2017-03-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Flipped gate current reference and method of using |
FR3048315B1 (fr) | 2016-02-26 | 2019-06-28 | Devialet | Convertisseur courant-tension, etage d'entree d'un amplificateur et amplificateur correspondant. |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5912603A (ja) * | 1982-07-13 | 1984-01-23 | Toshiba Corp | カスコ−ド回路 |
US4563655A (en) * | 1984-04-02 | 1986-01-07 | Hewlett-Packard Company | AGC Circuit |
US5451909A (en) * | 1993-02-22 | 1995-09-19 | Texas Instruments Incorporated | Feedback amplifier for regulated cascode gain enhancement |
US6954053B2 (en) * | 2002-07-10 | 2005-10-11 | Atmel Corporation | Interface for shunt voltage regulator in a contactless smartcard |
US6963244B1 (en) * | 2003-12-12 | 2005-11-08 | Analog Devices, Inc. | Common mode linearized input stage and amplifier topology |
DE602005025760D1 (de) * | 2004-06-15 | 2011-02-17 | Analog Devices Inc | Chopper-stabilisierter präzisions-stromspiegel |
US7164317B1 (en) * | 2004-12-03 | 2007-01-16 | National Semiconductor Corporation | Apparatus and method for a low-voltage class AB amplifier with split cascode |
-
2010
- 2010-03-16 CN CN201080066591.2A patent/CN102884723B/zh active Active
- 2010-03-16 KR KR1020127025631A patent/KR101805557B1/ko active IP Right Grant
- 2010-03-16 JP JP2012555462A patent/JP5711273B2/ja active Active
- 2010-03-16 BR BR112012022176A patent/BR112012022176B8/pt active IP Right Grant
- 2010-03-16 US US13/582,333 patent/US8901998B2/en active Active
- 2010-03-16 WO PCT/FR2010/050473 patent/WO2011107671A1/fr active Application Filing
- 2010-03-16 EP EP10719533.1A patent/EP2543136B1/fr active Active
Non-Patent Citations (1)
Title |
---|
See references of WO2011107671A1 * |
Also Published As
Publication number | Publication date |
---|---|
US8901998B2 (en) | 2014-12-02 |
CN102884723B (zh) | 2016-01-20 |
KR101805557B1 (ko) | 2017-12-07 |
BR112012022176B1 (pt) | 2020-12-15 |
KR20130009801A (ko) | 2013-01-23 |
JP2013527997A (ja) | 2013-07-04 |
WO2011107671A1 (fr) | 2011-09-09 |
JP5711273B2 (ja) | 2015-04-30 |
BR112012022176B8 (pt) | 2021-01-05 |
EP2543136B1 (fr) | 2017-03-08 |
CN102884723A (zh) | 2013-01-16 |
US20130057351A1 (en) | 2013-03-07 |
BR112012022176A2 (pt) | 2016-10-25 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
EP1916762B1 (fr) | Oscillateur à quartz asservi en amplitude avec domaine étendu de tension et de température | |
FR2819064A1 (fr) | Regulateur de tension a stabilite amelioree | |
FR2800937A1 (fr) | Circuit de commutation de courant et convertisseur numerique-analogique utilisant ce circuit | |
EP2543136B1 (fr) | Convertisseur courant-tension à réflecteur de courant, étage d'entrée d'un amplificateur et amplificateur correspondant | |
EP0562905B1 (fr) | Circuit à retard variable | |
EP1771944B1 (fr) | Amplificateur audio classe ad | |
EP0278534B1 (fr) | Déphaseur large bande | |
EP1885057B1 (fr) | Compensation en fréquence d'un amplificateur comportant au moins deux étages de gain | |
EP3172837B1 (fr) | Convertisseur courant-tension, étage d'entrée d'un amplificateur et amplificateur correspondant | |
FR2943826A1 (fr) | Systeme de couplage tele-alimente avec une liaison filaire de communication, et appareil de commande d'au moins un interrupteur electronique comprenant un tel systeme de couplage | |
EP2543140A1 (fr) | Amplificateur de classe a de type push-pull | |
EP2182631A2 (fr) | Cellule amplificatrice hyperfréquences large bande à gain variable et amplificateur comportant une telle cellule | |
FR3048315B1 (fr) | Convertisseur courant-tension, etage d'entree d'un amplificateur et amplificateur correspondant. | |
FR2818762A1 (fr) | Regulateur de tension a gain statique en boucle ouverte reduit | |
FR2744304A1 (fr) | Convertisseur numerique-analogique differentiel a fonction de filtrage et compensation de decalage | |
FR2843250A1 (fr) | Convertisseur numerique-analogique comprenant des moyens pour ameliorer la linearite de conversion. | |
WO2012072503A1 (fr) | Cellule de commutation de puissance et équipement électronique correspondant | |
FR2602379A1 (fr) | Circuit repeteur de tension pour charges a composante ohmique, avec compensation de la distorsion harmonique | |
EP1922807A1 (fr) | Dispositif d'amplification d'une tension representative d'une information audiophonique | |
EP3172836B1 (fr) | Etage d'entrée d'un amplificateur et amplificateur correspondant | |
EP1414148B1 (fr) | Amplificateur de puissance pour systemes de transmission radiofrequences | |
FR2536224A1 (fr) | Amplificateur videofrequence | |
EP0166643A1 (fr) | Alimentation à découpage de puissance | |
FR3085563A1 (fr) | Etage de sortie classe a notamment pour casque audio | |
EP3501102A1 (fr) | Dispositif d'amplification comprenant un circuit de compensation |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PUAI | Public reference made under article 153(3) epc to a published international application that has entered the european phase |
Free format text: ORIGINAL CODE: 0009012 |
|
17P | Request for examination filed |
Effective date: 20120903 |
|
AK | Designated contracting states |
Kind code of ref document: A1 Designated state(s): AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO SE SI SK SM TR |
|
DAX | Request for extension of the european patent (deleted) | ||
17Q | First examination report despatched |
Effective date: 20140303 |
|
GRAP | Despatch of communication of intention to grant a patent |
Free format text: ORIGINAL CODE: EPIDOSNIGR1 |
|
INTG | Intention to grant announced |
Effective date: 20160921 |
|
GRAS | Grant fee paid |
Free format text: ORIGINAL CODE: EPIDOSNIGR3 |
|
GRAA | (expected) grant |
Free format text: ORIGINAL CODE: 0009210 |
|
AK | Designated contracting states |
Kind code of ref document: B1 Designated state(s): AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO SE SI SK SM TR |
|
REG | Reference to a national code |
Ref country code: GB Ref legal event code: FG4D Free format text: NOT ENGLISH |
|
REG | Reference to a national code |
Ref country code: CH Ref legal event code: EP Ref country code: AT Ref legal event code: REF Ref document number: 874359 Country of ref document: AT Kind code of ref document: T Effective date: 20170315 |
|
REG | Reference to a national code |
Ref country code: FR Ref legal event code: PLFP Year of fee payment: 8 |
|
REG | Reference to a national code |
Ref country code: IE Ref legal event code: FG4D Free format text: LANGUAGE OF EP DOCUMENT: FRENCH |
|
REG | Reference to a national code |
Ref country code: DE Ref legal event code: R096 Ref document number: 602010040565 Country of ref document: DE |
|
REG | Reference to a national code |
Ref country code: LT Ref legal event code: MG4D |
|
REG | Reference to a national code |
Ref country code: NL Ref legal event code: MP Effective date: 20170308 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: HR Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20170308 Ref country code: LT Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20170308 Ref country code: FI Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20170308 Ref country code: GR Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20170609 Ref country code: NO Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20170608 |
|
REG | Reference to a national code |
Ref country code: AT Ref legal event code: MK05 Ref document number: 874359 Country of ref document: AT Kind code of ref document: T Effective date: 20170308 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: SE Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20170308 Ref country code: LV Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20170308 Ref country code: ES Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20170308 Ref country code: BG Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20170608 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: NL Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20170308 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: IT Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20170308 Ref country code: CZ Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20170308 Ref country code: EE Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20170308 Ref country code: AT Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20170308 Ref country code: SK Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20170308 Ref country code: RO Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20170308 |
|
REG | Reference to a national code |
Ref country code: CH Ref legal event code: PL |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: SM Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20170308 Ref country code: PT Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20170710 Ref country code: PL Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20170308 Ref country code: IS Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20170708 |
|
REG | Reference to a national code |
Ref country code: DE Ref legal event code: R097 Ref document number: 602010040565 Country of ref document: DE |
|
REG | Reference to a national code |
Ref country code: IE Ref legal event code: MM4A |
|
PLBE | No opposition filed within time limit |
Free format text: ORIGINAL CODE: 0009261 |
|
STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: DK Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20170308 Ref country code: LU Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20170316 Ref country code: MC Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20170308 |
|
26N | No opposition filed |
Effective date: 20171211 |
|
REG | Reference to a national code |
Ref country code: FR Ref legal event code: PLFP Year of fee payment: 9 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: SI Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20170308 Ref country code: CH Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20170331 Ref country code: LI Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20170331 Ref country code: IE Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20170316 |
|
REG | Reference to a national code |
Ref country code: BE Ref legal event code: MM Effective date: 20170331 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: BE Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20170331 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: MT Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20170308 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: HU Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT; INVALID AB INITIO Effective date: 20100316 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: CY Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20170308 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: MK Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20170308 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: TR Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20170308 |
|
PGFP | Annual fee paid to national office [announced via postgrant information from national office to epo] |
Ref country code: FR Payment date: 20230209 Year of fee payment: 14 |
|
P01 | Opt-out of the competence of the unified patent court (upc) registered |
Effective date: 20230425 |
|
PGFP | Annual fee paid to national office [announced via postgrant information from national office to epo] |
Ref country code: DE Payment date: 20240307 Year of fee payment: 15 Ref country code: GB Payment date: 20240325 Year of fee payment: 15 |