EP2537183A2 - Shielding structure for transmission lines - Google Patents

Shielding structure for transmission lines

Info

Publication number
EP2537183A2
EP2537183A2 EP11745210A EP11745210A EP2537183A2 EP 2537183 A2 EP2537183 A2 EP 2537183A2 EP 11745210 A EP11745210 A EP 11745210A EP 11745210 A EP11745210 A EP 11745210A EP 2537183 A2 EP2537183 A2 EP 2537183A2
Authority
EP
European Patent Office
Prior art keywords
comb
metallization layer
electrically conducting
conducting vias
structures
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP11745210A
Other languages
German (de)
French (fr)
Other versions
EP2537183B1 (en
EP2537183A4 (en
Inventor
Shuxian Chen
Jeffrey T. Watt
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Altera Corp
Original Assignee
Altera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Altera Corp filed Critical Altera Corp
Publication of EP2537183A2 publication Critical patent/EP2537183A2/en
Publication of EP2537183A4 publication Critical patent/EP2537183A4/en
Application granted granted Critical
Publication of EP2537183B1 publication Critical patent/EP2537183B1/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/60—Capacitors
    • H10D1/62—Capacitors having potential barriers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/423—Shielding layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W42/00—Arrangements for protection of devices
    • H10W42/20—Arrangements for protection of devices protecting against electromagnetic or particle radiation, e.g. light, X-rays, gamma-rays or electrons

Definitions

  • This relates to shielding structures formed in the back end of integrated circuits.
  • a typical integrated circuit comprises a semiconductor substrate in and on which are defined a multitude of transistors and a series of metal interconnect layers on top of the substrate.
  • the interconnect layers are insulated from one another by intermetallic dielectric layers.
  • Interconnection paths are defined in the metallic layers and selective connections are made between the paths in the various layers so as to connect the transistors formed in the substrate to each other and to external connections.
  • FIGS. 1 A - IF depict cross-sections of several conventional shielding structures.
  • a microstrip 10 comprises a signal line 12 located above and insulated from a ground plane 14 that provides a current return path.
  • a pair of transmission lines may be used in place of a single signal line to provide differential-type signaling.
  • the signal line 12 is defined in one metallization layer
  • the ground plane 14 is defined in a second metallization layer
  • the signal line and ground plane are separated by at least one intermetallic dielectric layer.
  • ground plane 14 may be a continuous two-dimensional sheet with no openings in it or may comprise a plurality of metal strips connected together at each end in a ladder-like configuration as shown in the horizontal section of FIG. IB. Other patterns of connected metallization may also be used; and in some cases the ground plane can be the silicon substrate.
  • a co-planar waveguide (CPW) 20 comprises a signal line 22 located between two ground planes 24, 25.
  • each ground plane may be a continuous two-dimensional sheet with no openings or it may comprise a ladder-like array of connected strips as shown in FIG. IB. Other patterns of connected metallization may also be used.
  • a grounded co-planar waveguide (GCPW) 30 comprises a signal line 32 located between two ground planes 34, 35 and above a third ground plane 36.
  • the ground planes 34, 35 are electrically connected to ground plane 36 by electrically conductive sidewalls 38, 39.
  • signal line 32 and ground planes 34, 35 are defined in a first metallization layer
  • ground plane 36 is defined in a second metallization layer beneath the first layer
  • the first and second metallization layers are separated by at least one intermetallic dielectric layer.
  • ground plane 36 may be a continuous two- dimensional sheet with no openings or it may comprise a ladder-like array of connected strips as shown in FIG.
  • the sidewalls are formed using stacks of vias that extend between the upper and lower metallization layers. As shown in the lateral section of FIG. IE, a first plurality of electrically conducting via stacks 138 form a sidewall that connects upper ground plane 34 to lower ground plane 36 and a second plurality of electrically conducting via stacks similar to that of FIG. IE forms a sidewall that connects upper ground plane 35 to lower ground plane 36. Additional rows of electrically conducting vias may be connected in parallel to connect the upper and lower ground planes.
  • a stripline 50 comprises a signal line 52 located between an upper ground plane 54 and a lower ground plane 56.
  • the upper and lower ground planes are electrically connected by electrically conductive sidewalls 58, 59 so that the signal line is in the center of the region enclosed by the ground planes and sidewalls.
  • signal line 52 is defined in one metallization layer
  • ground plane 54 is defined in a second metallization layer above it
  • ground plane 56 is defined in a third metallization layer below it.
  • a first plurality of electrically conducting vias form a sidewall that connects upper ground plane 54 to lower ground plane 56 on one side of the signal line 52; and a second plurality of electrically conducting vias form a sidewall that connects upper ground plane 54 to lower ground plane 56 on the other side of signal line 52.
  • ground planes may be continuous two-dimensional sheets with no openings or ladder-like arrays of connected strips as shown in FIG. IB or some other pattern of connected metallization; and the vias may be similar to those shown in FIG. IE.
  • the advantages and disadvantages of several types of integrated circuit transmission lines are discussed, for example, at S. Pellerano et al., "A 64 GHz LNA with 15.5 dB Gain and 6.5 dB NF in 90 nm CMOS," IEEE J. of Solid-State Circuits. Vol. 43, No. 7. pp. 1543 - 52 (July 2008)
  • the present invention is an improved shielding structure that can be implemented in the metallization layers of an integrated circuit.
  • the improved shielding structure reduces parasitic coupling between the transmission line(s) and the shielding structure with the result that the shielding structure has lower insertion loss than prior art shielding structures. Further, it has a better signal/noise ratio.
  • the shielding structure comprises: first and second comb-like structures defined in a first metallization layer on an integrated circuit, each comb-like structure comprising a plurality of teeth, the teeth of each comb-like structure extending toward the other comb-like structure; a first plurality of electrically conducting vias extending upward from the first comb-like structure; a second plurality of electrically conducting vias extending upward from the second comblike structure; first and second planar structures in a second metallization layer above the first metallization layer; a third plurality of electrically conducting vias extending downward from the first planar structure toward the first plurality of electrically conducting vias; and a fourth plurality of electrically conducting vias extending downward from the second planar structure toward the second plurality of electrically conducting vias.
  • At least one signal line is located in the second metallization layer between the first and second planar structures; and the first and second comb-like structures, the first and second planar structures and the first, second, third, and fourth electrically conducting vias are all at substantially the same potential, which preferably is ground.
  • a pair of signal lines may be used to carry differential-type signals; the first and second planar structures may also be comb-like structures; and multiple rows of electrically conducting vias may extend from the planar structures and/or the comb-like structures.
  • the preferred embodiment may be regarded as a modification of a grounded co-planar waveguide, the invention may also be practiced in other types of waveguides such as microstrips and striplines.
  • FIGS. 1 A - 1 F are cross-sections of illustrative prior art waveguide structures
  • FIG. 2 is a perspective view of an illustrative embodiment of the invention
  • FIG. 3 is a cross-section along line 3-3 of FIG. 2
  • FIG. 4 is a cross-section along line 4-4 of FIG. 2
  • FIG. 5 is a perspective view of a second embodiment of the invention
  • FIG. 6 is a plot of transmission loss versus operating frequency for the shielding structure of the present invention and a prior art shielding structure
  • FIGS. 7 and 8 are horizontal sections of alternatives that may be used in the practice of the invention.
  • FIG. 2 is a perspective view of an illustrative embodiment of a shielding structure 200 of the present invention
  • FIGS. 3 and 4 are cross-sections along lines 3- 3 and 4-4, respectively, of FIG. 2.
  • Shielding structure 200 is formed in an integrated circuit in a plurality of metallization layers 211 - 214 on a semiconductor substrate 220.
  • the metallization layers are separated from each other and from substrate 220 by intermetallic dielectric layers 231 - 234 (shown in FIG. 4 but not shown in FIG. 2 for reasons of clarity).
  • Shielding structure 200 comprises first and second comb-like structures 240, 245 defined in first metallization layer 211, each comb-like structure comprising first and second pluralities of teeth 242, 247 that extend toward the other comb-like structure; a first plurality of electrically conducting vias 250 that extend upward from the first comb-like structure 240; a second plurality of electrically conducting vias 255 that extend upward from the second comb-like structure 245; first and second planar structures 260, 265 in a second metallization layer 214 above the first metallization layer; a third plurality of electrically conducting vias 270 that extend downward from the first planar structure 260 toward the first plurality of electrically conducting vias 250; and a fourth plurality of electrically conducting vias 275 that extend downward from the second planar structure 265 toward the second plurality of electrically conducting vias, 255.
  • Signal lines 280, 282 are located in metallization layer 214 between the first and second planar structures.
  • the first and second comb-like structures, the first and second planar structures, and the first, second, third and fourth electrically conducting vias are all at the same potential, preferably ground.
  • the metallization layers are the uppermost metallization layers of an integrated circuit.
  • metallization layer 214 might be the uppermost layer of the integrated circuit while metallization layer 211 might be several layers below it, the number of layers depending on various design criteria. In other cases, metallization layer 214 might not be the uppermost layer of the integrated circuit.
  • FIG. 3 A horizontal cross-section of metallization layer 211 along line 3 - 3 of FIG. 2 is shown in FIG. 3.
  • the first comb-like structure 240 comprises a first plurality of teeth 242; and the second comb-like structure 245 comprises a second plurality of teeth 247.
  • the teeth are parallel to one another.
  • the teeth of the first plurality are connected together by a first transverse element 244; and the teeth of the second plurality are connected together by a second transverse element 249.
  • the teeth of the first comb-like structure 240 extend between the teeth of the second comb-like structure 240 but they do not contact the teeth of the second comb-like structure. However, as indicated above, the teeth are at the same potential. To accomplish this, an electrical connection is maintained between the two comb-like structures if only through the ground connection. Alternatively, one or a small number ( ⁇ 10%) of the teeth of the two comb-like structures may be directly connected together (not shown).
  • the comb-like structures 240, 245 are formed by defining the structures in metallization layer 211 using well-known etching technology to define the appropriate patterns in the metallization layer...
  • FIG. 4 A vertical cross-section through vias 250, 270 along line 4 - 4 of FIG. 2 is shown in FIG. 4.
  • the vertical cross-section through vias 255, 275 is similar.
  • vias 250 extend upward in stacks 252 from metallization layer 211, through intermetallic dielectric layer 232, metallization layer 212, and intermetallic dielectric layer 233 to metallization layer 213.
  • stacks 252 do not reach metallization layer 214.
  • Vias 270 extend downward in stacks 272 from metallization layer 214, through intermetallic dielectric layer 234, metallization layer 213, and intermetallic dielectric layer 233 to metallization layer 212.
  • stacks 272 do not reach metallization layer 211.
  • vias 250 and vias 270 are at the same potential. To accomplish this, some of vias 250, 270 may be connected to each other by extending the via stack to the appropriate metallization layer or by connecting the stacks by metallization layers 212 and/or 213. Only a small number ⁇ 10%) of vias relative to the total number of vias should be connected in this way. Alternatively, the vias may be connected together through the ground connection.
  • the vias are formed by conventional semiconductor processes in which holes are etched in an intermetallic dielectric layer down to the metallic layer immediately below and the holes are then filled with a conducting material such as
  • the first and second planar structures may be comb-like structures; and multiple rows of electrically conducting vias may extend from the planar structures and/or the comb-like structures.
  • a stripline can be implemented in which first and second comb-like structures 540, 545 are defined in a lower metallization layer 51 1, third and fourth comb-like structures 560, 565 are defined in an upper metallization layer 515; and one or more signal lines 580, 582 are defined in a third metallization layer 513 located between the upper and lower metallization layers.
  • first and second comb-like structures 540, 545 are defined in a lower metallization layer 51 1
  • third and fourth comb-like structures 560, 565 are defined in an upper metallization layer 515
  • one or more signal lines 580, 582 are defined in a third metallization layer 513 located between the upper and lower metallization layers.
  • horizontal sections through both the lower metallization layer and the upper metallization layer are the same.as that depicted in FIG.3.
  • the stripline 4 may be formed by extending via stacks upwards from the comb-like structures in the lower metallization layer and downwards from the comb-like structures in the upper metallization layer.
  • the stripline is formed in five metallization layers 511 - 515; but the invention may be practiced using a greater number or a lesser number of metallization layers.
  • FIG. 6 A plot of simulated transmission loss versus frequency is set forth in FIG. 6. As shown therein, at 12.5 GHz the transmission loss for the waveguide of FIG. 2 is 10.1 dB/mm while the loss for the conventional waveguide is 12.6 dB/mm.
  • FIG. 3 depicts an arrangement in which each finger of comblike structure 240 extends between two fingers of comb-like structure 245, comb-like structures could be used where a pair of fingers 742 of one comb-like structure 740 extend between two pairs of fingers 747 of the second comb-like structure 745, as depicted in FIG. 7 or where a triplet of fingers 842 of one comb-like structure 840 extend between two triplets of fingers 847 of the second comb-like structure 845 as depicted in FIG. 8.
  • FIGS. 2 and 5 disclose structures in which the transmission lines are formed in the same metallization layer, structures may also be used in which the transmission lines are located in different metallization layers.

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Physics & Mathematics (AREA)
  • Health & Medical Sciences (AREA)
  • Electromagnetism (AREA)
  • Toxicology (AREA)
  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)

Abstract

A shielding structure comprises first and second comb-like structures defined in a first metallization layer on an integrated circuit, each comb-like structure comprising a plurality of teeth, the teeth of each comb-like structure extending toward the other comb- like structure; a first plurality of electrically conducting vias extending upward from the first comb-like structure; a second plurality of electrically conducting vias extending upward from the second comb-like structure; first and second planar structures in a second metallization layer above the first metallization layer; a third plurality of electrically conducting vias extending downward from the first planar structure toward the first plurality of electrically conducting vias; and a fourth plurality of electrically conducting vias extending downward from the second planar structure toward the second plurality of electrically conducting vias. The first and second comb-like structures, the first and second planar structures and the first, second, third, and fourth electrically conducting vias all being at substantially the same potential, preferably ground. In one embodiment, one or more signal lines are located in the second metallization layer between the first and second planar structures; and in another embodiment they are located in a third metallization layer between the first and second metallization layers.

Description

SHIELDING STRUCTURE FOR TRANSMISSION LINES
BACKGROUND OF THE INVENTION
[0001] This relates to shielding structures formed in the back end of integrated circuits.
[0002] A typical integrated circuit comprises a semiconductor substrate in and on which are defined a multitude of transistors and a series of metal interconnect layers on top of the substrate. The interconnect layers are insulated from one another by intermetallic dielectric layers. Interconnection paths are defined in the metallic layers and selective connections are made between the paths in the various layers so as to connect the transistors formed in the substrate to each other and to external connections. For additional information, see, for example, Plummer et al, Silicon VLSI Technology, ch. 11 (Prentice Hall, 2000); Doering et al (ed.), Handbook of Semiconductor
Manufacturing Technolgy (2nd ed.) (CRC Press 2008).
[0003] In recent years, the frequencies of signals transmitted on some of the interconnection paths of an integrated circuit have risen into the GigaHertz(GHz) range. At these frequencies, it becomes desirable to shield the interconnection path; and shielding structures used for many years in conventional microwave technology have been adapted for use in integrated circuits. FIGS. 1 A - IF depict cross-sections of several conventional shielding structures. In the transverse section of FIG. 1A, a microstrip 10 comprises a signal line 12 located above and insulated from a ground plane 14 that provides a current return path. In other embodiments, a pair of transmission lines may be used in place of a single signal line to provide differential-type signaling. When implemented in an integrated circuit, the signal line 12 is defined in one metallization layer, the ground plane 14 is defined in a second metallization layer and the signal line and ground plane are separated by at least one intermetallic dielectric layer.
Illustratively, ground plane 14 may be a continuous two-dimensional sheet with no openings in it or may comprise a plurality of metal strips connected together at each end in a ladder-like configuration as shown in the horizontal section of FIG. IB. Other patterns of connected metallization may also be used; and in some cases the ground plane can be the silicon substrate.
[0004] In the transverse section of FIG. 1 C, a co-planar waveguide (CPW) 20 comprises a signal line 22 located between two ground planes 24, 25. When
implemented in an integrated circuit, the signal line and ground planes of the coplanar waveguide are all implemented in the same metallization layer and insulated from the substrate of the integrated circuit by at least one intermetallic dielectric layer. Again, each ground plane may be a continuous two-dimensional sheet with no openings or it may comprise a ladder-like array of connected strips as shown in FIG. IB. Other patterns of connected metallization may also be used.
[0005] In the transverse section of FIG. 1 D, a grounded co-planar waveguide (GCPW) 30 comprises a signal line 32 located between two ground planes 34, 35 and above a third ground plane 36. The ground planes 34, 35 are electrically connected to ground plane 36 by electrically conductive sidewalls 38, 39. When implemented in an integrated circuit, signal line 32 and ground planes 34, 35 are defined in a first metallization layer, ground plane 36 is defined in a second metallization layer beneath the first layer, and the first and second metallization layers are separated by at least one intermetallic dielectric layer. Illustratively, ground plane 36 may be a continuous two- dimensional sheet with no openings or it may comprise a ladder-like array of connected strips as shown in FIG. IB or another pattern of connected metallization. The sidewalls are formed using stacks of vias that extend between the upper and lower metallization layers. As shown in the lateral section of FIG. IE, a first plurality of electrically conducting via stacks 138 form a sidewall that connects upper ground plane 34 to lower ground plane 36 and a second plurality of electrically conducting via stacks similar to that of FIG. IE forms a sidewall that connects upper ground plane 35 to lower ground plane 36. Additional rows of electrically conducting vias may be connected in parallel to connect the upper and lower ground planes.
[0006] In the transverse section of FIG. IF, a stripline 50 comprises a signal line 52 located between an upper ground plane 54 and a lower ground plane 56. Optionally, the upper and lower ground planes are electrically connected by electrically conductive sidewalls 58, 59 so that the signal line is in the center of the region enclosed by the ground planes and sidewalls. When stripline 50 is implemented in an integrated circuit, signal line 52 is defined in one metallization layer, ground plane 54 is defined in a second metallization layer above it and ground plane 56 is defined in a third metallization layer below it. Optionally, a first plurality of electrically conducting vias form a sidewall that connects upper ground plane 54 to lower ground plane 56 on one side of the signal line 52; and a second plurality of electrically conducting vias form a sidewall that connects upper ground plane 54 to lower ground plane 56 on the other side of signal line 52.
Again, the ground planes may be continuous two-dimensional sheets with no openings or ladder-like arrays of connected strips as shown in FIG. IB or some other pattern of connected metallization; and the vias may be similar to those shown in FIG. IE. The advantages and disadvantages of several types of integrated circuit transmission lines are discussed, for example, at S. Pellerano et al., "A 64 GHz LNA with 15.5 dB Gain and 6.5 dB NF in 90 nm CMOS," IEEE J. of Solid-State Circuits. Vol. 43, No. 7. pp. 1543 - 52 (July 2008)
SUMMARY OF THE PRESENT INVENTION
[0007] The present invention is an improved shielding structure that can be implemented in the metallization layers of an integrated circuit. The improved shielding structure reduces parasitic coupling between the transmission line(s) and the shielding structure with the result that the shielding structure has lower insertion loss than prior art shielding structures. Further, it has a better signal/noise ratio.
[0008] In a preferred embodiment of the invention, the shielding structure comprises: first and second comb-like structures defined in a first metallization layer on an integrated circuit, each comb-like structure comprising a plurality of teeth, the teeth of each comb-like structure extending toward the other comb-like structure; a first plurality of electrically conducting vias extending upward from the first comb-like structure; a second plurality of electrically conducting vias extending upward from the second comblike structure; first and second planar structures in a second metallization layer above the first metallization layer; a third plurality of electrically conducting vias extending downward from the first planar structure toward the first plurality of electrically conducting vias; and a fourth plurality of electrically conducting vias extending downward from the second planar structure toward the second plurality of electrically conducting vias. At least one signal line is located in the second metallization layer between the first and second planar structures; and the first and second comb-like structures, the first and second planar structures and the first, second, third, and fourth electrically conducting vias are all at substantially the same potential, which preferably is ground.
[0009] Numerous variations may be practiced in the preferred embodiment. For example, a pair of signal lines may be used to carry differential-type signals; the first and second planar structures may also be comb-like structures; and multiple rows of electrically conducting vias may extend from the planar structures and/or the comb-like structures.
[0010] While the preferred embodiment may be regarded as a modification of a grounded co-planar waveguide, the invention may also be practiced in other types of waveguides such as microstrips and striplines.
BRIEF DESCRIPTION OF THE DRAWINGS
[0011] These and other objects and advantages of the present invention will be apparent to those of ordinary skill in the art in view of the following detailed description in which:
[0012] FIGS. 1 A - 1 F are cross-sections of illustrative prior art waveguide structures;
[0013] FIG. 2 is a perspective view of an illustrative embodiment of the invention; [0014] FIG. 3 is a cross-section along line 3-3 of FIG. 2; [0015] FIG. 4 is a cross-section along line 4-4 of FIG. 2; [0016] FIG. 5 is a perspective view of a second embodiment of the invention;
[0017] FIG. 6 is a plot of transmission loss versus operating frequency for the shielding structure of the present invention and a prior art shielding structure; and
[0018] FIGS. 7 and 8 are horizontal sections of alternatives that may be used in the practice of the invention.
DETAILED DESCRIPTION
[0019] FIG. 2 is a perspective view of an illustrative embodiment of a shielding structure 200 of the present invention; and FIGS. 3 and 4 are cross-sections along lines 3- 3 and 4-4, respectively, of FIG. 2. Shielding structure 200 is formed in an integrated circuit in a plurality of metallization layers 211 - 214 on a semiconductor substrate 220. The metallization layers are separated from each other and from substrate 220 by intermetallic dielectric layers 231 - 234 (shown in FIG. 4 but not shown in FIG. 2 for reasons of clarity). Shielding structure 200 comprises first and second comb-like structures 240, 245 defined in first metallization layer 211, each comb-like structure comprising first and second pluralities of teeth 242, 247 that extend toward the other comb-like structure; a first plurality of electrically conducting vias 250 that extend upward from the first comb-like structure 240; a second plurality of electrically conducting vias 255 that extend upward from the second comb-like structure 245; first and second planar structures 260, 265 in a second metallization layer 214 above the first metallization layer; a third plurality of electrically conducting vias 270 that extend downward from the first planar structure 260 toward the first plurality of electrically conducting vias 250; and a fourth plurality of electrically conducting vias 275 that extend downward from the second planar structure 265 toward the second plurality of electrically conducting vias, 255. Signal lines 280, 282 are located in metallization layer 214 between the first and second planar structures. The first and second comb-like structures, the first and second planar structures, and the first, second, third and fourth electrically conducting vias are all at the same potential, preferably ground.
[0020] Preferably, the metallization layers are the uppermost metallization layers of an integrated circuit. By way of example but not limitation, metallization layer 214 might be the uppermost layer of the integrated circuit while metallization layer 211 might be several layers below it, the number of layers depending on various design criteria. In other cases, metallization layer 214 might not be the uppermost layer of the integrated circuit.
[0021] A horizontal cross-section of metallization layer 211 along line 3 - 3 of FIG. 2 is shown in FIG. 3. As shown therein, the first comb-like structure 240 comprises a first plurality of teeth 242; and the second comb-like structure 245 comprises a second plurality of teeth 247. The teeth are parallel to one another. The teeth of the first plurality are connected together by a first transverse element 244; and the teeth of the second plurality are connected together by a second transverse element 249. As shown in FIG. 3, the teeth of the first comb-like structure 240 extend between the teeth of the second comb-like structure 240 but they do not contact the teeth of the second comb-like structure. However, as indicated above, the teeth are at the same potential. To accomplish this, an electrical connection is maintained between the two comb-like structures if only through the ground connection. Alternatively, one or a small number (< 10%) of the teeth of the two comb-like structures may be directly connected together (not shown).
[0022] The comb-like structures 240, 245 are formed by defining the structures in metallization layer 211 using well-known etching technology to define the appropriate patterns in the metallization layer...
[0023] A vertical cross-section through vias 250, 270 along line 4 - 4 of FIG. 2 is shown in FIG. 4. The vertical cross-section through vias 255, 275 is similar. As shown in FIG. 4, vias 250 extend upward in stacks 252 from metallization layer 211, through intermetallic dielectric layer 232, metallization layer 212, and intermetallic dielectric layer 233 to metallization layer 213. Thus, stacks 252 do not reach metallization layer 214. Vias 270 extend downward in stacks 272 from metallization layer 214, through intermetallic dielectric layer 234, metallization layer 213, and intermetallic dielectric layer 233 to metallization layer 212. Thus, stacks 272 do not reach metallization layer 211. In addition, while stacks 252 extend between stacks 272, they do not contact each other at metallization layers 212 or 213. However, as indicated above, vias 250 and vias 270 are at the same potential. To accomplish this, some of vias 250, 270 may be connected to each other by extending the via stack to the appropriate metallization layer or by connecting the stacks by metallization layers 212 and/or 213. Only a small number {< 10%) of vias relative to the total number of vias should be connected in this way. Alternatively, the vias may be connected together through the ground connection.
[0024] The vias are formed by conventional semiconductor processes in which holes are etched in an intermetallic dielectric layer down to the metallic layer immediately below and the holes are then filled with a conducting material such as
g aluminum or copper. Well known processes are then used to form the next metallic layer on top of the dielectric layer so that it is electrically connected to the filled holes; and this layer is then etched to separate the via stacks. A dielectric layer is then formed on the metallic layer; and the process is repeated to form the next layer of vias in the stacks. Further details on the via formation process may be found at pages 702 - 706 of
Plummer, cited above, which are hereby incorporated by reference herein.
[0025] Numerous variations may be practiced in the embodiment depicted in FIG. 2. For example, a single signal line may be used instead of the pair of signal lines 280, 282. The first and second planar structures may be comb-like structures; and multiple rows of electrically conducting vias may extend from the planar structures and/or the comb-like structures.
[0026] The invention may also be practiced used other waveguide configurations. For example, as shown in FIG. 5, a stripline can be implemented in which first and second comb-like structures 540, 545 are defined in a lower metallization layer 51 1, third and fourth comb-like structures 560, 565 are defined in an upper metallization layer 515; and one or more signal lines 580, 582 are defined in a third metallization layer 513 located between the upper and lower metallization layers. Illustratively, horizontal sections through both the lower metallization layer and the upper metallization layer are the same.as that depicted in FIG.3. Optionally, sidewalls similar to those depicted in FIG. 4 may be formed by extending via stacks upwards from the comb-like structures in the lower metallization layer and downwards from the comb-like structures in the upper metallization layer. In the illustrative embodiment of FIG. 5, the stripline is formed in five metallization layers 511 - 515; but the invention may be practiced using a greater number or a lesser number of metallization layers.
[0027] Practice of the invention has been observed to reduce waveguide insertion loss by approximately 20% compared to a conventional grounded co-planar waveguide such as that depicted in FIGS ID, IB and IE. A plot of simulated transmission loss versus frequency is set forth in FIG. 6. As shown therein, at 12.5 GHz the transmission loss for the waveguide of FIG. 2 is 10.1 dB/mm while the loss for the conventional waveguide is 12.6 dB/mm.
[0028) As will be apparent to those skilled in the art, numerous variations may be practiced within the spirit and scope of the present invention. For example, while horizontal cross-section of FIG. 3 depicts an arrangement in which each finger of comblike structure 240 extends between two fingers of comb-like structure 245, comb-like structures could be used where a pair of fingers 742 of one comb-like structure 740 extend between two pairs of fingers 747 of the second comb-like structure 745, as depicted in FIG. 7 or where a triplet of fingers 842 of one comb-like structure 840 extend between two triplets of fingers 847 of the second comb-like structure 845 as depicted in FIG. 8. Even larger groupings of fingers might be used; and groupings of different numbers of fingers can be used at different places in the comb-like structures. Similarly, pairs (or triplets, or more) of vias might extend downward between two pairs (or triplets, or more) of upwardly extending vias; and groupings of different numbers of vias can be used at different places in the sidewalls. While FIGS. 2 and 5 disclose structures in which the transmission lines are formed in the same metallization layer, structures may also be used in which the transmission lines are located in different metallization layers.

Claims

WHAT IS CLAIMED IS;
1. A shielding structure comprising:
first and second comb-like structures defined in a first metallization layer on an integrated circuit, each comb-like structure comprising a plurality of teeth, the teeth of each comb-like structure extending toward the other comb-like structure;
a first plurality of electrically conducting vias extending upward from the first comb-like structure;
a second plurality of electrically conducting vias extending upward from the second comb-like structure;
first and second planar structures in a second metallization layer above the first metallization layer;
a third plurality of electrically conducting vias extending downward from the first planar structure toward the first plurality of electrically conducting vias; and
a fourth plurality of electrically conducting vias extending downward from the second planar structure toward the second plurality of electrically conducting vias, said first and second comb-like structures, said first and second planar structures and said first, second, third, and fourth electrically conducting vias all being at substantially the same potential.
2. The shielding structure of claim 1 wherein the teeth of each comb-like structure extend between the teeth of the other comb-like structure.
3. The shielding structure of claim 1 wherein the electrically conducting vias of the first plurality of vias extend between the electrically conducting vias of the third plurality of vias.
4 The shielding structure of claim 1 further comprising a first signal line located in the second metallization layer between the first and second planar structures.
5. The shielding structure of claim 1 further comprising first and second signal lines located in the second metallization layer between the first and second planar structures.
6. The shielding structure of claim 1 wherein at least one of the planar structures is a comb-like structure.
7. The shielding structure of claim 1 wherein the first and second planar structures are third and fourth comb-like structures, each comb-like structure comprising a plurality of teeth, the teeth of the third comb-like structure and the teeth of the fourth comb-like structure extending toward each other.
8. The shielding structure of claim 7 wherein at least one signal line is located in a third metallization layer between the first and second metallization layers.
9. The shielding structure of claim 7 wherein a first signal line is located in a third metallization layer between the first and second metallization layers and a second signal line is located in a fourth metallization layer between the first and second metallization layers.
10. A shielding structure comprising:
first and second arrays of conductive elements defined in a first metallization layer on an integrated circuit, the conductive elements of the first array being connected together and extending between the conductive elements of the second array, the conductive elements of the second array being connected together;
a first plurality of electrically conducting vias extending upward from the first array;
a second plurality of electrically conducting vias extending upward from the second array;
first and second planar structures in a second metallization layer above the first metallization layer;
a third plurality of electrically conducting vias extending downward from the first planar structure toward the first plurality of electrically conducting vias; and
a fourth plurality of electrically conducting vias extending downward from the second planar structure toward the second plurality of electrically conducting vias, said first and second arrays, said first and second planar structures and said first, second, third, and fourth electrically conducting vias all being at substantially the same potential.
11. The shielding structure of claim 10 wherein the electrically conducting vias of the first plurality of vias extend between the electrically conducting vias of the second plurality of vias.
12. The shielding structure of claim 10 further comprising a first signal line located in the second metallization layer between the first and second planar structures.
13. The shielding structure of claim 10 further comprising first and second signal lines located in the second metallization layer between the first and second planar structures.
14. The shielding structure of claim 10 wherein the first and second planar elements are third and fourth arrays of conductive elements defined in the second metallization layer, the conductive elements of the third array being connected together and extending between the conductive elements of the fourth array, the conductive elements of the fourth array being connected together.
15. The shielding structure of claim 14 wherein at least one signal line is located in a third metallization layer between the first and second metallization layers.
16. The shielding structure of claim 14 wherein a first signal line is located in a third metallization layer between the first and second metallization layers and a second signal line is located in a fourth metallization layer between the first and second metallization layers.
17. A shielding structure comprising:
first and second arrays of conductive elements defined in a first metallization layer on an integrated circuit, the conductive elements of the first array being connected together and extending between the conductive elements of the second array, the conductive elements of the second array being connected together;
third and fourth arrays of conductive elements in a second metallization layer above the first metallization layer, the conductive elements of the third array being connected together and extending between the conductive elements of the fourth array, the conductive elements of the fourth array being connected together; and at least one signal line located in a third metallization layer between the first and second metallization layers,
the first, second, third, and fourth arrays of conductive elements all being at substantially the same potential.
18. The shielding structure of claim 17 wherein the conductive elements in at least one array of conductive elements are connected together in a comb-like structure.
19. The shielding structure of claim 17 further comprising a second signal line located in a fourth metallization layer between the first and second metallization layers.
20. The shielding structure of claim 17 further comprising a second signal line located in the third metallization layer.
EP11745210.2A 2010-02-19 2011-02-17 Shielding structure for transmission lines Active EP2537183B1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US12/709,289 US7999361B1 (en) 2010-02-19 2010-02-19 Shielding structure for transmission lines
PCT/US2011/025194 WO2011103266A2 (en) 2010-02-19 2011-02-17 Shielding structure for transmission lines

Publications (3)

Publication Number Publication Date
EP2537183A2 true EP2537183A2 (en) 2012-12-26
EP2537183A4 EP2537183A4 (en) 2014-03-26
EP2537183B1 EP2537183B1 (en) 2016-04-06

Family

ID=44358544

Family Applications (1)

Application Number Title Priority Date Filing Date
EP11745210.2A Active EP2537183B1 (en) 2010-02-19 2011-02-17 Shielding structure for transmission lines

Country Status (5)

Country Link
US (3) US7999361B1 (en)
EP (1) EP2537183B1 (en)
JP (1) JP5756816B2 (en)
CN (1) CN102844864B (en)
WO (1) WO2011103266A2 (en)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5842368B2 (en) * 2011-04-11 2016-01-13 ソニー株式会社 Semiconductor device
JP2014120710A (en) * 2012-12-19 2014-06-30 Nippon Telegr & Teleph Corp <Ntt> Multilayer high frequency transmission line and manufacturing method therefor
US9245603B2 (en) * 2013-10-21 2016-01-26 Macronix International Co., Ltd. Integrated circuit and operating method for the same
JP6244967B2 (en) * 2014-02-19 2017-12-13 株式会社ソシオネクスト Capacitor array and AD converter
JP2017034155A (en) * 2015-08-04 2017-02-09 大日本印刷株式会社 Display device
CN105762136B (en) * 2016-04-20 2018-12-14 佛山臻智微芯科技有限公司 Differential transmission line shielding construction
US10939541B2 (en) * 2017-03-31 2021-03-02 Huawei Technologies Co., Ltd. Shield structure for a low crosstalk single ended clock distribution circuit
US10236573B2 (en) * 2017-06-20 2019-03-19 Qualcomm Incorporated On-chip coupling capacitor with patterned radio frequency shielding structure for lower loss
US10446898B2 (en) 2017-06-29 2019-10-15 Qualcomm Incorporated On-chip coplanar waveguide having a shielding layer comprising a capacitor formed by sets of interdigitated fingers
JP7082019B2 (en) * 2018-09-18 2022-06-07 株式会社東芝 Solid-state image sensor
GB2612039B (en) * 2021-10-19 2024-01-17 Sat Com Pty Ltd Impedance adaptor
WO2023140090A1 (en) * 2022-01-20 2023-07-27 パナソニックＩｐマネジメント株式会社 Waveguide
US20220217835A1 (en) * 2022-03-25 2022-07-07 Intel Corporation High Density Skip Layer Transmission Line with Plated Slot
EP4712257A1 (en) * 2024-09-13 2026-03-18 Nxp B.V. Controlling impedance and phase shift of a transmission line

Family Cites Families (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6885275B1 (en) * 1998-11-12 2005-04-26 Broadcom Corporation Multi-track integrated spiral inductor
US6870456B2 (en) * 1999-11-23 2005-03-22 Intel Corporation Integrated transformer
JP2002050742A (en) * 2000-07-31 2002-02-15 Nec Corp Semiconductor device and method of manufacturing the same
JP4553461B2 (en) * 2000-08-23 2010-09-29 ルネサスエレクトロニクス株式会社 Semiconductor device, design method thereof and design apparatus
US6496402B1 (en) * 2000-10-17 2002-12-17 Intel Corporation Noise suppression for open bit line DRAM architectures
DE10063376A1 (en) * 2000-12-19 2002-06-20 Philips Corp Intellectual Pty High pressure discharge lamp used as a light source in digital projection systems comprises a longitudinally extended bulb having two throat regions and a vacuum-tight discharge chamber
US6903459B2 (en) * 2001-05-17 2005-06-07 Matsushita Electric Industrial Co., Ltd. High frequency semiconductor device
US6970064B2 (en) * 2001-09-05 2005-11-29 Zhang Minghao Mary Center-tap transformers in integrated circuits
JP3599017B2 (en) * 2001-11-20 2004-12-08 日本電気株式会社 Adjustment method of clock propagation delay time
US6747340B2 (en) * 2002-03-15 2004-06-08 Memx, Inc. Multi-level shielded multi-conductor interconnect bus for MEMS
JP2004031389A (en) * 2002-06-21 2004-01-29 Fujitsu Ltd Semiconductor circuit design method, semiconductor circuit design device, program, and semiconductor device
JP3906139B2 (en) * 2002-10-16 2007-04-18 株式会社東芝 Magnetic random access memory
JP2004140308A (en) * 2002-10-16 2004-05-13 Adorinkusu:Kk Printed wiring board for high-speed signal using slit method
CA2418674A1 (en) * 2003-02-07 2004-08-07 Tak Shun Cheung Transmission lines and transmission line components with wavelength reduction and shielding
JP4141881B2 (en) * 2003-04-04 2008-08-27 シャープ株式会社 Integrated circuit
JP4619705B2 (en) * 2004-01-15 2011-01-26 株式会社東芝 Semiconductor device
JP3793202B2 (en) * 2004-02-02 2006-07-05 キヤノン株式会社 Solid-state imaging device
US7123118B2 (en) * 2004-03-08 2006-10-17 Wemtec, Inc. Systems and methods for blocking microwave propagation in parallel plate structures utilizing cluster vias
DE102004014752B4 (en) * 2004-03-25 2008-11-20 Infineon Technologies Ag Semiconductor device with coreless converter and half-bridge
WO2006001389A1 (en) * 2004-06-28 2006-01-05 Mitsubishi Denki Kabushiki Kaisha Multilayer dielectric substrate and semiconductor package
JP4099672B2 (en) * 2004-12-21 2008-06-11 セイコーエプソン株式会社 Semiconductor device
US20060139117A1 (en) * 2004-12-23 2006-06-29 Brunker David L Multi-channel waveguide structure
US7576382B2 (en) * 2005-02-02 2009-08-18 Ricoh Company, Ltd. Semiconductor integrated device and method of providing shield interconnection therein
JP5008872B2 (en) * 2005-02-02 2012-08-22 株式会社リコー Semiconductor integrated device
JP5211694B2 (en) * 2006-01-04 2013-06-12 富士通株式会社 Arrangement method of shield line in semiconductor integrated circuit, semiconductor integrated circuit design apparatus, and semiconductor integrated circuit design program
US7755457B2 (en) * 2006-02-07 2010-07-13 Harris Corporation Stacked stripline circuits
JP2007306290A (en) * 2006-05-11 2007-11-22 Univ Of Tokyo Transmission line
US8193878B2 (en) 2008-06-24 2012-06-05 International Business Machines Corporation Structure, structure and method for providing an on-chip variable delay transmission line with fixed characteristic impedance
US8022784B2 (en) * 2008-07-07 2011-09-20 Korea Advanced Institute Of Science And Technology (Kaist) Planar transmission line-to-waveguide transition apparatus having an embedded bent stub

Also Published As

Publication number Publication date
US20140048915A1 (en) 2014-02-20
JP5756816B2 (en) 2015-07-29
JP2013520797A (en) 2013-06-06
EP2537183B1 (en) 2016-04-06
US8823135B2 (en) 2014-09-02
US8558355B2 (en) 2013-10-15
CN102844864A (en) 2012-12-26
CN102844864B (en) 2015-08-26
US20110204493A1 (en) 2011-08-25
US20110291248A1 (en) 2011-12-01
EP2537183A4 (en) 2014-03-26
WO2011103266A3 (en) 2011-11-24
WO2011103266A2 (en) 2011-08-25
US7999361B1 (en) 2011-08-16

Similar Documents

Publication Publication Date Title
US7999361B1 (en) Shielding structure for transmission lines
US8324979B2 (en) Coupled microstrip lines with ground planes having ground strip shields and ground conductor extensions
US8279025B2 (en) Slow-wave coaxial transmission line having metal shield strips and dielectric strips with minimum dimensions
KR100939648B1 (en) Multilayer Inductors Formed on Semiconductor Substrates
US8000083B2 (en) Scalable integrated circuit high density capacitors
JP5054019B2 (en) Trench capacitor device suitable for separating applications in high frequency operation
US8841771B2 (en) Semiconductor device
CN101771038B (en) Integrated circuit structure
US9831173B2 (en) Slot-shielded coplanar strip-line compatible with CMOS processes
US8922293B2 (en) Microstrip lines with tunable characteristic impedance and wavelength
US8022784B2 (en) Planar transmission line-to-waveguide transition apparatus having an embedded bent stub
CA2550882A1 (en) Capacitor
CN101814645B (en) Coupled microstrip line structure and its manufacturing method
CN116387787B (en) Three-dimensional structured miniature Wilkinson power divider
JP2006042098A (en) High frequency wiring board
US6975189B1 (en) On-chip multilayer metal shielded transmission line
KR20090036030A (en) Transmission line of multilayer metal structure and forming method thereof
JP2007027518A (en) High frequency circuit module and laminated high frequency circuit module

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

17P Request for examination filed

Effective date: 20120829

AK Designated contracting states

Kind code of ref document: A2

Designated state(s): AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR

DAX Request for extension of the european patent (deleted)
A4 Supplementary search report drawn up and despatched

Effective date: 20140226

RIC1 Information provided on ipc code assigned before grant

Ipc: H01L 27/04 20060101AFI20140220BHEP

REG Reference to a national code

Ref country code: DE

Ref legal event code: R079

Ref document number: 602011024946

Country of ref document: DE

Free format text: PREVIOUS MAIN CLASS: H01L0027040000

Ipc: H01L0023522000

GRAP Despatch of communication of intention to grant a patent

Free format text: ORIGINAL CODE: EPIDOSNIGR1

RIC1 Information provided on ipc code assigned before grant

Ipc: H01L 23/522 20060101AFI20150805BHEP

INTG Intention to grant announced

Effective date: 20150831

GRAS Grant fee paid

Free format text: ORIGINAL CODE: EPIDOSNIGR3

GRAA (expected) grant

Free format text: ORIGINAL CODE: 0009210

AK Designated contracting states

Kind code of ref document: B1

Designated state(s): AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR

REG Reference to a national code

Ref country code: GB

Ref legal event code: FG4D

REG Reference to a national code

Ref country code: AT

Ref legal event code: REF

Ref document number: 788607

Country of ref document: AT

Kind code of ref document: T

Effective date: 20160415

Ref country code: CH

Ref legal event code: EP

REG Reference to a national code

Ref country code: IE

Ref legal event code: FG4D

REG Reference to a national code

Ref country code: DE

Ref legal event code: R096

Ref document number: 602011024946

Country of ref document: DE

REG Reference to a national code

Ref country code: LT

Ref legal event code: MG4D

Ref country code: NL

Ref legal event code: MP

Effective date: 20160406

REG Reference to a national code

Ref country code: AT

Ref legal event code: MK05

Ref document number: 788607

Country of ref document: AT

Kind code of ref document: T

Effective date: 20160406

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: NL

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20160406

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: LT

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20160406

Ref country code: NO

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20160706

Ref country code: FI

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20160406

Ref country code: IS

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20160806

Ref country code: PL

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20160406

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: LV

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20160406

Ref country code: AT

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20160406

Ref country code: RS

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20160406

Ref country code: HR

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20160406

Ref country code: ES

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20160406

Ref country code: PT

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20160808

Ref country code: SE

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20160406

Ref country code: GR

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20160707

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: BE

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20160406

Ref country code: IT

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20160406

REG Reference to a national code

Ref country code: DE

Ref legal event code: R097

Ref document number: 602011024946

Country of ref document: DE

REG Reference to a national code

Ref country code: FR

Ref legal event code: PLFP

Year of fee payment: 7

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: SK

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20160406

Ref country code: DK

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20160406

Ref country code: EE

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20160406

Ref country code: RO

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20160406

Ref country code: CZ

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20160406

PLBE No opposition filed within time limit

Free format text: ORIGINAL CODE: 0009261

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: SM

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20160406

26N No opposition filed

Effective date: 20170110

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: SI

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20160406

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: MC

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20160406

REG Reference to a national code

Ref country code: CH

Ref legal event code: PL

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: LI

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20170228

Ref country code: CH

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20170228

REG Reference to a national code

Ref country code: IE

Ref legal event code: MM4A

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: LU

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20170217

REG Reference to a national code

Ref country code: FR

Ref legal event code: PLFP

Year of fee payment: 8

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: IE

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20170217

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: MT

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20170217

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: AL

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20160406

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: HU

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT; INVALID AB INITIO

Effective date: 20110217

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: BG

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20160406

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: CY

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20160406

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: MK

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20160406

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: TR

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20160406

P01 Opt-out of the competence of the unified patent court (upc) registered

Effective date: 20230531

REG Reference to a national code

Ref country code: DE

Ref legal event code: R079

Ref document number: 602011024946

Country of ref document: DE

Free format text: PREVIOUS MAIN CLASS: H01L0023522000

Ipc: H10W0020400000

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: GB

Payment date: 20260216

Year of fee payment: 16

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: DE

Payment date: 20260217

Year of fee payment: 16

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: FR

Payment date: 20260219

Year of fee payment: 16